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https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-22 05:59:15 +01:00
delayed address latching cycle - might break other builds, needs testing
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093aabe940
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@ -20,16 +20,16 @@ module n64_pi (
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logic [1:0] n64_reset_ff;
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logic [1:0] n64_reset_ff;
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logic [1:0] n64_nmi_ff;
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logic [1:0] n64_nmi_ff;
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logic [2:0] n64_pi_alel_ff;
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logic [3:0] n64_pi_alel_ff;
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logic [2:0] n64_pi_aleh_ff;
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logic [3:0] n64_pi_aleh_ff;
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logic [1:0] n64_pi_read_ff;
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logic [1:0] n64_pi_read_ff;
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logic [2:0] n64_pi_write_ff;
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logic [2:0] n64_pi_write_ff;
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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n64_reset_ff <= {n64_reset_ff[0], n64_reset};
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n64_reset_ff <= {n64_reset_ff[0], n64_reset};
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n64_nmi_ff <= {n64_nmi_ff[0], n64_nmi};
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n64_nmi_ff <= {n64_nmi_ff[0], n64_nmi};
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n64_pi_aleh_ff <= {n64_pi_aleh_ff[1:0], n64_pi_aleh};
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n64_pi_aleh_ff <= {n64_pi_aleh_ff[2:0], n64_pi_aleh};
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n64_pi_alel_ff <= {n64_pi_alel_ff[1:0], n64_pi_alel};
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n64_pi_alel_ff <= {n64_pi_alel_ff[2:0], n64_pi_alel};
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n64_pi_read_ff <= {n64_pi_read_ff[0], n64_pi_read};
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n64_pi_read_ff <= {n64_pi_read_ff[0], n64_pi_read};
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n64_pi_write_ff <= {n64_pi_write_ff[1:0], n64_pi_write};
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n64_pi_write_ff <= {n64_pi_write_ff[1:0], n64_pi_write};
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end
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end
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@ -44,8 +44,8 @@ module n64_pi (
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always_comb begin
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always_comb begin
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pi_reset = n64_reset_ff[1];
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pi_reset = n64_reset_ff[1];
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pi_nmi = n64_nmi_ff[1];
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pi_nmi = n64_nmi_ff[1];
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pi_aleh = n64_pi_aleh_ff[2];
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pi_aleh = n64_pi_aleh_ff[3];
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pi_alel = n64_pi_alel_ff[2];
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pi_alel = n64_pi_alel_ff[3];
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pi_read = n64_pi_read_ff[1];
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pi_read = n64_pi_read_ff[1];
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pi_write = n64_pi_write_ff[2];
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pi_write = n64_pi_write_ff[2];
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end
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end
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@ -250,6 +250,7 @@ module n64_pi (
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logic [15:0] read_fifo_rdata;
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logic [15:0] read_fifo_rdata;
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logic read_fifo_wait;
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logic read_fifo_wait;
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logic [15:0] read_fifo_buffer;
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n64_pi_fifo read_fifo_inst (
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n64_pi_fifo read_fifo_inst (
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.clk(clk),
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.clk(clk),
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@ -268,6 +269,7 @@ module n64_pi (
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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read_fifo_read <= 1'b0;
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read_fifo_read <= 1'b0;
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read_fifo_buffer <= read_fifo_rdata;
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if (reset || !pi_reset || alel_op) begin
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if (reset || !pi_reset || alel_op) begin
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read_fifo_wait <= 1'b0;
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read_fifo_wait <= 1'b0;
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@ -279,14 +281,14 @@ module n64_pi (
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read_fifo_wait <= 1'b1;
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read_fifo_wait <= 1'b1;
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end else begin
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end else begin
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read_fifo_read <= 1'b1;
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read_fifo_read <= 1'b1;
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n64_pi_dq_out <= read_fifo_rdata;
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n64_pi_dq_out <= read_fifo_buffer;
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end
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end
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end
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end
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if (!read_fifo_empty && read_fifo_wait) begin
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if (!read_fifo_empty && read_fifo_wait) begin
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read_fifo_read <= 1'b1;
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read_fifo_read <= 1'b1;
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read_fifo_wait <= 1'b0;
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read_fifo_wait <= 1'b0;
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n64_pi_dq_out <= read_fifo_rdata;
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n64_pi_dq_out <= read_fifo_buffer;
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end
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end
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end
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end
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