mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2025-01-13 04:59:09 +01:00
small cleanup
This commit is contained in:
parent
7d8614e456
commit
ad88fefae5
@ -146,5 +146,5 @@ void boot (boot_params_t *params) {
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"t3"
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"t3"
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);
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);
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while (1);
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while (true);
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}
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}
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@ -19,5 +19,5 @@ void error_display (const char *fmt, ...) {
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va_end(args);
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va_end(args);
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display_printf("\n");
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display_printf("\n");
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while (1);
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while (true);
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}
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}
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@ -120,6 +120,10 @@ exception_fatal:
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exception_interrupt:
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exception_interrupt:
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andi $a0, $t0, C0_CR_IP_MASK
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andi $a0, $t0, C0_CR_IP_MASK
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srl $a0, C0_CR_IP_BIT
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srl $a0, C0_CR_IP_BIT
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mfc0 $t0, C0_STATUS
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andi $t0, C0_SR_IM_MASK
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srl $t0, C0_SR_IM_BIT
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and $a0, $t0
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jal exception_interrupt_handler
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jal exception_interrupt_handler
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exception_restore:
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exception_restore:
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@ -48,5 +48,5 @@ void exception_fatal_handler (uint32_t exception_code, exception_t *e) {
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display_printf(" t8: 0x%08lX t9: 0x%08lX k0: 0x%08lX k1: 0x%08lX\n", e->t8.u32, e->t9.u32, e->k0.u32, e->k1.u32);
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display_printf(" t8: 0x%08lX t9: 0x%08lX k0: 0x%08lX k1: 0x%08lX\n", e->t8.u32, e->t9.u32, e->k0.u32, e->k1.u32);
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display_printf(" gp: 0x%08lX sp: 0x%08lX s8: 0x%08lX ra: 0x%08lX\n\n", e->gp.u32, e->sp.u32, e->s8.u32, e->ra.u32);
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display_printf(" gp: 0x%08lX sp: 0x%08lX s8: 0x%08lX ra: 0x%08lX\n\n", e->gp.u32, e->sp.u32, e->s8.u32, e->ra.u32);
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while (1);
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while (true);
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}
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}
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@ -5,6 +5,7 @@
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typedef enum {
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typedef enum {
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INTERRUPT_NONE = 0,
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INTERRUPT_SW_0 = (1 << 0),
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INTERRUPT_SW_0 = (1 << 0),
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INTERRUPT_SW_1 = (1 << 1),
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INTERRUPT_SW_1 = (1 << 1),
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INTERRUPT_RCP = (1 << 2),
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INTERRUPT_RCP = (1 << 2),
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@ -16,54 +17,71 @@ typedef enum {
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} interrupt_t;
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} interrupt_t;
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static void exception_interrupt_unhandled (uint8_t interrupt) {
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void exception_interrupt_handler (uint8_t interrupt) {
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display_init((uint32_t *) (&assets_sc64_logo_640_240_dimmed));
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if (interrupt == INTERRUPT_NONE) {
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display_init((uint32_t *) (&assets_sc64_logo_640_240_dimmed));
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version_print();
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version_print();
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display_printf("[ Unhandled interrupt ]\n");
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display_printf("[ Empty interrupt ]\n");
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display_printf("Pending (0x%02X):\n", interrupt);
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display_printf("There is no interrupt to handle\n");
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for (int i = 0; i < 8; i++) {
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switch (interrupt & (1 << i)) {
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while (true);
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case INTERRUPT_SW_0: display_printf(" Software interrupt (0)\n"); break;
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case INTERRUPT_SW_1: display_printf(" Software interrupt (1)\n"); break;
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case INTERRUPT_RCP: display_printf(" RCP interrupt (2)\n"); break;
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case INTERRUPT_CART: display_printf(" CART interrupt (3)\n"); break;
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case INTERRUPT_PRENMI: display_printf(" Pre NMI interrupt (4)\n"); break;
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case INTERRUPT_HW_5: display_printf(" Hardware interrupt (5)\n"); break;
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case INTERRUPT_HW_6: display_printf(" Hardware interrupt (6)\n"); break;
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case INTERRUPT_TIMER: display_printf(" Timer interrupt (7)\n"); break;
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default: break;
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}
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}
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}
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while (1);
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}
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void exception_interrupt_handler (uint8_t interrupt) {
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if (interrupt & INTERRUPT_CART) {
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if (interrupt & INTERRUPT_CART) {
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interrupt &= ~(INTERRUPT_CART);
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sc64_irq_t irq = sc64_irq_pending();
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sc64_irq_t irq = sc64_irq_pending();
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if (irq != SC64_IRQ_NONE) {
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if (irq != SC64_IRQ_NONE) {
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return sc64_irq_callback(irq);
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sc64_irq_callback(irq);
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}
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}
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}
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}
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if (interrupt & INTERRUPT_PRENMI) {
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if (interrupt & INTERRUPT_PRENMI) {
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interrupt &= ~(INTERRUPT_PRENMI);
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if (display_ready()) {
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if (display_ready()) {
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display_init(NULL);
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display_init(NULL);
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display_printf("Resetting...\n");
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display_printf("Resetting...\n");
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}
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}
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while (1);
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while (true);
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}
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}
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if (interrupt & INTERRUPT_TIMER) {
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if (interrupt & INTERRUPT_TIMER) {
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interrupt &= ~(INTERRUPT_TIMER);
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display_init((uint32_t *) (&assets_sc64_logo_640_240_dimmed));
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display_init((uint32_t *) (&assets_sc64_logo_640_240_dimmed));
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version_print();
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version_print();
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display_printf("[ Watchdog ]\n");
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display_printf("[ Watchdog ]\n");
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display_printf("SC64 bootloader did not finish loading in 5 seconds\n");
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display_printf("SC64 bootloader did not finish loading in 5 seconds\n");
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while (1);
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while (true);
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}
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}
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exception_interrupt_unhandled(interrupt);
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if (interrupt != INTERRUPT_NONE) {
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display_init((uint32_t *) (&assets_sc64_logo_640_240_dimmed));
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version_print();
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display_printf("[ Unhandled interrupt ]\n");
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display_printf("Pending (0x%02X):\n", interrupt);
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for (int i = 0; i < 8; i++) {
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switch (interrupt & (1 << i)) {
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case INTERRUPT_SW_0: display_printf(" (0) Software interrupt\n"); break;
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case INTERRUPT_SW_1: display_printf(" (1) Software interrupt\n"); break;
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case INTERRUPT_RCP: display_printf(" (2) RCP interrupt\n"); break;
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case INTERRUPT_CART: display_printf(" (3) CART interrupt\n"); break;
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case INTERRUPT_PRENMI: display_printf(" (4) Pre NMI interrupt\n"); break;
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case INTERRUPT_HW_5: display_printf(" (5) Hardware interrupt\n"); break;
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case INTERRUPT_HW_6: display_printf(" (6) Hardware interrupt\n"); break;
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case INTERRUPT_TIMER: display_printf(" (7) Timer interrupt\n"); break;
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default: break;
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}
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}
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while (true);
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}
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}
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}
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@ -48,6 +48,9 @@
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#define C0_SR_CU2 (1 << 30)
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#define C0_SR_CU2 (1 << 30)
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#define C0_SR_CU3 (1 << 31)
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#define C0_SR_CU3 (1 << 31)
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#define C0_SR_IM_MASK (C0_SR_IM7 | C0_SR_IM6 | C0_SR_IM5 | C0_SR_IM4 | C0_SR_IM3 | C0_SR_IM2 | C0_SR_IM1 | C0_SR_IM0)
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#define C0_SR_IM_BIT (8)
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#define C0_CR_EC0 (1 << 2)
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#define C0_CR_EC0 (1 << 2)
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#define C0_CR_EC1 (1 << 3)
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#define C0_CR_EC1 (1 << 3)
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