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bram extension

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This commit is contained in:
Mateusz Faderewski 2024-09-29 02:43:48 +02:00
parent 5aa250f3ef
commit b54fcad8bc
6 changed files with 23 additions and 22 deletions
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10
docs/01_memory_map.md
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@ -25,9 +25,9 @@ This mapping is used internally by FPGA/μC and when accessing flashcart from US
| Flash [1] | `0x0400_0000` | 16 MiB | RW/R | Flash |
| Data buffer | `0x0500_0000` | 8 kiB | RW | BlockRAM |
| EEPROM | `0x0500_2000` | 2 kiB | RW | BlockRAM |
| 64DD buffer | `0x0500_2800` | 256 bytes | RW | BlockRAM |
| FlashRAM buffer [2] | `0x0500_2900` | 128 bytes | R | BlockRAM |
| N/A [3] | `0x0500_2980` | to `0x07FF_FFFF` | R | N/A |
| 64DD/MCU buffer | `0x0500_2800` | 1 kiB | RW | BlockRAM |
| FlashRAM buffer [2] | `0x0500_2C00` | 128 bytes | R | BlockRAM |
| N/A [3] | `0x0500_2C80` | to `0x07FF_FFFF` | R | N/A |
- Note [1]: Flash memory region `0x04E0_0000` - `0x04FD_FFFF` is write protected as it contains N64 bootloader. This section can be overwritten only via firmware update process.
- Note [2]: Due to BlockRAM usage optimization this section is read only.
@ -53,8 +53,8 @@ This mapping is used when accessing flashcart from N64 side.
| ROM shadow [7] | `0x1FFC_0000` | 128 kiB | R | `0x04FE_0000` | Flash | mem bus | SC64 register access is enabled |
| Data buffer | `0x1FFE_0000` | 8 kiB | RW | `0x0500_0000` | Block RAM | mem bus | SC64 register access is enabled |
| EEPROM | `0x1FFE_2000` | 2 kiB | RW | `0x0500_2000` | Block RAM | mem bus | SC64 register access is enabled |
| 64DD buffer [8] | `0x1FFE_2800` | 256 bytes | RW | `0x0500_2800` | Block RAM | mem bus | SC64 register access is enabled |
| FlashRAM buffer [8] | `0x1FFE_2900` | 128 bytes | R | `0x0500_2900` | Block RAM | mem bus | SC64 register access is enabled |
| 64DD/MCU buffer [8] | `0x1FFE_2800` | 1 kiB | RW | `0x0500_2800` | Block RAM | mem bus | SC64 register access is enabled |
| FlashRAM buffer [8] | `0x1FFE_2C00` | 128 bytes | R | `0x0500_2C00` | Block RAM | mem bus | SC64 register access is enabled |
| SC64 registers | `0x1FFF_0000` | 28 bytes | RW | N/A | Flashcart Interface | reg bus | SC64 register access is enabled |
- Note [1]: 64DD IPL share SDRAM memory space with ROM (last 4 MiB minus 128 kiB for saves). Write access is always disabled for this section.

22
fw/rtl/memory/memory_bram.sv
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@ -36,11 +36,11 @@ module memory_bram (
eeprom_selected = 1'b0;
dd_selected = 1'b0;
flashram_selected = 1'b0;
if (mem_bus.address[25:24] == 2'b01 && mem_bus.address[23:14] == 10'd0) begin
buffer_selected = mem_bus.address[13] == 1'b0;
eeprom_selected = mem_bus.address[13:11] == 3'b100;
dd_selected = mem_bus.address[13:8] == 6'b101000;
flashram_selected = mem_bus.address[13:7] == 7'b1010010;
if (mem_bus.address[26:24] == 3'h5) begin
buffer_selected = (mem_bus.address[23:0] >= 24'h00_0000 && mem_bus.address[23:0] < 24'h00_2000);
eeprom_selected = (mem_bus.address[23:0] >= 24'h00_2000 && mem_bus.address[23:0] < 24'h00_2800);
dd_selected = (mem_bus.address[23:0] >= 24'h00_2800 && mem_bus.address[23:0] < 24'h00_2C00);
flashram_selected = (mem_bus.address[23:0] >= 24'h00_2C00 && mem_bus.address[23:0] < 24'h00_2C80);
end
end
@ -112,26 +112,26 @@ module memory_bram (
end
// DD memory
// 64DD/MCU buffer memory
logic [15:0] dd_bram [0:127];
logic [15:0] dd_bram [0:511];
logic [15:0] dd_bram_rdata;
always_ff @(posedge clk) begin
if (write && dd_selected) begin
dd_bram[mem_bus.address[7:1]] <= mem_bus.wdata;
dd_bram[mem_bus.address[9:1]] <= mem_bus.wdata;
end
if (n64_scb.dd_write) begin
dd_bram[n64_scb.dd_address] <= n64_scb.dd_wdata;
dd_bram[{2'b00, n64_scb.dd_address}] <= n64_scb.dd_wdata;
end
end
always_ff @(posedge clk) begin
dd_bram_rdata <= dd_bram[mem_bus.address[7:1]];
dd_bram_rdata <= dd_bram[mem_bus.address[9:1]];
end
always_ff @(posedge clk) begin
n64_scb.dd_rdata <= dd_bram[n64_scb.dd_address];
n64_scb.dd_rdata <= dd_bram[{2'b00, n64_scb.dd_address}];
end

2
sw/controller/src/flashram.c
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@ -6,7 +6,7 @@
#define FLASHRAM_SECTOR_SIZE (16 * 1024)
#define FLASHRAM_PAGE_SIZE (128)
#define FLASHRAM_ADDRESS (0x03FE0000UL)
#define FLASHRAM_BUFFER_ADDRESS (0x05002900UL)
#define FLASHRAM_BUFFER_ADDRESS (0x05002C00UL)
typedef enum {

2
sw/controller/src/sd.c
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@ -4,7 +4,7 @@
#include "timer.h"
#define SD_INIT_BUFFER_ADDRESS (0x05002800UL)
#define SD_INIT_BUFFER_ADDRESS (0x05002BB8UL)
#define BYTE_SWAP_ADDRESS_END (0x05000000UL)
#define CMD6_ARG_CHECK_HS (0x00FFFFF1UL)

2
sw/controller/src/usb.c
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@ -17,7 +17,7 @@
#define BOOTLOADER_ADDRESS (0x04E00000UL)
#define BOOTLOADER_LENGTH (1920 * 1024)
#define MEMORY_LENGTH (0x05002980UL)
#define MEMORY_LENGTH (0x05002C80UL)
#define RX_FLUSH_ADDRESS (0x07F00000UL)
#define RX_FLUSH_LENGTH (1 * 1024 * 1024)

7
sw/deployer/src/sc64/mod.rs
View File

@ -109,7 +109,7 @@ const FIRMWARE_UPDATE_TIMEOUT: Duration = Duration::from_secs(90);
const ISV_BUFFER_LENGTH: usize = 64 * 1024;
pub const MEMORY_LENGTH: usize = 0x0500_2980;
pub const MEMORY_LENGTH: usize = 0x0500_2C80;
const MEMORY_CHUNK_LENGTH: usize = 1 * 1024 * 1024;
@ -679,12 +679,13 @@ impl SC64 {
}
pub fn get_sd_card_info(&mut self) -> Result<SdCardInfo, Error> {
const SD_CARD_INFO_BUFFER_ADDRESS: u32 = 0x0500_2BE0;
let info =
match self.command_sd_card_operation(SdCardOp::GetInfo(SD_CARD_BUFFER_ADDRESS))? {
match self.command_sd_card_operation(SdCardOp::GetInfo(SD_CARD_INFO_BUFFER_ADDRESS))? {
SdCardOpPacket {
result: SdCardResult::OK,
status: _,
} => self.command_memory_read(SD_CARD_BUFFER_ADDRESS, 32)?,
} => self.command_memory_read(SD_CARD_INFO_BUFFER_ADDRESS, 32)?,
packet => {
return Err(Error::new(
format!("Couldn't get SD card info registers: {}", packet.result).as_str(),