diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..4f9a394 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +**/.vscode diff --git a/.media/sc64_clean_pcb.jpg b/.media/sc64_clean_pcb.jpg new file mode 100644 index 0000000..bcd4ff9 Binary files /dev/null and b/.media/sc64_clean_pcb.jpg differ diff --git a/.media/sc64_in_n64.jpg b/.media/sc64_in_n64.jpg new file mode 100644 index 0000000..60f234e Binary files /dev/null and b/.media/sc64_in_n64.jpg differ diff --git a/.media/sc64_on_table.jpg b/.media/sc64_on_table.jpg new file mode 100644 index 0000000..80b8538 Binary files /dev/null and b/.media/sc64_on_table.jpg differ diff --git a/README.md b/README.md index e69de29..9e1b529 100644 --- a/README.md +++ b/README.md @@ -0,0 +1,48 @@ +# SummerCollection + +A collection of hardware, firmware and software designs of SummerCart64 - Nintendo 64 FlashCart/DevKit. + +## Project parts + +### Hardware + +Folder **`hw`** contains PCB design made in Autodesk Eagle. + +### Firmware + +Folder **`fw`** contains firmware written in Verilog for Intel MAX10 FPGA. + +### Software + +Folder **`sw`** contains several helper programs that makes flash cart work all together, including bootloader and PC communication software. + +## What works + +Currently hardware implements basic functionality for playing games - ROM emulation, bootloader and PC communication. You can send any ROM to the SDRAM from PC and if game doesn't check for save hardware then it most likely will work. Bootloader does all the work necessary to setup the console registers for specific CIC chip that game requires. + +## Issues + +There are several issues with the project at the moment in order of importance: + +- Documentation is not finished for most of the modules. +- No save hardware implementation. +- No SD card interface hardware implementation. +- No RTC hardware implementation. +- Currently PC communication disables N64 PI interface completely as there's no bus arbiter implemented. +- No save write-back to SD card hardware implementation. +- PCB schematic is unorganized and some component values are missing. +- There's no BOM for hardware. +- PCB design and necessary components needs to be reconsidered for next version. +- No CIC implementation in FPGA, current solution uses [UltraCIC II](https://github.com/perkinsb1024/UltraCIC-II) based on ATtiny45. + +## What's next + +Current goal is to implement EEPROM save emulation. + +## Finished sample + +![SummerCart64 clean PCB](.media/sc64_clean_pcb.jpg) + +![SummerCart64 on table](.media/sc64_on_table.jpg) + +![SummerCart64 in partialy disassembled Nintendo 64](.media/sc64_in_n64.jpg) diff --git a/fw/.gitignore b/fw/.gitignore new file mode 100644 index 0000000..ac1e7c7 --- /dev/null +++ b/fw/.gitignore @@ -0,0 +1,7 @@ +/db +/greybox_tmp +/incremental_db +/output_files +*.qws +*.rpt +*.txt diff --git a/fw/README.md b/fw/README.md index e69de29..8b9627d 100644 --- a/fw/README.md +++ b/fw/README.md @@ -0,0 +1,7 @@ +# SummerCart64 Firmware + +A FPGA firmware written in Verilog for SummerCart64. + +## TODO + +- Expand documentation diff --git a/fw/SummerCart64.qpf b/fw/SummerCart64.qpf new file mode 100644 index 0000000..2e8f544 --- /dev/null +++ b/fw/SummerCart64.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition +# Date created = 23:45:19 July 29, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "20.1" +DATE = "23:45:19 July 29, 2020" + +# Revisions + +PROJECT_REVISION = "SummerCart64" diff --git a/fw/SummerCart64.qsf b/fw/SummerCart64.qsf new file mode 100644 index 0000000..a3d3005 --- /dev/null +++ b/fw/SummerCart64.qsf @@ -0,0 +1,208 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition +# Date created = 23:45:19 July 29, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# SummerCart64_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M08SCE144C8G +set_global_assignment -name TOP_LEVEL_ENTITY top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:45:19 JULY 29, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_location_assignment PIN_26 -to i_clk +set_location_assignment PIN_98 -to io_sdram_dq[0] +set_location_assignment PIN_97 -to io_sdram_dq[1] +set_location_assignment PIN_96 -to io_sdram_dq[2] +set_location_assignment PIN_93 -to io_sdram_dq[3] +set_location_assignment PIN_92 -to io_sdram_dq[4] +set_location_assignment PIN_91 -to io_sdram_dq[5] +set_location_assignment PIN_90 -to io_sdram_dq[6] +set_location_assignment PIN_89 -to io_sdram_dq[7] +set_location_assignment PIN_99 -to io_sdram_dq[8] +set_location_assignment PIN_100 -to io_sdram_dq[9] +set_location_assignment PIN_101 -to io_sdram_dq[10] +set_location_assignment PIN_102 -to io_sdram_dq[11] +set_location_assignment PIN_105 -to io_sdram_dq[12] +set_location_assignment PIN_106 -to io_sdram_dq[13] +set_location_assignment PIN_110 -to io_sdram_dq[14] +set_location_assignment PIN_111 -to io_sdram_dq[15] +set_location_assignment PIN_79 -to o_sdram_a[0] +set_location_assignment PIN_78 -to o_sdram_a[1] +set_location_assignment PIN_77 -to o_sdram_a[2] +set_location_assignment PIN_76 -to o_sdram_a[3] +set_location_assignment PIN_61 -to o_sdram_a[4] +set_location_assignment PIN_62 -to o_sdram_a[5] +set_location_assignment PIN_64 -to o_sdram_a[6] +set_location_assignment PIN_65 -to o_sdram_a[7] +set_location_assignment PIN_66 -to o_sdram_a[8] +set_location_assignment PIN_69 -to o_sdram_a[9] +set_location_assignment PIN_80 -to o_sdram_a[10] +set_location_assignment PIN_70 -to o_sdram_a[11] +set_location_assignment PIN_74 -to o_sdram_a[12] +set_location_assignment PIN_84 -to o_sdram_ba[0] +set_location_assignment PIN_81 -to o_sdram_ba[1] +set_location_assignment PIN_75 -to o_sdram_clk +set_location_assignment PIN_85 -to o_sdram_cs +set_location_assignment PIN_87 -to o_sdram_cas +set_location_assignment PIN_86 -to o_sdram_ras +set_location_assignment PIN_88 -to o_sdram_we +set_location_assignment PIN_114 -to o_sd_clk +set_location_assignment PIN_118 -to io_sd_cmd +set_location_assignment PIN_119 -to io_sd_dat[3] +set_location_assignment PIN_120 -to io_sd_dat[2] +set_location_assignment PIN_112 -to io_sd_dat[1] +set_location_assignment PIN_113 -to io_sd_dat[0] +set_location_assignment PIN_134 -to o_flash_cs +set_location_assignment PIN_131 -to o_flash_clk +set_location_assignment PIN_132 -to io_flash_dq[3] +set_location_assignment PIN_136 -to io_flash_dq[2] +set_location_assignment PIN_135 -to io_flash_dq[1] +set_location_assignment PIN_130 -to io_flash_dq[0] +set_location_assignment PIN_122 -to o_sram_clk +set_location_assignment PIN_123 -to io_sram_dq[3] +set_location_assignment PIN_127 -to io_sram_dq[2] +set_location_assignment PIN_126 -to io_sram_dq[1] +set_location_assignment PIN_121 -to io_sram_dq[0] +set_location_assignment PIN_124 -to o_sram_cs +set_location_assignment PIN_24 -to io_n64_si_dq +set_location_assignment PIN_25 -to i_n64_nmi +set_location_assignment PIN_27 -to i_n64_reset +set_location_assignment PIN_28 -to i_n64_si_clk +set_location_assignment PIN_46 -to i_n64_pi_aleh +set_location_assignment PIN_50 -to i_n64_pi_alel +set_location_assignment PIN_47 -to i_n64_pi_read +set_location_assignment PIN_48 -to i_n64_pi_write +set_location_assignment PIN_60 -to io_n64_pi_ad[0] +set_location_assignment PIN_58 -to io_n64_pi_ad[1] +set_location_assignment PIN_56 -to io_n64_pi_ad[2] +set_location_assignment PIN_54 -to io_n64_pi_ad[3] +set_location_assignment PIN_44 -to io_n64_pi_ad[4] +set_location_assignment PIN_41 -to io_n64_pi_ad[5] +set_location_assignment PIN_38 -to io_n64_pi_ad[6] +set_location_assignment PIN_32 -to io_n64_pi_ad[7] +set_location_assignment PIN_33 -to io_n64_pi_ad[8] +set_location_assignment PIN_39 -to io_n64_pi_ad[9] +set_location_assignment PIN_43 -to io_n64_pi_ad[10] +set_location_assignment PIN_45 -to io_n64_pi_ad[11] +set_location_assignment PIN_52 -to io_n64_pi_ad[12] +set_location_assignment PIN_55 -to io_n64_pi_ad[13] +set_location_assignment PIN_57 -to io_n64_pi_ad[14] +set_location_assignment PIN_59 -to io_n64_pi_ad[15] +set_location_assignment PIN_13 -to i_ftdi_do +set_location_assignment PIN_14 -to o_ftdi_di +set_location_assignment PIN_12 -to i_ftdi_clk +set_location_assignment PIN_15 -to i_ftdi_cs +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to o_sdram_clk +set_location_assignment PIN_29 -to i_n64_cic_clk +set_location_assignment PIN_30 -to io_n64_cic_dq +set_location_assignment PIN_138 -to io_pmod[0] +set_location_assignment PIN_140 -to io_pmod[1] +set_location_assignment PIN_141 -to io_pmod[2] +set_location_assignment PIN_6 -to io_pmod[3] +set_location_assignment PIN_7 -to io_pmod[4] +set_location_assignment PIN_8 -to io_pmod[5] +set_location_assignment PIN_10 -to io_pmod[6] +set_location_assignment PIN_11 -to io_pmod[7] +set_location_assignment PIN_22 -to io_rtc_sda +set_location_assignment PIN_21 -to o_rtc_scl +set_location_assignment PIN_17 -to o_led +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name USE_SIGNALTAP_FILE misc/SignalTapLogicAnalyzer.stp +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED WITH WEAK PULL-UP" +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE" +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_n64_si_dq +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_n64_cic_dq +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_aleh +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_read +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_write +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_alel +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_cic_clk +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_ftdi_do +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_si_clk +set_global_assignment -name SMART_RECOMPILE OFF +set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to i_clk +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON +set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to i_ftdi_clk +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON +set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to "pll:sys_pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]" +set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to "pll:sys_pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name VERILOG_FILE rtl/cart_config.v +set_global_assignment -name VERILOG_FILE rtl/sdram.v +set_global_assignment -name VERILOG_FILE rtl/external/wbsdram.v +set_global_assignment -name VERILOG_FILE rtl/external/qflexpress.v +set_global_assignment -name VERILOG_FILE rtl/address_decoder.v +set_global_assignment -name VERILOG_FILE rtl/flash.v +set_global_assignment -name VERILOG_FILE rtl/n64_pi.v +set_global_assignment -name VERILOG_FILE rtl/pc.v +set_global_assignment -name VERILOG_FILE rtl/top.v +set_global_assignment -name SDC_FILE constraints.sdc +set_global_assignment -name QIP_FILE rtl/intel/pll/pll.qip +set_global_assignment -name QIP_FILE rtl/intel/gpio/gpio_ddro.qip +set_global_assignment -name QIP_FILE rtl/intel/fifo/fifo_bus_to_pc.qip +set_global_assignment -name QIP_FILE rtl/intel/fifo/fifo_pc_to_bus.qip +set_global_assignment -name SIGNALTAP_FILE misc/SignalTapLogicAnalyzer.stp +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name SLD_FILE db/SignalTapLogicAnalyzer_auto_stripped.stp \ No newline at end of file diff --git a/fw/constraints.sdc b/fw/constraints.sdc new file mode 100644 index 0000000..2749b28 --- /dev/null +++ b/fw/constraints.sdc @@ -0,0 +1,7 @@ +create_clock -name i_clk -period 20 [get_ports i_clk] + +create_clock -name i_ftdi_clk -period 33.333 [get_ports i_ftdi_clk] + +derive_pll_clocks -create_base_clocks + +derive_clock_uncertainty diff --git a/fw/misc/SignalTapLogicAnalyzer.stp b/fw/misc/SignalTapLogicAnalyzer.stp new file mode 100644 index 0000000..862ee68 --- /dev/null +++ b/fw/misc/SignalTapLogicAnalyzer.stp @@ -0,0 +1,701 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 'n64_pi:n64_pi_inst|o_address[1]' == high && 'n64_pi:n64_pi_inst|o_read_rq' == rising edge + + + + + + 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fw/rtl/address_decoder.v b/fw/rtl/address_decoder.v new file mode 100644 index 0000000..61262e1 --- /dev/null +++ b/fw/rtl/address_decoder.v @@ -0,0 +1,37 @@ +module address_decoder ( + input [31:0] i_address, + + output o_cart_config, + output o_flash, + output o_flash_cfg, + output o_sdram, + + input i_flash_enable, + input i_sdram_enable, + + output o_address_valid +); + + localparam CART_CONFIG_ADDR = 32'h1E00_0000; + localparam CART_CONFIG_WIDTH = 8; + + assign o_cart_config = i_address[31:CART_CONFIG_WIDTH] == CART_CONFIG_ADDR[31:CART_CONFIG_WIDTH]; + + localparam FLASH_ADDR = 32'h1000_0000; + localparam FLASH_REMAP_ADDR = 32'h1800_0000; + localparam FLASH_WIDTH = 24; + + assign o_flash = i_flash_enable && (i_address[31:FLASH_WIDTH] == (i_sdram_enable ? FLASH_REMAP_ADDR[31:FLASH_WIDTH] : FLASH_ADDR[31:FLASH_WIDTH])); + + localparam FLASH_CFG_ADDR = 32'h1C00_0000; + + assign o_flash_cfg = i_flash_enable && (i_address == FLASH_CFG_ADDR); + + localparam SDRAM_ADDR = 32'h1000_0000; + localparam SDRAM_WIDTH = 26; + + assign o_sdram = i_sdram_enable && (i_address[31:SDRAM_WIDTH] == SDRAM_ADDR[31:SDRAM_WIDTH]); + + assign o_address_valid = (|{o_cart_config, o_flash, o_flash_cfg, o_sdram}); + +endmodule diff --git a/fw/rtl/cart_config.v b/fw/rtl/cart_config.v new file mode 100644 index 0000000..961afde --- /dev/null +++ b/fw/rtl/cart_config.v @@ -0,0 +1,71 @@ +module cart_config ( + input i_clk, + input i_reset, + + input i_n64_reset, + input i_n64_nmi, + + input i_select, + input i_read_rq, + input i_write_rq, + output reg o_ack, + input [31:0] i_address, + input [31:0] i_data, + output [31:0] o_data, + + input i_n64_disabled, + + output o_flash_enable, + output o_sdram_enable +); + + reg [1:0] r_cart_config; + reg [7:0] r_cic_type; + + wire [31:0] w_regs [1:0]; + assign w_regs[0] = {30'd0, r_cart_config}; + assign w_regs[1] = {24'd0, r_cic_type}; + + assign o_data = w_regs[i_address[2]]; + + assign o_flash_enable = r_cart_config[0]; + assign o_sdram_enable = r_cart_config[1]; + + reg r_last_n64_reset; + reg r_last_n64_nmi; + + wire w_n64_reset_op = !i_n64_disabled && !r_last_n64_reset && i_n64_reset; + wire w_n64_nmi_op = !i_n64_disabled && !r_last_n64_nmi && i_n64_nmi; + + always @(posedge i_clk or posedge i_reset) begin + if (i_reset) begin + r_last_n64_reset <= 1'b0; + r_last_n64_nmi <= 1'b0; + end else begin + r_last_n64_reset <= i_n64_reset; + r_last_n64_nmi <= i_n64_nmi; + end + end + + always @(posedge i_clk or posedge i_reset or posedge w_n64_reset_op or posedge w_n64_nmi_op) begin + if (i_reset || w_n64_reset_op || w_n64_nmi_op) begin + r_cart_config <= 2'b01; + end else begin + if (i_select && i_write_rq && !i_address[2]) r_cart_config <= i_data[1:0]; + end + end + + always @(posedge i_clk or posedge i_reset) begin + if (i_reset) begin + r_cic_type <= 8'd0; + end else begin + if (i_select && i_write_rq && i_address[2]) r_cic_type <= i_data[7:0]; + end + end + + always @(posedge i_clk) begin + o_ack <= 1'b0; + if (i_select && (i_read_rq || i_write_rq)) o_ack <= 1'b1; + end + +endmodule diff --git a/fw/rtl/external/README.md b/fw/rtl/external/README.md new file mode 100644 index 0000000..0e296fd --- /dev/null +++ b/fw/rtl/external/README.md @@ -0,0 +1,25 @@ +# External code for SummerCart64 Firmware + +This folder contains code downloaded directly from external repositories with minor modifications. + +## qflexpress.v + +### Source + +[https://github.com/ZipCPU/qspiflash/blob/master/rtl/qflexpress.v](https://github.com/ZipCPU/qspiflash/blob/master/rtl/qflexpress.v) + +### Modifications + +- Changed initialization sequence. +- Extended address space for 16-bit address alignment. + +## wbsdram.v + +### Source + +[https://github.com/ZipCPU/arrowzip/blob/master/rtl/arrowzip/wbsdram.v](https://github.com/ZipCPU/arrowzip/blob/master/rtl/arrowzip/wbsdram.v) + +### Modifications + +- Changed refresh interval that suits 90 MHz clock and used SDRAM. +- Changed column and row address widths. diff --git a/fw/rtl/external/qflexpress.v b/fw/rtl/external/qflexpress.v new file mode 100644 index 0000000..9daca83 --- /dev/null +++ b/fw/rtl/external/qflexpress.v @@ -0,0 +1,2239 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// Filename: qflexpress.v +// +// Project: A Set of Wishbone Controlled SPI Flash Controllers +// +// Purpose: To provide wishbone controlled read access (and read access +// *only*) to the QSPI flash, using a flash clock equal to the +// system clock, and nothing more. Indeed, this is designed to be a +// *very* stripped down version of a flash driver, with the goal of +// providing 1) very fast access for 2) very low logic count. +// +// Three modes/states of operation: +// 1. Startup/maintenance, places the device in the Quad XIP mode +// 2. Normal operations, takes 12+8N clocks to read a value +// 3. Configuration--useful to allow an external controller issue erase +// or program commands (or other) without requiring us to +// clutter up the logic with a giant state machine +// +// STARTUP +// 1. Waits for the flash to come on line +// Start out idle for 300 uS +// 2. Sends a signal to remove the flash from any QSPI read mode. In our +// case, we'll send several clocks of an empty command. In SPI +// mode, it'll get ignored. In QSPI mode, it'll remove us from +// QSPI mode. +// 3. Explicitly places and leaves the flash into QSPI mode +// 0xEB 3(0x00) 0xa0 6(0x00) +// 4. All done +// +// Creator: Dan Gisselquist, Ph.D. +// Gisselquist Technology, LLC +// +//////////////////////////////////////////////////////////////////////////////// +// +// Copyright (C) 2018-2019, Gisselquist Technology, LLC +// +// This file is part of the set of Wishbone controlled SPI flash controllers +// project +// +// The Wishbone SPI flash controller project is free software (firmware): +// you can redistribute it and/or modify it under the terms of the GNU Lesser +// General Public License as published by the Free Software Foundation, either +// version 3 of the License, or (at your option) any later version. +// +// The Wishbone SPI flash controller project is distributed in the hope +// that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +// warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this program. (It's in the $(ROOT)/doc directory. Run make +// with no target there if the PDF file isn't present.) If not, see +// for a copy. +// +// License: LGPL, v3, as defined and found on www.gnu.org, +// http://www.gnu.org/licenses/lgpl.html +// +// +//////////////////////////////////////////////////////////////////////////////// +// +// +`default_nettype none +// +// 290 raw, 372 w/ pipe, 410 cfg, 499 cfg w/pipe +module qflexpress(i_clk, i_reset, + i_wb_cyc, i_wb_stb, i_cfg_stb, i_wb_we, i_wb_addr, i_wb_data, + o_wb_ack, o_wb_stall, o_wb_data, + o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat); + // + // LGFLASHSZ is the size of the flash memory. It defines the number + // of bits in the address register and more. This controller will support + // flash sizes up to 2^LGFLASHSZ, where LGFLASHSZ goes up to 32. + parameter LGFLASHSZ=24; + // + // OPT_PIPE makes it possible to string multiple requests together, + // with no intervening need to shutdown the QSPI connection and send a + // new address + parameter [0:0] OPT_PIPE = 1'b1; + // + // OPT_CFG enables the configuration logic port, and hence the + // ability to erase and program the flash, as well as the ability + // to perform other commands such as read-manufacturer ID, adjust + // configuration registers, etc. + parameter [0:0] OPT_CFG = 1'b1; + // + // OPT_STARTUP enables the startup logic + parameter [0:0] OPT_STARTUP = 1'b1; + // + // OPT_ADDR32 enables 32 bit addressing, rather than 24bit + // Control this by controlling the LGFLASHSZ parameter above. Anything + // greater than 24 will use 32-bit addressing, otherwise the regular + // 24-bit addressing + localparam [0:0] OPT_ADDR32 = (LGFLASHSZ > 24); + // + parameter OPT_CLKDIV = 0; + // + // Normally, I place the first byte read from the flash, and the lowest + // flash address, into bits [7:0], and then shift it up--to where upon + // return it is found in bits [31:24]. This is ideal for a big endian + // systems, not so much for little endian systems. The endian swap + // allows the bus to swap the return values in order to support little + // endian systems. + parameter [0:0] OPT_ENDIANSWAP = 1'b1; + // + // OPT_ODDR will be true any time the clock has no clock division + localparam [0:0] OPT_ODDR = (OPT_CLKDIV == 0); + // + // CKDV_BITS is the number of bits necessary to represent a counter + // that can do the CLKDIV division + localparam CKDV_BITS = (OPT_CLKDIV == 0) ? 0 + : ((OPT_CLKDIV < 2) ? 1 + : ((OPT_CLKDIV < 4) ? 2 + : ((OPT_CLKDIV < 8) ? 3 + : ((OPT_CLKDIV < 16) ? 4 + : ((OPT_CLKDIV < 32) ? 5 + : ((OPT_CLKDIV < 64) ? 6 + : ((OPT_CLKDIV < 128) ? 7 + : ((OPT_CLKDIV < 256) ? 8 : 9)))))))); + // + // RDDELAY is the number of clock cycles from when o_qspi_dat is valid + // until i_qspi_dat is valid. Read delays from 0-4 have been verified. + // DDR Registered I/O on a Xilinx device can be done with a RDDELAY=3 + // On Intel/Altera devices, RDDELAY=2 works + // I'm using RDDELAY=0 for my iCE40 devices + // + parameter RDDELAY = 0; + // + // NDUMMY is the number of "dummy" clock cycles between the 24-bits of + // the Quad I/O address and the first data bits. This includes the + // two clocks of the Quad output mode byte, 0xa0. The default is 10 + // for a Micron device. Windbond seems to want 2. Note your flash + // device carefully when you choose this value. + // + parameter NDUMMY = 6; + // + // For dealing with multiple flash devices, the OPT_STARTUP_FILE allows + // a hex file to be provided containing the necessary script to place + // the design into the proper initial configuration. + parameter OPT_STARTUP_FILE=""; + // + // + // + // + localparam [4:0] CFG_MODE = 12; + localparam [4:0] QSPEED_BIT = 11; + localparam [4:0] DSPEED_BIT = 10; // Not supported + localparam [4:0] DIR_BIT = 9; + localparam [4:0] USER_CS_n = 8; + // + localparam [1:0] NORMAL_SPI = 2'b00; + localparam [1:0] QUAD_WRITE = 2'b10; + localparam [1:0] QUAD_READ = 2'b11; + // localparam [7:0] DIO_READ_CMD = 8'hbb; + localparam [7:0] QIO_READ_CMD = OPT_ADDR32 ? 8'hec : 8'heb; + // + localparam AW=LGFLASHSZ-1; + localparam DW=32; + // +`ifdef FORMAL + localparam F_LGDEPTH=$clog2(3+RDDELAY+(OPT_ADDR32 ? 2:0)); + reg f_past_valid; +`endif + // + // + input wire i_clk, i_reset; + // + input wire i_wb_cyc, i_wb_stb, i_cfg_stb, i_wb_we; + input wire [(AW-1):0] i_wb_addr; + input wire [(DW-1):0] i_wb_data; + // + output reg o_wb_ack, o_wb_stall; + output reg [(DW-1):0] o_wb_data; + // + output reg o_qspi_sck; + output reg o_qspi_cs_n; + output reg [1:0] o_qspi_mod; + output wire [3:0] o_qspi_dat; + input wire [3:0] i_qspi_dat; + // + // Debugging port + // output wire o_dbg_trigger; + // output wire [31:0] o_debug; + + reg dly_ack, read_sck, xtra_stall; + // clk_ctr must have enough bits for ... + // 8 address clocks, 4-bits each + // NDUMMY dummy clocks, including two mode bytes + // 8 data clocks + // (RDDELAY clocks not counted here) + reg [4:0] clk_ctr; + + // + // User override logic + // + reg cfg_mode, cfg_speed, cfg_dir, cfg_cs; + wire cfg_write, cfg_hs_write, cfg_ls_write, cfg_hs_read, + user_request, bus_request, pipe_req, cfg_noop, cfg_stb; + // + assign bus_request = (i_wb_stb)&&(!o_wb_stall) + &&(!i_wb_we)&&(!cfg_mode); + assign cfg_stb = (OPT_CFG)&&(i_cfg_stb)&&(!o_wb_stall); + assign cfg_noop = ((cfg_stb)&&((!i_wb_we)||(!i_wb_data[CFG_MODE]) + ||(i_wb_data[USER_CS_n]))) + ||((!OPT_CFG)&&(i_cfg_stb)&&(!o_wb_stall)); + assign user_request = (cfg_stb)&&(i_wb_we)&&(i_wb_data[CFG_MODE]); + + assign cfg_write = (user_request)&&(!i_wb_data[USER_CS_n]); + assign cfg_hs_write = (cfg_write)&&(i_wb_data[QSPEED_BIT]) + &&(i_wb_data[DIR_BIT]); + assign cfg_hs_read = (cfg_write)&&(i_wb_data[QSPEED_BIT]) + &&(!i_wb_data[DIR_BIT]); + assign cfg_ls_write = (cfg_write)&&(!i_wb_data[QSPEED_BIT]); + + + reg ckstb, ckpos, ckneg, ckpre; + reg maintenance; + reg [1:0] m_mod; + reg m_cs_n; + reg m_clk; + reg [3:0] m_dat; + + + generate if (OPT_ODDR) + begin + + always @(*) + begin + ckstb = 1'b1; + ckpos = 1'b1; + ckneg = 1'b1; + ckpre = 1'b1; + end + + end else if (OPT_CLKDIV == 1) + begin : CKSTB_ONE + + reg clk_counter; + + initial clk_counter = 1'b1; + always @(posedge i_clk) + if (i_reset) + clk_counter <= 1'b1; + else if (clk_counter != 0) + clk_counter <= 1'b0; + else if (bus_request) + clk_counter <= (pipe_req); + else if ((maintenance)||(!o_qspi_cs_n && o_wb_stall)) + clk_counter <= 1'b1; + + always @(*) + begin + ckpre = (clk_counter == 1); + ckstb = (clk_counter == 0); + ckpos = (clk_counter == 1); + ckneg = (clk_counter == 0); + end + + end else begin : CKSTB_GEN + + reg [CKDV_BITS-1:0] clk_counter; + + initial clk_counter = OPT_CLKDIV; + always @(posedge i_clk) + if (i_reset) + clk_counter <= OPT_CLKDIV; + else if (clk_counter != 0) + clk_counter <= clk_counter - 1; + else if (bus_request) + clk_counter <= (pipe_req ? OPT_CLKDIV : 0); + else if ((maintenance)||(!o_qspi_cs_n && o_wb_stall)) + clk_counter <= OPT_CLKDIV; + + initial ckpre = (OPT_CLKDIV == 1); + initial ckstb = 1'b0; + initial ckpos = (OPT_CLKDIV == 1); + always @(posedge i_clk) + if (i_reset) + begin + ckpre <= (OPT_CLKDIV == 1); + ckstb <= 1'b0; + ckpos <= (OPT_CLKDIV == 1); + end else // if (OPT_CLKDIV > 1) + begin + ckpre <= (clk_counter == 2); + ckstb <= (clk_counter == 1); + ckpos <= (clk_counter == (OPT_CLKDIV+1)/2+1); + end + + always @(*) + ckneg = ckstb; +`ifdef FORMAL + always @(*) + assert(!ckpos || !ckneg); + + always @(posedge i_clk) + if ((f_past_valid)&&(!$past(i_reset))&&($past(ckpre))) + assert(ckstb); +`endif + end endgenerate + + // + // + // Maintenance / startup portion + // + // + generate if (OPT_STARTUP) + begin : GEN_STARTUP + localparam M_WAITBIT=10; + localparam M_LGADDR=5; +`ifdef FORMAL + // For formal, jump into the middle of the startup + localparam M_FIRSTIDX=9; +`else + localparam M_FIRSTIDX=0; +`endif + reg [M_WAITBIT:0] m_this_word; + reg [M_WAITBIT:0] m_cmd_word [0:(1< 3) + m_counter <= 3; +`endif + end + end else begin + m_midcount <= (m_counter > 1); + if (m_counter > 0) + m_counter <= m_counter - 1'b1; + end + + initial m_cs_n = 1'b1; + initial m_mod = NORMAL_SPI; + always @(posedge i_clk) + if (i_reset) + begin + m_cs_n <= 1'b1; + m_mod <= NORMAL_SPI; + m_bitcount <= 0; + end else if (ckstb) + begin + if (m_bitcount != 0) + m_bitcount <= m_bitcount - 1; + else if ((m_ce)&&(m_final)) + begin + m_cs_n <= 1'b1; + m_mod <= NORMAL_SPI; + m_bitcount <= 0; + end else if ((m_midcount)||(m_this_word[M_WAITBIT])) + begin + m_cs_n <= 1'b1; + m_mod <= NORMAL_SPI; + m_bitcount <= 0; + end else begin + m_cs_n <= 1'b0; + m_mod <= m_this_word[M_WAITBIT-1:M_WAITBIT-2]; + m_bitcount <= (!OPT_ODDR && m_cs_n) ? 4'h2 : 4'h1; + if (!m_this_word[M_WAITBIT-1]) + m_bitcount <= (!OPT_ODDR && m_cs_n) ? 4'h8 : 4'h7;//i.e.7 + end + end + + always @(posedge i_clk) + if (m_ce) + begin + if (m_bitcount == 0) + begin + if (!OPT_ODDR && m_cs_n) + begin + m_dat <= {(4){m_this_word[7]}}; + m_byte <= m_this_word[7:0]; + end else begin + m_dat <= m_this_word[7:4]; + m_byte <= { m_this_word[3:0], 4'h0}; + if (!m_this_word[M_WAITBIT-1]) + begin + // Slow speed + m_dat[0] <= m_this_word[7]; + m_byte <= { m_this_word[6:0], 1'b0 }; + end + end + end else begin + m_dat <= m_byte[7:4]; + m_byte <= { m_byte[3:0], 4'h0 }; + if (!m_mod[1]) + begin + // Slow speed + m_dat[0] <= m_byte[7]; + m_byte <= { m_byte[6:0], 1'b0 }; + end else begin + m_byte <= { m_byte[3:0], 4'b00 }; + end + end + end + + if (OPT_ODDR) + begin + always @(*) + m_clk = !m_cs_n; + end else begin + + always @(posedge i_clk) + if (i_reset) + m_clk <= 1'b1; + else if (m_cs_n) + m_clk <= 1'b1; + else if ((!m_clk)&&(ckpos)) + m_clk <= 1'b1; + else if (m_midcount) + m_clk <= 1'b1; + else if (new_word && m_this_word[M_WAITBIT]) + m_clk <= 1'b1; + else if (ckneg) + m_clk <= 1'b0; + end + +`ifdef FORMAL + (* anyconst *) reg [M_LGADDR:0] f_const_addr; + + always @(*) + begin + assert((m_cmd_word[f_const_addr][M_WAITBIT]) + ||(m_cmd_word[f_const_addr][9:8] != 2'b01)); + if (m_cmd_word[f_const_addr][M_WAITBIT]) + assert(m_cmd_word[f_const_addr][M_WAITBIT-3:0] > 0); + end + always @(*) + begin + if (m_cmd_index != f_const_addr) + assume((m_cmd_word[m_cmd_index][M_WAITBIT])||(m_cmd_word[m_cmd_index][9:8] != 2'b01)); + if (m_cmd_word[m_cmd_index][M_WAITBIT]) + assume(m_cmd_word[m_cmd_index][M_WAITBIT-3:0]>0); + end + + always @(*) + begin + assert((m_this_word[M_WAITBIT]) + ||(m_this_word[9:8] != 2'b01)); + if (m_this_word[M_WAITBIT]) + assert(m_this_word[M_WAITBIT-3:0] > 0); + end + + // Setting the last two command words to IDLE with maximum + // counts is required by our implementation + always @(*) + assert(m_cmd_word[5'h1e] == 11'h7ff); + always @(*) + assert(m_cmd_word[5'h1f] == 11'h7ff); + + wire [M_LGADDR-1:0] last_index; + assign last_index = m_cmd_index - 1; + + always @(posedge i_clk) + if ((f_past_valid)&&(m_cmd_index != M_FIRSTIDX)) + assert(m_this_word == m_cmd_word[last_index]); + + always @(posedge i_clk) + assert(m_midcount == (m_counter != 0)); + + always @(posedge i_clk) + begin + cover(!maintenance); + cover(m_cmd_index == 5'h0a); + cover(m_cmd_index == 5'h0b); + cover(m_cmd_index == 5'h0c); + cover(m_cmd_index == 5'h0d); + cover(m_cmd_index == 5'h0e); + cover(m_cmd_index == 5'h0f); + cover(m_cmd_index == 5'h10); + cover(m_cmd_index == 5'h11); + cover(m_cmd_index == 5'h12); + cover(m_cmd_index == 5'h13); + cover(m_cmd_index == 5'h14); + cover(m_cmd_index == 5'h15); + cover(m_cmd_index == 5'h16); + cover(m_cmd_index == 5'h17); + cover(m_cmd_index == 5'h18); + cover(m_cmd_index == 5'h19); + cover(m_cmd_index == 5'h1a); + cover(m_cmd_index == 5'h1b); + cover(m_cmd_index == 5'h1c); + cover(m_cmd_index == 5'h1d); + cover(m_cmd_index == 5'h1e); + cover(m_cmd_index == 5'h1f); + end + + reg [M_WAITBIT:0] f_last_word; + reg [8:0] f_mspi; + reg [2:0] f_mqspi; + + initial f_last_word = -1; + always @(posedge i_clk) + if (i_reset) + f_last_word = -1; + else if (new_word) + f_last_word <= m_this_word; + + + initial f_mspi = 0; + always @(posedge i_clk) + if (i_reset) + f_mspi <= 0; + else if (ckstb) begin + f_mspi <= f_mspi << 1; + if (maintenance && !m_final && new_word + &&(!m_this_word[M_WAITBIT]) + &&(m_this_word[9:8] == NORMAL_SPI)) + begin + if (m_cs_n && !OPT_ODDR) + f_mspi[0] <= 1'b1; + else + f_mspi[1] <= 1'b1; + end + end + + initial f_mqspi = 0; + always @(posedge i_clk) + if (i_reset) + f_mqspi <= 0; + else if (ckstb) begin + f_mqspi <= f_mqspi << 1; + if (maintenance && !m_final && new_word + &&(!m_this_word[M_WAITBIT]) + &&(m_this_word[9])) + begin + if (m_cs_n && !OPT_ODDR) + f_mqspi[0] <= 1'b1; + else + f_mqspi[1] <= 1'b1; + end + end + + always @(*) + if (OPT_ODDR) + assert(!f_mspi[0] && !f_mqspi[0]); + + + always @(*) + if ((|f_mspi) || (|f_mqspi)) + begin + + assert(maintenance); + assert(!m_cs_n); + assert(m_mod == f_last_word[9:8]); + assert(m_midcount == 1'b0); + + end else if (maintenance && o_qspi_cs_n) + begin + assert(f_last_word[M_WAITBIT]); + assert(m_counter <= f_last_word[M_WAITBIT-1:0]); + assert(m_midcount == (m_counter != 0)); + assert(m_cs_n); + end + + always @(*) + assert((f_mspi == 0)||(f_mqspi == 0)); + + always @(*) + if (|f_mspi) + assert(m_mod == NORMAL_SPI); + + always @(*) + case(f_mspi[8:1]) + 8'h00: begin end + 8'h01: assert(m_dat[0] == f_last_word[7]); + 8'h02: assert(m_dat[0] == f_last_word[6]); + 8'h04: assert(m_dat[0] == f_last_word[5]); + 8'h08: assert(m_dat[0] == f_last_word[4]); + 8'h10: assert(m_dat[0] == f_last_word[3]); + 8'h20: assert(m_dat[0] == f_last_word[2]); + 8'h40: assert(m_dat[0] == f_last_word[1]); + 8'h80: assert(m_dat[0] == f_last_word[0]); + default: begin assert(0); end + endcase + + always @(*) + if (|f_mqspi) + assert(m_mod == QUAD_WRITE || m_mod == QUAD_READ); + + always @(*) + case(f_mqspi[2:1]) + 2'b00: begin end + 2'b01: assert(m_dat[3:0] == f_last_word[7:4]); + 2'b10: assert(m_dat[3:0] == f_last_word[3:0]); + default: begin assert(f_mqspi != 2'b11); end + endcase +`endif + end else begin : NO_STARTUP_OPT + + always @(*) + begin + maintenance = 0; + m_mod = 2'b00; + m_cs_n = 1'b1; + m_clk = 1'b0; + m_dat = 4'h0; + end + + // verilator lint_off UNUSED + wire [8:0] unused_maintenance; + assign unused_maintenance = { maintenance, + m_mod, m_cs_n, m_clk, m_dat }; + // verilator lint_on UNUSED + end endgenerate + + + reg [32+(OPT_ADDR32 ? 8:0)+4*(OPT_ODDR ? 0:1)-1:0] data_pipe; + reg pre_ack = 1'b0; + reg actual_sck; + + // + // + // Data / access portion + // + // + initial data_pipe = 0; + always @(posedge i_clk) + begin + if (!o_wb_stall) + begin + // Set the high bits to zero initially + data_pipe <= 0; + + data_pipe[8+LGFLASHSZ-1:0] <= { + i_wb_addr, 1'b0, 4'ha, 4'h0 }; + + if (i_cfg_stb) + // High speed configuration I/O + data_pipe[24+(OPT_ADDR32 ? 8:0) +: 8] <= i_wb_data[7:0]; + + if ((i_cfg_stb)&&(!i_wb_data[QSPEED_BIT])) + begin // Low speed configuration I/O + data_pipe[28+(OPT_ADDR32 ? 8:0)]<= i_wb_data[7]; + data_pipe[24+(OPT_ADDR32 ? 8:0)]<= i_wb_data[6]; + end + + if (i_cfg_stb) + begin // These can be set independent of speed + data_pipe[20+(OPT_ADDR32 ? 8:0)]<= i_wb_data[5]; + data_pipe[16+(OPT_ADDR32 ? 8:0)]<= i_wb_data[4]; + data_pipe[12+(OPT_ADDR32 ? 8:0)]<= i_wb_data[3]; + data_pipe[ 8+(OPT_ADDR32 ? 8:0)]<= i_wb_data[2]; + data_pipe[ 4+(OPT_ADDR32 ? 8:0)]<= i_wb_data[1]; + data_pipe[ 0+(OPT_ADDR32 ? 8:0)]<= i_wb_data[0]; + end + end else if (ckstb) + data_pipe <= { data_pipe[(32+(OPT_ADDR32 ? 8:0)+4*((OPT_ODDR ? 0:1)-1))-1:0], 4'h0 }; + + if (maintenance) + data_pipe[28+(OPT_ADDR32 ? 8:0)+4*(OPT_ODDR ? 0:1) +: 4] <= m_dat; + end + + assign o_qspi_dat = data_pipe[28+(OPT_ADDR32 ? 8:0)+4*(OPT_ODDR ? 0:1) +: 4]; + + // Since we can't abort any transaction once started, without + // risking losing XIP mode or any other mode we might be in, we'll + // keep track of whether this operation should be ack'd upon + // completion + always @(posedge i_clk) + if ((i_reset)||(!i_wb_cyc)) + pre_ack <= 1'b0; + else if ((bus_request)||(cfg_write)) + pre_ack <= 1'b1; + + generate if (OPT_PIPE) + begin : OPT_PIPE_BLOCK + reg r_pipe_req; + wire w_pipe_condition; + + reg [(AW-1):0] next_addr; + always @(posedge i_clk) + if (!o_wb_stall) + next_addr <= i_wb_addr + 2'd2; + + assign w_pipe_condition = (i_wb_stb)&&(!i_wb_we)&&(pre_ack) + &&(!maintenance) + &&(!cfg_mode) + &&(!o_qspi_cs_n) + &&(|clk_ctr[2:0]) + &&(next_addr == i_wb_addr); + + initial r_pipe_req = 1'b0; + always @(posedge i_clk) + if ((clk_ctr == 1)&&(ckstb)) + r_pipe_req <= 1'b0; + else + r_pipe_req <= w_pipe_condition; + + assign pipe_req = r_pipe_req; + end else begin + assign pipe_req = 1'b0; + end endgenerate + + + initial clk_ctr = 0; + always @(posedge i_clk) + if ((i_reset)||(maintenance)) + clk_ctr <= 0; + else if ((bus_request)&&(!pipe_req)) + // Notice that this is only for + // regular bus reads, and so the check for + // !pipe_req + clk_ctr <= 5'd14 + NDUMMY + (OPT_ADDR32 ? 2:0)+(OPT_ODDR ? 0:1); + else if (bus_request) // && pipe_req + // Otherwise, if this is a piped read, we'll + // reset the counter back to eight. + clk_ctr <= 5'd8; + else if (cfg_ls_write) + clk_ctr <= 5'd8 + ((OPT_ODDR) ? 0:1); + else if (cfg_write) + clk_ctr <= 5'd2 + ((OPT_ODDR) ? 0:1); + else if ((ckstb)&&(|clk_ctr)) + clk_ctr <= clk_ctr - 1'b1; + + initial o_qspi_sck = (!OPT_ODDR); + always @(posedge i_clk) + if (i_reset) + o_qspi_sck <= (!OPT_ODDR); + else if (maintenance) + o_qspi_sck <= m_clk; + else if ((!OPT_ODDR)&&(bus_request)&&(pipe_req)) + o_qspi_sck <= 1'b0; + else if ((bus_request)||(cfg_write)) + o_qspi_sck <= 1'b1; + else if (OPT_ODDR) + begin + if ((cfg_mode)&&(clk_ctr <= 1)) + // Config mode has no pipe instructions + o_qspi_sck <= 1'b0; + else if (clk_ctr[4:0] > 5'd1) + o_qspi_sck <= 1'b1; + else + o_qspi_sck <= 1'b0; + end else if (((ckpos)&&(!o_qspi_sck))||(o_qspi_cs_n)) + begin + o_qspi_sck <= 1'b1; + end else if ((ckneg)&&(o_qspi_sck)) begin + + if ((cfg_mode)&&(clk_ctr <= 1)) + // Config mode has no pipe instructions + o_qspi_sck <= 1'b1; + else if (clk_ctr[4:0] > 5'd1) + o_qspi_sck <= 1'b0; + else + o_qspi_sck <= 1'b1; + end + + initial o_qspi_cs_n = 1'b1; + always @(posedge i_clk) + if (i_reset) + o_qspi_cs_n <= 1'b1; + else if (maintenance) + o_qspi_cs_n <= m_cs_n; + else if ((cfg_stb)&&(i_wb_we)) + o_qspi_cs_n <= (!i_wb_data[CFG_MODE])||(i_wb_data[USER_CS_n]); + else if ((OPT_CFG)&&(cfg_cs)) + o_qspi_cs_n <= 1'b0; + else if ((bus_request)||(cfg_write)) + o_qspi_cs_n <= 1'b0; + else if (ckstb) + o_qspi_cs_n <= (clk_ctr <= 1); + + // Control the mode of the external pins + // NORMAL_SPI: i_miso is an input, o_mosi is an output + // QUAD_READ: i_miso is an input, o_mosi is an input + // QUAD_WRITE: i_miso is an output, o_mosi is an output + initial o_qspi_mod = NORMAL_SPI; + always @(posedge i_clk) + if (i_reset) + o_qspi_mod <= NORMAL_SPI; + else if (maintenance) + o_qspi_mod <= m_mod; + else if ((bus_request)&&(!pipe_req)) + o_qspi_mod <= QUAD_WRITE; + else if ((bus_request)||(cfg_hs_read)) + o_qspi_mod <= QUAD_READ; + else if (cfg_hs_write) + o_qspi_mod <= QUAD_WRITE; + else if ((cfg_ls_write)||((cfg_mode)&&(!cfg_speed))) + o_qspi_mod <= NORMAL_SPI; + else if ((ckstb)&&(clk_ctr <= 5'd9)&&((!cfg_mode)||(!cfg_dir))) + o_qspi_mod <= QUAD_READ; + + initial o_wb_stall = 1'b1; + always @(posedge i_clk) + if (i_reset) + o_wb_stall <= 1'b1; + else if (maintenance) + o_wb_stall <= 1'b1; + else if ((RDDELAY > 0)&&((i_cfg_stb)||(i_wb_stb))&&(!o_wb_stall)) + o_wb_stall <= 1'b1; + else if ((RDDELAY == 0)&&((cfg_write)||(bus_request))) + o_wb_stall <= 1'b1; + else if (ckstb || clk_ctr == 0) + begin + if (ckpre && (i_wb_stb)&&(pipe_req)&&(clk_ctr == 5'd2)) + o_wb_stall <= 1'b0; + else if ((clk_ctr > 1)||(xtra_stall)) + o_wb_stall <= 1'b1; + else + o_wb_stall <= 1'b0; + end else if (ckpre && (i_wb_stb)&&(pipe_req)&&(clk_ctr == 5'd1)) + o_wb_stall <= 1'b0; + + initial dly_ack = 1'b0; + always @(posedge i_clk) + if (i_reset) + dly_ack <= 1'b0; + else if ((ckstb)&&(clk_ctr == 1)) + dly_ack <= (i_wb_cyc)&&(pre_ack); + else if ((i_wb_stb)&&(!o_wb_stall)&&(!bus_request)) + dly_ack <= 1'b1; + else if (cfg_noop) + dly_ack <= 1'b1; + else + dly_ack <= 1'b0; + + generate if (OPT_ODDR) + begin : SCK_ACTUAL + + always @(*) + actual_sck = o_qspi_sck; + + end else if (OPT_CLKDIV == 1) + begin : SCK_ONE + + initial actual_sck = 1'b0; + always @(posedge i_clk) + if (i_reset) + actual_sck <= 1'b0; + else + actual_sck <= (!o_qspi_sck)&&(clk_ctr > 0); + + end else begin : SCK_ANY + + initial actual_sck = 1'b0; + always @(posedge i_clk) + if (i_reset) + actual_sck <= 1'b0; + else + actual_sck <= (o_qspi_sck)&&(ckpre)&&(clk_ctr > 0); + + end endgenerate + + +`ifdef FORMAL + reg [F_LGDEPTH-1:0] f_extra; +`endif + + generate if (RDDELAY == 0) + begin : RDDELAY_NONE + + always @(*) + begin + read_sck = actual_sck; + o_wb_ack = dly_ack; + xtra_stall = 1'b0; + end + +`ifdef FORMAL + always @(*) + f_extra = 0; +`endif + + end else + begin : RDDELAY_NONZERO + + reg [RDDELAY-1:0] sck_pipe, ack_pipe, stall_pipe; + reg not_done; + + initial sck_pipe = 0; + initial ack_pipe = 0; + initial stall_pipe = -1; + if (RDDELAY > 1) + begin + always @(posedge i_clk) + if (i_reset) + sck_pipe <= 0; + else + sck_pipe <= { sck_pipe[RDDELAY-2:0], actual_sck }; + + always @(posedge i_clk) + if (i_reset || !i_wb_cyc) + ack_pipe <= 0; + else + ack_pipe <= { ack_pipe[RDDELAY-2:0], dly_ack }; + + always @(posedge i_clk) + if (i_reset) + stall_pipe <= -1; + else + stall_pipe <= { stall_pipe[RDDELAY-2:0], not_done }; + + + end else // if (RDDELAY > 0) + begin + always @(posedge i_clk) + if (i_reset) + sck_pipe <= 0; + else + sck_pipe <= actual_sck; + + always @(posedge i_clk) + if (i_reset || !i_wb_cyc) + ack_pipe <= 0; + else + ack_pipe <= dly_ack; + + always @(posedge i_clk) + if (i_reset) + stall_pipe <= -1; + else + stall_pipe <= not_done; + end + + always @(*) + begin + not_done = (i_wb_stb || i_cfg_stb) && !o_wb_stall; + if (clk_ctr > 1) + not_done = 1'b1; + if ((clk_ctr == 1)&&(!ckstb)) + not_done = 1'b1; + end + + always @(*) + o_wb_ack = ack_pipe[RDDELAY-1]; + + always @(*) + read_sck = sck_pipe[RDDELAY-1]; + + always @(*) + xtra_stall = |stall_pipe; + +`ifdef FORMAL + integer k; + always @(*) + if (!i_wb_cyc) + f_extra = 0; + else begin + f_extra = 0; + for(k=0; k 0) + begin + always @(posedge i_clk) + assume(i_qspi_dat == $past(dly_idat,RDDELAY)); + end else begin + always @(posedge i_clk) + assume(i_qspi_dat == dly_idat); + end endgenerate + + // + //////////////////////////////////////////////////////////////////////// + // + // Maintenance mode assertions + // + + always @(*) + if (maintenance) + begin + assume((!i_wb_stb)&&(!i_cfg_stb)); + + assert(f_outstanding == 0); + + assert(o_wb_stall); + // + assert(clk_ctr == 0); + assert(cfg_mode == 1'b0); + end + + always @(*) + if (maintenance) + begin + assert(clk_ctr == 0); + assert(!o_wb_ack); + end + + //////////////////////////////////////////////////////////////////////// + // + // + // + always @(posedge i_clk) + if (dly_ack) + assert(clk_ctr[2:0] == 0); + + // Zero cycle requests + always @(posedge i_clk) + if ((f_past_valid)&&(!$past(i_reset))&&(($past(cfg_noop)) + ||($past(i_wb_stb && i_wb_we && !o_wb_stall)))) + assert((dly_ack)&&((!i_wb_cyc) + ||(f_outstanding == 1 + f_extra))); + + always @(posedge i_clk) + if ((f_outstanding > 0)&&(clk_ctr > 0)) + assert(pre_ack); + + always @(posedge i_clk) + if ((i_wb_cyc)&&(dly_ack)) + assert(f_outstanding >= 1 + f_extra); + + always @(posedge i_clk) + if ((f_past_valid)&&(clk_ctr == 0)&&(!dly_ack) + &&((!$past(i_wb_stb|i_cfg_stb))||($past(o_wb_stall)))) + assert(f_outstanding == f_extra); + + always @(*) + if ((i_wb_cyc)&&(pre_ack)&&(!o_qspi_cs_n)) + assert((f_outstanding >= 1 + f_extra)||((OPT_CFG)&&(cfg_mode))); + + always @(*) + if ((cfg_mode)&&(!dly_ack)&&(clk_ctr == 0)) + assert(f_outstanding == f_extra); + + always @(*) + if (cfg_mode) + assert(f_outstanding <= 1 + f_extra); + + ///////////////// + // + // Idle channel + // + ///////////////// + always @(*) + if (!maintenance) + begin + if (o_qspi_cs_n) + begin + assert(clk_ctr == 0); + assert(o_qspi_sck == !OPT_ODDR); + end else if (clk_ctr == 0) + assert(o_qspi_sck == !OPT_ODDR); + end + + always @(*) + assert(o_qspi_mod != 2'b01); + + always @(*) + if (clk_ctr > (5'h8 * (1+OPT_CLKDIV))) + begin + assert(!cfg_mode); + assert(!cfg_cs); + end + + + always @(posedge i_clk) + if ((OPT_CLKDIV==1)&&(!o_qspi_cs_n)&&(!$past(o_qspi_cs_n)) + &&(!$past(o_qspi_cs_n,2))&&(!cfg_mode)) + assert(o_qspi_sck != $past(o_qspi_sck)); + + ///////////////// + // + // Read requests + // + ///////////////// + always @(posedge i_clk) + if ((f_past_valid)&&(!$past(i_reset))&&($past(bus_request))) + begin + assert(!o_qspi_cs_n); + if ((OPT_ODDR)||(!$past(pipe_req))) + assert(o_qspi_sck == 1'b1); + else + assert(o_qspi_sck == 1'b0); + // + if (!$past(o_qspi_cs_n)) + begin + assert(clk_ctr == 5'd8); + assert(o_qspi_mod == QUAD_READ); + end else begin + assert(clk_ctr == 5'd14 + NDUMMY + + (OPT_ADDR32 ? 2:0) + (OPT_ODDR ? 0:1)); + assert(o_qspi_mod == QUAD_WRITE); + end + end + + always @(*) + assert(clk_ctr <= 5'd18 + NDUMMY + (OPT_ODDR ? 0:1)); + + always @(*) + if ((OPT_ODDR)&&(!o_qspi_cs_n)) + assert((o_qspi_sck)||(actual_sck)||(cfg_mode)||(maintenance)); + + always @(*) + if ((RDDELAY == 0)&&((dly_ack)&&(clk_ctr == 0))) + assert(!o_wb_stall); + + always @(*) + if (!maintenance) + begin + if (cfg_mode) + begin + if (!cfg_cs) + assert(o_qspi_cs_n); + else if (!cfg_speed) + assert(o_qspi_mod == NORMAL_SPI); + else if ((cfg_dir)&&(clk_ctr > 0)) + assert(o_qspi_mod == QUAD_WRITE); + end else if (clk_ctr > 5'd8) + assert(o_qspi_mod == QUAD_WRITE); + else if (clk_ctr > 0) + assert(o_qspi_mod == QUAD_READ); + end + + always @(posedge i_clk) + if (((!OPT_PIPE)&&(clk_ctr != 0))||(clk_ctr > 5'd1)) + assert(o_wb_stall); + + always @(posedge i_clk) + if ((OPT_CLKDIV>0)&&($past(o_qspi_cs_n))) + assert(o_qspi_sck); + + ///////////////// + // + // User mode + // + ///////////////// + always @(*) + if ((maintenance)||(!OPT_CFG)) + assert(!cfg_mode); + always @(*) + if ((OPT_CFG)&&(cfg_mode)) + assert(o_qspi_cs_n == !cfg_cs); + else + assert(!cfg_cs); + + // + // + // + // + always @(posedge i_clk) + if (bus_request) + begin + // Make sure all of the bits are set + fv_addr <= 0; + // Now set as many bits as we have address bits + fv_addr[AW-1:0] <= i_wb_addr; + end + + always @(posedge i_clk) + if ((i_wb_stb || i_cfg_stb) && !o_wb_stall && i_wb_we) + fv_data <= i_wb_data; + + // Memory reads + + initial f_memread = 0; + generate if (RDDELAY == 0) + begin + + always @(posedge i_clk) + if (i_reset) + f_memread <= 0; + else begin + if (ckstb) + f_memread <= { f_memread[F_MEMACK-1:0],1'b0}; + else if (!OPT_ODDR) + f_memread[F_MEMACK] <= 1'b0; + if ((bus_request)&&(o_qspi_cs_n)) + f_memread[0] <= 1'b1; + end + end else begin + + always @(posedge i_clk) + if (i_reset) + f_memread <= 0; + else begin + if (ckstb) + f_memread <= { f_memread[F_MEMACK-1:0],1'b0}; + else if (!OPT_ODDR) + f_memread[F_MEMACK:F_MEMDONE] + <= { f_memread[F_MEMACK-1:F_MEMDONE],1'b0}; + if ((bus_request)&&(o_qspi_cs_n)) + f_memread[0] <= 1'b1; + end + end endgenerate + + always @(posedge i_clk) + if ((OPT_ODDR)&&(|f_memread[F_MEMDONE-1:0])) + assert(o_qspi_sck); + + always @(posedge i_clk) + if (|f_memread[6+(OPT_ADDR32 ? 2:0)+(OPT_ODDR ? 0:1):0]) + assert(o_qspi_mod == QUAD_WRITE); + else if (|f_memread[(OPT_ODDR ? 0:1)+(OPT_ADDR32 ? 2:0) +7 +: NDUMMY]) + // begin assert(1); end + begin end + else if (|f_memread) + assert(o_qspi_mod == QUAD_READ); + + generate if (RDDELAY > 0) + begin + always @(posedge i_clk) + if ($past(ckpos,RDDELAY)) + begin + if ($past(o_qspi_mod,RDDELAY) == NORMAL_SPI) + f_past_data <= { f_past_data[31:0], i_qspi_dat[1] }; + else if ($past(o_qspi_mod,RDDELAY) == QUAD_READ) + f_past_data <= { f_past_data[28:0], i_qspi_dat[3:0] }; + end + end else begin + always @(posedge i_clk) + if (ckpos) + begin + if (o_qspi_mod == NORMAL_SPI) + f_past_data <= { f_past_data[31:0], i_qspi_dat[1] }; + else if (o_qspi_mod == QUAD_READ) + f_past_data <= { f_past_data[28:0], i_qspi_dat[3:0] }; + end + end endgenerate + + + always @(posedge i_clk) + if (|f_memread[(OPT_ODDR ? 0:1) +: 7 + (OPT_ADDR32 ? 2:0)]) + begin + if (OPT_ADDR32) + begin + // Eight extra bits of address + if (f_memread[(OPT_ODDR ? 0:1)]) + assert(o_qspi_dat== fv_addr[29:26]); + if (f_memread[1 + (OPT_ODDR ? 0:1)]) + assert(o_qspi_dat== fv_addr[25:22]); + end + // 6 nibbles of address, one nibble of mode + if (f_memread[(OPT_ODDR ? 0:1)+(OPT_ADDR32 ? 2:0)]) + assert(o_qspi_dat== fv_addr[21:18]); + if (f_memread[1+(OPT_ODDR ? 0:1)+(OPT_ADDR32 ? 2:0)]) + assert(o_qspi_dat== fv_addr[17:14]); + if (f_memread[2+(OPT_ODDR ? 0:1)+(OPT_ADDR32 ? 2:0)]) + assert(o_qspi_dat== fv_addr[13:10]); + if (f_memread[3+(OPT_ODDR ? 0:1)+(OPT_ADDR32 ? 2:0)]) + assert(o_qspi_dat== fv_addr[ 9: 6]); + if (f_memread[4+(OPT_ODDR ? 0:1)+(OPT_ADDR32 ? 2:0)]) + assert(o_qspi_dat== fv_addr[ 5: 2]); + if (f_memread[5+(OPT_ODDR ? 0:1)+(OPT_ADDR32 ? 2:0)]) + assert(o_qspi_dat=={ fv_addr[1:0],2'b00 }); + if (f_memread[6+(OPT_ODDR ? 0:1)+(OPT_ADDR32 ? 2:0)]) + assert(o_qspi_dat == 4'ha); + end + + always @(posedge i_clk) + if (OPT_ODDR) + begin + if (f_memread[F_MEMACK] && OPT_ENDIANSWAP) + begin + assert(o_wb_data[ 7: 4] == $past(i_qspi_dat,8)); + assert(o_wb_data[ 3: 0] == $past(i_qspi_dat,7)); + assert(o_wb_data[15:12] == $past(i_qspi_dat,6)); + assert(o_wb_data[11: 8] == $past(i_qspi_dat,5)); + assert(o_wb_data[23:20] == $past(i_qspi_dat,4)); + assert(o_wb_data[19:16] == $past(i_qspi_dat,3)); + assert(o_wb_data[31:28] == $past(i_qspi_dat,2)); + assert(o_wb_data[27:24] == $past(i_qspi_dat,1)); + end else if (f_memread[F_MEMACK]) + begin + assert(o_wb_data[31:28] == $past(i_qspi_dat,8)); + assert(o_wb_data[27:24] == $past(i_qspi_dat,7)); + assert(o_wb_data[23:20] == $past(i_qspi_dat,6)); + assert(o_wb_data[19:16] == $past(i_qspi_dat,5)); + assert(o_wb_data[15:12] == $past(i_qspi_dat,4)); + assert(o_wb_data[11: 8] == $past(i_qspi_dat,3)); + assert(o_wb_data[ 7: 4] == $past(i_qspi_dat,2)); + assert(o_wb_data[ 3: 0] == $past(i_qspi_dat,1)); + end else if (|f_memread) + begin + if (!OPT_PIPE) + assert(o_wb_stall); + else if (!f_memread[F_MEMDONE-1]) + assert(o_wb_stall); + assert(!o_wb_ack); + end + end else if (f_memread[F_MEMACK] && OPT_ENDIANSWAP) + assert((!o_wb_ack)||( + o_wb_data[ 7: 0] == f_past_data[31:24] + && o_wb_data[15: 8] == f_past_data[23:16] + && o_wb_data[23:16] == f_past_data[15: 8] + && o_wb_data[31:24] == f_past_data[ 7: 0])); + else if (f_memread[F_MEMACK]) // 25 + assert((!o_wb_ack)||(o_wb_data == f_past_data[31:0])); + else if (|f_memread) + begin + if ((!OPT_PIPE)||(!ckstb)) + assert(o_wb_stall); + else if (!f_memread[F_MEMDONE-1]) + assert(o_wb_stall); + assert(!o_wb_ack); + end + + always @(posedge i_clk) + if (f_memread[F_MEMDONE]) + assert((clk_ctr == 0)||((OPT_PIPE)&&(clk_ctr == F_PIPEDONE))); + // else if (|f_memread[F_MEMDONE-1:0]) + // assert(f_memread[F_MEMDONE-clk_ctr]); + + generate for(k=0; k 0) + begin + + always @(posedge i_clk) + if (|f_cfghswrite[F_CFGHSACK:F_CFGHSDONE]) + assert(!actual_sck); + + end endgenerate + + always @(posedge i_clk) + if (|f_cfghswrite) + begin + assert(!o_qspi_cs_n); + assert(o_qspi_mod == QUAD_WRITE); + end + + always @(posedge i_clk) + if (|f_cfghswrite[1:0]) + begin + assert(!dly_ack); + assert(o_wb_stall); + end + + always @(posedge i_clk) + if (f_cfghswrite[F_CFGHSACK]) + begin + assert((o_wb_ack)||(!$past(pre_ack))||(!$past(i_wb_cyc))); + assert(o_qspi_mod == QUAD_WRITE); + assert(!o_wb_stall); + end else if (|f_cfghswrite) + begin + assert(o_wb_stall); + assert(!o_wb_ack); + end + + //////////////////////////////////////////////////////////////////////// + // + // High speed config read + // + initial f_cfghsread = 0; + always @(posedge i_clk) + if (i_reset) + f_cfghsread <= 0; + else begin + if (ckstb) + f_cfghsread <= { f_cfghsread[F_CFGHSACK-1:0], 1'b0 }; + else if (!OPT_ODDR) + f_cfghsread[F_CFGHSACK:F_CFGHSDONE] + <={f_cfghsread[F_CFGHSACK:F_CFGHSDONE], 1'b0}; + if (cfg_hs_read) + f_cfghsread[0] <= 1'b1; + end + + always @(*) + if (OPT_ODDR) + begin + if (|f_cfghsread[1:0]) + assert(o_qspi_sck); + else if (|f_cfghsread) + assert(!o_qspi_sck); + end + + always @(posedge i_clk) + if (|f_cfghsread[F_CFGHSACK:F_CFGHSDONE]) + assert(o_qspi_sck == !OPT_ODDR); + + always @(*) + if ((!maintenance)&&(o_qspi_cs_n)) + assert(!actual_sck); + + always @(posedge i_clk) + if (|f_cfghsread[F_CFGHSDONE-1:F_CFGHSDONE-2]) + begin + assert(!dly_ack); + assert(!o_qspi_cs_n); + assert(o_qspi_mod == QUAD_READ); + assert(o_wb_stall); + end + + generate if (RDDELAY > 0) + begin + + always @(posedge i_clk) + if (|f_cfghswrite[F_CFGHSACK:F_CFGHSDONE]) + assert(!actual_sck); + + end endgenerate + + + always @(posedge i_clk) + if (f_cfghsread[F_CFGHSACK]) + begin + if (OPT_ODDR) + begin + assert(o_wb_data[7:4] == $past(i_qspi_dat[3:0],2)); + assert(o_wb_data[3:0] == $past(i_qspi_dat[3:0],1)); + end + assert(o_wb_data[7:0] == f_past_data[7:0]); + assert((o_wb_ack)||(!$past(pre_ack))||(!$past(i_wb_cyc))); + assert(o_qspi_mod == QUAD_READ); + assert(!o_wb_stall); + end else if (|f_cfghsread) + begin + assert(o_wb_stall); + assert(!o_wb_ack); + end + + //////////////////////////////////////////////////////////////////////// + // + // Crossover checks + // + wire f_qspi_not_done, f_qspi_not_ackd, f_qspi_active, f_qspi_ack; + assign f_qspi_not_done = + (|f_memread[F_MEMDONE-1:0]) + ||(|f_piperead[F_PIPEDONE-1:0]) + ||(|f_cfglswrite[F_CFGLSDONE-1:0]) + ||(|f_cfghswrite[F_CFGHSDONE-1:0]) + ||(|f_cfghsread[F_CFGHSDONE-1:0]); + assign f_qspi_active = (!maintenance)&&( + (|f_memread[F_MEMACK-1:0]) + ||(|f_piperead[F_PIPEACK-1:0]) + ||(|f_cfglswrite[F_CFGLSACK-1:0]) + ||(|f_cfghswrite[F_CFGHSACK-1:0]) + ||(|f_cfghsread[F_CFGHSACK-1:0])); + assign f_qspi_not_ackd = (!maintenance)&&(!f_qspi_not_done)&&( + (|f_memread[F_MEMACK-1:0]) + ||(|f_piperead[F_PIPEACK-1:0]) + ||(|f_cfglswrite[F_CFGLSACK-1:0]) + ||(|f_cfghswrite[F_CFGHSACK-1:0]) + ||(|f_cfghsread[F_CFGHSACK-1:0])); + assign f_qspi_ack = (!maintenance)&& + (|f_memread[F_MEMACK:0]) + ||(|f_piperead[F_PIPEACK:0]) + ||(|f_cfglswrite[F_CFGLSACK:0]) + ||(|f_cfghswrite[F_CFGHSACK:0]) + ||(|f_cfghsread[F_CFGHSACK:0]); + + always @(*) + begin + if ((|f_memread[F_MEMDONE:0])||(|f_piperead[F_PIPEDONE:0])) + begin + assert(f_cfglswrite == 0); + assert(f_cfghswrite == 0); + assert(f_cfghsread == 0); + end + + if (|f_cfglswrite[F_CFGLSDONE:0]) + begin + assert(f_cfghswrite[F_CFGHSDONE:0] == 0); + assert(f_cfghsread[F_CFGHSDONE:0] == 0); + end + + if (|f_cfghswrite[F_CFGHSDONE:0]) + assert(f_cfghsread[F_CFGHSDONE:0] == 0); + + if (maintenance) + begin + assert(f_memread == 0); + assert(f_piperead == 0); + assert(f_cfglswrite == 0); + assert(f_cfghswrite == 0); + assert(f_cfghsread == 0); + end + + assert(clk_ctr <= F_MEMDONE); + end + + always @(posedge i_clk) + if ((f_past_valid)&&(!f_qspi_ack)&&(!$past(i_reset)) + &&(!$past(maintenance))) + begin + assert($stable(o_wb_data[7:0])); + if (!cfg_mode && !$past(cfg_mode) + && !$past(i_cfg_stb && !o_wb_stall) + &&($past(f_past_valid)) + && !$past(i_cfg_stb && !o_wb_stall,2)) + assert($stable(o_wb_data)); + end + + always @(*) + if (!maintenance && actual_sck) + begin + assert(f_qspi_not_done); + /* + assert((|f_memread[F_MEMDONE:0]) + ||(|f_piperead[F_PIPEDONE:0]) + ||(|f_cfglswrite[F_CFGLSDONE:0]) + ||(|f_cfghswrite[F_CFGHSDONE:0]) + ||(|f_cfghsread[F_CFGHSDONE:0])); + */ + end + + always @(*) + if (!maintenance && !o_qspi_cs_n && !cfg_mode) + begin + assert((|f_memread[F_MEMDONE:0]) + ||(|f_piperead[F_PIPEDONE:0])); + end else if (!maintenance && cfg_mode) + begin + if ((o_qspi_sck == OPT_ODDR)||(clk_ctr > 0)||(actual_sck)) + begin + assert( (|f_cfglswrite[F_CFGLSDONE-1:0]) + ||(|f_cfghswrite[F_CFGHSDONE-1:0]) + ||(|f_cfghsread[F_CFGHSDONE-1:0])); + end + end + + always @(posedge i_clk) + if (o_wb_ack && !$past((i_wb_stb || i_cfg_stb)&&!o_wb_stall, 1+RDDELAY)) + begin + assert(f_memread[F_MEMACK] + || f_piperead[F_PIPEACK] + || f_cfglswrite[F_CFGLSACK] + || f_cfghswrite[F_CFGHSACK] + || f_cfghsread[F_CFGHSACK]); + end + + + //////////////////////////////////////////////////////////////////////// + // + // Cover Properties + // + //////////////////////////////////////////////////////////////////////// + // + // Due to the way the chip starts up, requiring 32k+ maintenance clocks, + // these cover statements are not likely to be hit + + generate if (!OPT_STARTUP) + begin + // Why is this generate only if !OPT_STARTUP? For performance + // reasons. The startup sequence can take a great many clocks. + // cover() would never be able to work through all of those + // clocks to find the following examples, and so it would fail. + // By only checking these cover() statements if !OPT_STARTUP, + // we give them an opportunity to succeed + always @(posedge i_clk) + cover(o_wb_ack && f_memread[ F_MEMACK]); + + if (OPT_CFG) + begin + always @(posedge i_clk) + begin + cover(cfg_ls_write); + cover(cfg_hs_write); + cover(cfg_hs_read); + + cover(|f_cfglswrite); + cover(|f_cfghsread); + cover(|f_cfghswrite); + + cover(o_wb_ack && |f_cfglswrite); + cover(o_wb_ack && |f_cfghsread); + cover(o_wb_ack && |f_cfghswrite); + + cover(f_cfglswrite[0]); + cover(f_cfghsread[ 0]); + cover(f_cfghswrite[0]); + + cover(f_cfglswrite[F_CFGLSACK-2]); + cover(f_cfghsread[ F_CFGHSACK-2]); + cover(f_cfghswrite[F_CFGHSACK-2]); + + cover(f_cfglswrite[F_CFGLSACK-1]); + cover(f_cfghsread[ F_CFGHSACK-1]); + cover(f_cfghswrite[F_CFGHSACK-1]); + + cover(f_cfglswrite[F_CFGLSACK]); + cover(f_cfghsread[ F_CFGHSACK]); + cover(f_cfghswrite[F_CFGHSACK]); + + cover(o_wb_ack && f_cfglswrite[F_CFGLSACK]); + cover(o_wb_ack && f_cfghsread[ F_CFGHSACK]); + cover(o_wb_ack && f_cfghswrite[F_CFGHSACK]); + end + end + + if (OPT_PIPE) + begin + always @(posedge i_clk) + cover(o_wb_ack && f_piperead[F_PIPEACK]); + end + // + // + // + always @(posedge i_clk) + cover((o_wb_ack)&&(!cfg_mode)); + always @(posedge i_clk) + cover((o_wb_ack)&&(!cfg_mode)&&(!$past(o_qspi_cs_n))); + always @(posedge i_clk) + // Cover a piped transaction + cover((o_wb_ack)&&(!cfg_mode)&&(!o_qspi_cs_n)); //! + always @(posedge i_clk) + cover((o_wb_ack)&&(cfg_mode)&&(cfg_speed)); + always @(posedge i_clk) + cover((o_wb_ack)&&(cfg_mode)&&(!cfg_speed)&&(cfg_dir)); + always @(posedge i_clk) + cover((o_wb_ack)&&(cfg_mode)&&(!cfg_speed)&&(!cfg_dir)); + end else begin + + always @(posedge i_clk) + cover(!maintenance); + + end endgenerate + +`endif +endmodule diff --git a/fw/rtl/external/wbsdram.v b/fw/rtl/external/wbsdram.v new file mode 100644 index 0000000..fdd4bbc --- /dev/null +++ b/fw/rtl/external/wbsdram.v @@ -0,0 +1,1038 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// Filename: wbsdram.v +// +// Project: ArrowZip, a demonstration of the Arrow MAX1000 FPGA board +// +// Purpose: Provide 32-bit wishbone access to the SDRAM memory on a MAX1000 +// board. Specifically, on each access, the controller will +// activate an appropriate bank of RAM (the SDRAM has four banks), and +// then issue the read/write command. In the case of walking off the +// bank, the controller will activate the next bank before you get to it. +// Upon concluding any wishbone access, all banks will be precharged and +// returned to idle. +// +// This particular implementation represents a second generation version +// because my first version was too complex. To speed things up, this +// version includes an extra wait state where the wishbone inputs are +// clocked into a flip flop before any action is taken on them. +// +// Creator: Dan Gisselquist, Ph.D. +// Gisselquist Technology, LLC +// +//////////////////////////////////////////////////////////////////////////////// +// +// Copyright (C) 2015-2019, Gisselquist Technology, LLC +// +// This program is free software (firmware): you can redistribute it and/or +// modify it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or (at +// your option) any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with this program. (It's in the $(ROOT)/doc directory. Run make with no +// target there if the PDF file isn't present.) If not, see +// for a copy. +// +// License: GPL, v3, as defined and found on www.gnu.org, +// http://www.gnu.org/licenses/gpl.html +// +// +//////////////////////////////////////////////////////////////////////////////// +// +// +`default_nettype none +// +`define DMOD_GETINPUT 1'b0 +`define DMOD_PUTOUTPUT 1'b1 +`define RAM_OPERATIONAL 2'b00 +`define RAM_POWER_UP 2'b01 +`define RAM_SET_MODE 2'b10 +`define RAM_INITIAL_REFRESH 2'b11 +// +module wbsdram(i_clk, + i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel, + o_wb_ack, o_wb_stall, o_wb_data, + o_ram_cs_n, o_ram_cke, o_ram_ras_n, o_ram_cas_n, o_ram_we_n, + o_ram_bs, o_ram_addr, + o_ram_dmod, i_ram_data, o_ram_data, o_ram_dqm, + o_debug); + parameter RDLY = 6; + localparam NCA=10, NRA=13, AW=(NCA+NRA+2)-1, DW=32; + localparam [NCA-2:0] COL_THRESHOLD = -16; + input wire i_clk; + // Wishbone + // inputs + input wire i_wb_cyc, i_wb_stb, i_wb_we; + input wire [(AW-1):0] i_wb_addr; + input wire [(DW-1):0] i_wb_data; + input wire [(DW/8-1):0] i_wb_sel; + // outputs + output wire o_wb_ack; + output reg o_wb_stall; + output wire [31:0] o_wb_data; + // SDRAM control + output wire o_ram_cke; + output reg o_ram_cs_n, + o_ram_ras_n, o_ram_cas_n, o_ram_we_n; + output reg [1:0] o_ram_bs; + output reg [12:0] o_ram_addr; + output reg o_ram_dmod; + input [15:0] i_ram_data; + output reg [15:0] o_ram_data; + output reg [1:0] o_ram_dqm; + output wire [(DW-1):0] o_debug; + + + // Calculate some metrics + + // + // First, do we *need* a refresh now --- i.e., must we break out of + // whatever we are doing to issue a refresh command? + // + // The step size here must be such that 8192 charges may be done in + // 64 ms. Thus for a clock of: + // ClkRate(MHz) (64ms/1000(ms/s)*ClkRate)/8192 + // 100 MHz 781 + // 96 MHz 750 + // 92 MHz 718 + // 88 MHz 687 + // 84 MHz 656 + // 80 MHz 625 + // + // However, since we do two refresh cycles everytime we need a refresh, + // this standard is close to overkill--but we'll use it anyway. At + // some later time we should address this, once we are entirely + // convinced that the memory is otherwise working without failure. Of + // course, at that time, it may no longer be a priority ... + // + reg need_refresh; + reg [9:0] refresh_clk; + wire refresh_cmd; + assign refresh_cmd = (!o_ram_cs_n)&&(!o_ram_ras_n)&&(!o_ram_cas_n)&&(o_ram_we_n); + initial refresh_clk = 0; + always @(posedge i_clk) + begin + if (refresh_cmd) + refresh_clk <= 10'd703; // Make suitable for 90 MHz clk + else if (|refresh_clk) + refresh_clk <= refresh_clk - 10'h1; + end + initial need_refresh = 1'b0; + always @(posedge i_clk) + need_refresh <= (refresh_clk == 10'h00)&&(!refresh_cmd); + + reg in_refresh; + reg [2:0] in_refresh_clk; + initial in_refresh_clk = 3'h0; + always @(posedge i_clk) + if (refresh_cmd) + in_refresh_clk <= 3'h6; + else if (|in_refresh_clk) + in_refresh_clk <= in_refresh_clk - 3'h1; + initial in_refresh = 0; + always @(posedge i_clk) + in_refresh <= (in_refresh_clk != 3'h0)||(refresh_cmd); +`ifdef FORMAL + always @(posedge i_clk) + if (in_refresh) + assert((refresh_cmd)||($past(in_refresh_clk) <= 3'h6)); + always @(posedge i_clk) + if (in_refresh) + assert(refresh_clk==10'd619+{{(7){1'b0}},in_refresh_clk}); +`endif + + + reg [2:0] bank_active [0:3]; + reg [(RDLY-1):0] r_barrell_ack; + reg r_pending; + reg r_we; + reg [(AW-1):0] r_addr; + reg [31:0] r_data; + reg [3:0] r_sel; + reg [(AW-NCA-2):0] bank_row [0:3]; + + + // + // Second, do we *need* a precharge now --- must be break out of + // whatever we are doing to issue a precharge command? + // + // Keep in mind, the number of clocks to wait has to be reduced by + // the amount of time it may take us to go into a precharge state. + // You may also notice that the precharge requirement is tighter + // than this one, so ... perhaps this isn't as required? + // + + reg [2:0] clocks_til_idle; + reg [1:0] m_state; + wire bus_cyc; + assign bus_cyc = ((i_wb_cyc)&&(i_wb_stb)&&(!o_wb_stall)); + reg nxt_dmod; + + // Pre-process pending operations + wire pending; + initial r_pending = 1'b0; + reg [(AW-1):0] fwd_addr; + initial r_addr = 0; + initial fwd_addr = { {(AW-(NCA)){1'b0}}, 1'b1, {(NCA-1){1'b0}} }; + always @(posedge i_clk) + begin + fwd_addr[NCA-2:0] <= 0; + if (bus_cyc) + begin + r_pending <= 1'b1; + r_we <= i_wb_we; + r_addr <= i_wb_addr; + r_data <= i_wb_data; + r_sel <= i_wb_sel; + fwd_addr[AW-1:NCA-1]<=i_wb_addr[(AW-1):(NCA-1)] + 1'b1; + end else if ((!o_ram_cs_n)&&(o_ram_ras_n)&&(!o_ram_cas_n)) + r_pending <= 1'b0; + else if (!i_wb_cyc) + r_pending <= 1'b0; + end + +`ifdef FORMAL + always @(*) + assert(fwd_addr[AW-1:NCA-1] == r_addr[(AW-1):(NCA-1)] + 1'b1); + always @(*) + assert(fwd_addr[NCA-3:0] == 0); +`endif + + wire [1:0] wb_bs, r_bs, fwd_bs; // Bank select + assign wb_bs = i_wb_addr[NCA:NCA-1]; + assign r_bs = r_addr[NCA:NCA-1]; + assign fwd_bs = fwd_addr[NCA:NCA-1]; + wire [NRA-1:0] wb_row, r_row, fwd_row; + assign wb_row = i_wb_addr[AW-1:NCA+1]; + assign r_row = r_addr[AW-1:NCA+1]; + assign fwd_row = fwd_addr[AW-1:NCA+1]; + + reg r_bank_valid; + initial r_bank_valid = 1'b0; + always @(posedge i_clk) + if (bus_cyc) + r_bank_valid <=((bank_active[wb_bs][2]) + &&(bank_row[wb_bs] == wb_row)); + else + r_bank_valid <= ((bank_active[r_bs][2]) + &&(bank_row[r_bs] == r_row)); + + reg fwd_bank_valid; + initial fwd_bank_valid = 0; + always @(posedge i_clk) + fwd_bank_valid <= ((bank_active[fwd_bs][2]) + &&(bank_row[fwd_bs] == fwd_row)); + + assign pending = (r_pending)&&(o_wb_stall); + + // + // + // Maintenance mode (i.e. startup) wires and logic + reg maintenance_mode; + reg m_ram_cs_n, m_ram_ras_n, m_ram_cas_n, m_ram_we_n, m_ram_dmod; + reg [(NRA-1):0] m_ram_addr; + // + // + // + + // Address MAP: + // 22-bits bits in, 23-bits out + // + // 22 1111 1111 1100 0000 0000 + // 10 9876 5432 1098 7654 3210 + // rr rrrr rrrr rrBB cccc cccc 0 + // 8765 4321 0 + // + initial r_barrell_ack = 0; + initial clocks_til_idle = 3'h0; + initial o_wb_stall = 1'b1; + initial o_ram_dmod = `DMOD_GETINPUT; + initial nxt_dmod = `DMOD_GETINPUT; + initial o_ram_cs_n = 1'b0; + initial o_ram_ras_n = 1'b1; + initial o_ram_cas_n = 1'b1; + initial o_ram_we_n = 1'b1; + initial o_ram_dqm = 2'b11; + assign o_ram_cke = 1'b1; + initial bank_active[0] = 3'b000; + initial bank_active[1] = 3'b000; + initial bank_active[2] = 3'b000; + initial bank_active[3] = 3'b000; + always @(posedge i_clk) + if (maintenance_mode) + begin + bank_active[0] <= 0; + bank_active[1] <= 0; + bank_active[2] <= 0; + bank_active[3] <= 0; + r_barrell_ack[(RDLY-1):0] <= 0; + o_wb_stall <= 1'b1; + // + o_ram_cs_n <= m_ram_cs_n; + o_ram_ras_n <= m_ram_ras_n; + o_ram_cas_n <= m_ram_cas_n; + o_ram_we_n <= m_ram_we_n; + o_ram_dmod <= m_ram_dmod; + o_ram_addr <= m_ram_addr; + o_ram_bs <= 2'b00; + nxt_dmod <= `DMOD_GETINPUT; + end else begin + o_wb_stall <= (r_pending)||(bus_cyc); + if (!i_wb_cyc) + r_barrell_ack <= 0; + else + r_barrell_ack <= r_barrell_ack >> 1; + nxt_dmod <= `DMOD_GETINPUT; + o_ram_dmod <= nxt_dmod; + + // + // We assume that, whatever state the bank is in, that it + // continues in that state and set up a series of shift + // registers to contain that information. If it will not + // continue in that state, all that therefore needs to be + // done is to set bank_active[?][2] below. + // + bank_active[0] <= { bank_active[0][2], bank_active[0][2:1] }; + bank_active[1] <= { bank_active[1][2], bank_active[1][2:1] }; + bank_active[2] <= { bank_active[2][2], bank_active[2][2:1] }; + bank_active[3] <= { bank_active[3][2], bank_active[3][2:1] }; + // + o_ram_cs_n <= (!i_wb_cyc); + // o_ram_cke <= 1'b1; + if (|clocks_til_idle[2:0]) + clocks_til_idle[2:0] <= clocks_til_idle[2:0] - 3'h1; + + // Default command is a + // NOOP if (i_wb_cyc) + // Device deselect if (!i_wb_cyc) + // o_ram_cs_n <= (!i_wb_cyc) above, NOOP + o_ram_ras_n <= 1'b1; + o_ram_cas_n <= 1'b1; + o_ram_we_n <= 1'b1; + + // o_ram_data <= r_data[15:0]; + + if (nxt_dmod) + ; + else + if ((!i_wb_cyc)||(need_refresh)) + begin // Issue a precharge all command (if any banks are open), + // otherwise an autorefresh command + if ((bank_active[0][2:1]==2'b10) + ||(bank_active[1][2:1]==2'b10) + ||(bank_active[2][2:1]==2'b10) + ||(bank_active[3][2:1]==2'b10) + ||(|clocks_til_idle[2:0])) + begin + // Do nothing this clock + // Can't precharge a bank immediately after + // activating it + end else if (bank_active[0][2] + ||(bank_active[1][2]) + ||(bank_active[2][2]) + ||(bank_active[3][2])) + begin // Close all active banks + o_ram_cs_n <= 1'b0; + o_ram_ras_n <= 1'b0; + o_ram_cas_n <= 1'b1; + o_ram_we_n <= 1'b0; + o_ram_addr[10] <= 1'b1; + bank_active[0][2] <= 1'b0; + bank_active[1][2] <= 1'b0; + bank_active[2][2] <= 1'b0; + bank_active[3][2] <= 1'b0; + end else if ((|bank_active[0]) + ||(|bank_active[1]) + ||(|bank_active[2]) + ||(|bank_active[3])) + // Can't precharge yet, the bus is still busy + begin end else if ((!in_refresh)&&((refresh_clk[9:8]==2'b00)||(need_refresh))) + begin // Send autorefresh command + o_ram_cs_n <= 1'b0; + o_ram_ras_n <= 1'b0; + o_ram_cas_n <= 1'b0; + o_ram_we_n <= 1'b1; + end // Else just send NOOP's, the default command + end else if (in_refresh) + begin + // NOOPS only here, until we are out of refresh + end else if ((pending)&&(!r_bank_valid)&&(bank_active[r_bs]==3'h0)) + begin // Need to activate the requested bank + o_ram_cs_n <= 1'b0; + o_ram_ras_n <= 1'b0; + o_ram_cas_n <= 1'b1; + o_ram_we_n <= 1'b1; + o_ram_addr <= r_row; + o_ram_bs <= r_bs; + // clocks_til_idle[2:0] <= 1; + bank_active[r_bs][2] <= 1'b1; + bank_row[r_bs] <= r_row; + // + end else if ((pending)&&(!r_bank_valid) + &&(bank_active[r_bs]==3'b111)) + begin // Need to close an active bank + o_ram_cs_n <= 1'b0; + o_ram_ras_n <= 1'b0; + o_ram_cas_n <= 1'b1; + o_ram_we_n <= 1'b0; + // o_ram_addr <= r_addr[(AW-1):(NCA+2)]; + o_ram_addr[10]<= 1'b0; + o_ram_bs <= r_bs; + // clocks_til_idle[2:0] <= 1; + bank_active[r_bs][2] <= 1'b0; + // bank_row[r_bs] <= r_row; + end else if ((pending)&&(!r_we) + &&(bank_active[r_bs][2]) + &&(r_bank_valid) + &&(clocks_til_idle[2:0] < 4)) + begin // Issue the read command + o_ram_cs_n <= 1'b0; + o_ram_ras_n <= 1'b1; + o_ram_cas_n <= 1'b0; + o_ram_we_n <= 1'b1; + o_ram_addr <= { 4'h0, r_addr[NCA-2:0], 1'b0 }; + o_ram_bs <= r_bs; + clocks_til_idle[2:0] <= 4; + + o_wb_stall <= 1'b0; + r_barrell_ack[(RDLY-1)] <= 1'b1; + end else if ((pending)&&(r_we) + &&(bank_active[r_bs][2]) + &&(r_bank_valid) + &&(clocks_til_idle[2:0] == 0)) + begin // Issue the write command + o_ram_cs_n <= 1'b0; + o_ram_ras_n <= 1'b1; + o_ram_cas_n <= 1'b0; + o_ram_we_n <= 1'b0; + o_ram_addr <= { 4'h0, r_addr[NCA-2:0], 1'b0 }; + o_ram_bs <= r_bs; + clocks_til_idle[2:0] <= 3'h1; + + o_wb_stall <= 1'b0; + r_barrell_ack[1] <= 1'b1; + // o_ram_data <= r_data[31:16]; + // + o_ram_dmod <= `DMOD_PUTOUTPUT; + nxt_dmod <= `DMOD_PUTOUTPUT; + end else if ((r_pending)&&(r_addr[(NCA-2):0] >= COL_THRESHOLD) + &&(!fwd_bank_valid)) + begin + // Do I need to close the next bank I'll need? + if (bank_active[fwd_bs][2:1]==2'b11) + begin // Need to close the bank first + o_ram_cs_n <= 1'b0; + o_ram_ras_n <= 1'b0; + o_ram_cas_n <= 1'b1; + o_ram_we_n <= 1'b0; + o_ram_addr[10] <= 1'b0; + o_ram_bs <= fwd_bs; + bank_active[fwd_bs][2] <= 1'b0; + end else if (bank_active[fwd_bs]==0) + begin + // Need to (pre-)activate the next bank + o_ram_cs_n <= 1'b0; + o_ram_ras_n <= 1'b0; + o_ram_cas_n <= 1'b1; + o_ram_we_n <= 1'b1; + o_ram_addr <= fwd_row; + o_ram_bs <= fwd_bs; + // clocks_til_idle[3:0] <= 1; + bank_active[fwd_bs] <= 3'h4; + bank_row[fwd_bs] <= fwd_row; + end + end + if (!i_wb_cyc) + r_barrell_ack <= 0; + end + + reg startup_hold; + reg [15:0] startup_idle; + initial startup_idle = 16'd20500; + initial startup_hold = 1'b1; + always @(posedge i_clk) + if (|startup_idle) + startup_idle <= startup_idle - 1'b1; + always @(posedge i_clk) + startup_hold <= |startup_idle; +`ifdef FORMAL + always @(*) + if (startup_hold) + assert(maintenance_mode); + always @(*) + if (|startup_idle) + assert(startup_hold); +`endif + + reg [3:0] maintenance_clocks; + reg maintenance_clocks_zero; + initial maintenance_mode = 1'b1; + initial maintenance_clocks = 4'hf; + initial maintenance_clocks_zero = 1'b0; + initial m_ram_addr = { 2'b00, 1'b0, 2'b00, 3'b010, 1'b0, 3'b001 }; + initial m_state = `RAM_POWER_UP; + initial m_ram_cs_n = 1'b1; + initial m_ram_ras_n = 1'b1; + initial m_ram_cas_n = 1'b1; + initial m_ram_we_n = 1'b1; + initial m_ram_dmod = `DMOD_GETINPUT; + always @(posedge i_clk) + begin + if (!maintenance_clocks_zero) + begin + maintenance_clocks <= maintenance_clocks - 4'h1; + maintenance_clocks_zero <= (maintenance_clocks == 4'h1); + end + // The only time the RAM address matters is when we set + // the mode. At other times, addr[10] matters, but the rest + // is ignored. Hence ... we'll set it to a constant. + m_ram_addr <= { 2'b00, 1'b0, 2'b00, 3'b010, 1'b0, 3'b001 }; + if (m_state == `RAM_POWER_UP) + begin + // All signals must be held in NOOP state during powerup + // m_ram_cke <= 1'b1; + m_ram_cs_n <= 1'b1; + m_ram_ras_n <= 1'b1; + m_ram_cas_n <= 1'b1; + m_ram_we_n <= 1'b1; + m_ram_dmod <= `DMOD_GETINPUT; + if (!startup_hold) + begin + m_state <= `RAM_SET_MODE; + maintenance_clocks <= 4'h3; + maintenance_clocks_zero <= 1'b0; + // Precharge all cmd + m_ram_cs_n <= 1'b0; + m_ram_ras_n <= 1'b0; + m_ram_cas_n <= 1'b1; + m_ram_we_n <= 1'b0; + m_ram_addr[10] <= 1'b1; + end + end else if (m_state == `RAM_SET_MODE) + begin + // Wait + m_ram_cs_n <= 1'b1; + m_ram_cs_n <= 1'b1; + m_ram_ras_n <= 1'b1; + m_ram_cas_n <= 1'b1; + m_ram_we_n <= 1'b1; + m_ram_addr[10] <= 1'b1; + + if (maintenance_clocks_zero) + begin + // Set mode cycle + m_ram_cs_n <= 1'b0; + m_ram_ras_n <= 1'b0; + m_ram_cas_n <= 1'b0; + m_ram_we_n <= 1'b0; + m_ram_dmod <= `DMOD_GETINPUT; + m_ram_addr[10] <= 1'b0; + + m_state <= `RAM_INITIAL_REFRESH; + maintenance_clocks <= 4'hc; + maintenance_clocks_zero <= 1'b0; + end + end else if (m_state == `RAM_INITIAL_REFRESH) + begin + // Refresh command + if (maintenance_clocks > 4'ha) + // Wait two clocks first + m_ram_cs_n <= 1'b1; + else if (maintenance_clocks > 4'h2) + m_ram_cs_n <= 1'b0; + else + m_ram_cs_n <= 1'b1; + m_ram_ras_n <= 1'b0; + m_ram_cas_n <= 1'b0; + m_ram_we_n <= 1'b1; + m_ram_dmod <= `DMOD_GETINPUT; + // m_ram_addr <= { 3'b000, 1'b0, 2'b00, 3'b010, 1'b0, 3'b001 }; + if (maintenance_clocks_zero) + maintenance_mode <= 1'b0; + end + end + + always @(posedge i_clk) + if (nxt_dmod) + o_ram_data <= r_data[15:0]; + else + o_ram_data <= r_data[31:16]; + + always @(posedge i_clk) + if (maintenance_mode) + o_ram_dqm <= 2'b11; + else if (r_we) + begin + if (nxt_dmod) + o_ram_dqm <= ~r_sel[1:0]; + else + o_ram_dqm <= ~r_sel[3:2]; + end else + o_ram_dqm <= 2'b00; + +`ifdef VERILATOR + // While I hate to build something that works one way under Verilator + // and another way in practice, this really isn't that. The problem + // \/erilator is having is resolved in toplevel.v---one file that + // \/erilator doesn't implement. In toplevel.v, there's not only a + // single clocked latch but two taking place. Here, we replicate one + // of those. The second takes place (somehow) within the sdramsim.cpp + // file. + reg [15:0] ram_data, last_ram_data; + always @(posedge i_clk) + ram_data <= i_ram_data; + always @(posedge i_clk) + last_ram_data <= ram_data; + assign o_wb_data = { last_ram_data, ram_data }; +`else + reg [15:0] last_ram_data; + always @(posedge i_clk) + last_ram_data <= i_ram_data; + assign o_wb_data = { last_ram_data, i_ram_data }; +`endif + assign o_wb_ack = r_barrell_ack[0]; + + // + // The following outputs are not necessary for the functionality of + // the SDRAM, but they can be used to feed an external "scope" to + // get an idea of what the internals of this SDRAM are doing. + // + // Just be aware of the r_we: it is set based upon the currently pending + // transaction, or (if none is pending) based upon the last transaction. + // If you want to capture the first value "written" to the device, + // you'll need to write a nothing value to the device to set r_we. + // The first value "written" to the device can be caught in the next + // interaction after that. + // + reg trigger; + always @(posedge i_clk) + trigger <= ((o_wb_data[15:0]==o_wb_data[31:16]) + &&(o_wb_ack)&&(!i_wb_we)); + + + assign o_debug = { i_wb_cyc, i_wb_stb, i_wb_we, o_wb_ack, o_wb_stall, // 5 + o_ram_cs_n, o_ram_ras_n, o_ram_cas_n, o_ram_we_n, o_ram_bs,//6 + o_ram_dmod, r_pending, // 2 + trigger, // 1 + o_ram_addr[9:0], // 10 more + (r_we) ? { o_ram_data[7:0] } // 8 values + : { o_wb_data[23:20], o_wb_data[3:0] } + // i_ram_data[7:0] + }; + + // Make Verilator happy + // verilator lint_off UNUSED + wire [NCA-1:0] unused; + assign unused = { fwd_addr[NCA-1:0] }; + // verilator lint_on UNUSED +`ifdef FORMAL + localparam REFRESH_CLOCKS = 6; + localparam ACTIVATE_CLOCKS = 6; + + // This device is 23MB, assert such + always @(*) + assert(AW == 21); + always @(*) + assert(NRA+NCA+2 == AW+1); + + wire [(5-1):0] f_nreqs, f_nacks, f_outstanding; + reg f_past_valid; + wire f_reset; + + always @(*) + if (o_ram_dmod) + assume(i_ram_data == o_ram_data); + + initial f_past_valid = 1'b0; + always @(posedge i_clk) + f_past_valid <= 1'b1; + + assign f_reset = !f_past_valid; + + always @(*) + if (o_ram_dmod) + assert(i_ram_data == o_ram_data); + + // Properties + // 1. Wishbone + fwb_slave #( .AW(AW), .DW(DW), + .F_MAX_STALL(ACTIVATE_CLOCKS + REFRESH_CLOCKS + + ACTIVATE_CLOCKS + RDLY + +ACTIVATE_CLOCKS), + .F_MAX_ACK_DELAY(REFRESH_CLOCKS + + ACTIVATE_CLOCKS + + ACTIVATE_CLOCKS + + ACTIVATE_CLOCKS+RDLY), + .F_LGDEPTH(5)) + fwb(i_clk, f_reset, + i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, + i_wb_data, i_wb_sel, + o_wb_ack, o_wb_stall, o_wb_data, 1'b0, + f_nreqs, f_nacks, f_outstanding); + + // 2. Proper startup ... + // 3. Operation + // 4. Refresh + // 4. SDRAM request == WB request + // + + // Once we leave maintenance mode (i.e. startup sequence), we *cannot* + // go back into it. + always @(posedge i_clk) + if ((f_past_valid)&&(!$past(maintenance_mode))) + assert(!maintenance_mode); + + // On the very first clock, we must always start up in maintenance mode + always @(posedge i_clk) + if (!f_past_valid) + assert(maintenance_mode); + + // Just to make things simpler, assume no accesses to the core during + // maintenance mode. Such accesses might violate our minimum + // acknowledgement time criteria for the wishbone above + always @(posedge i_clk) + if ((f_past_valid)&&(maintenance_mode)) + assume(!i_wb_stb); + + // Likewise, assert that there are *NO* outstanding transactions in + // this maintenance mode + always @(posedge i_clk) + if ((f_past_valid)&&(maintenance_mode)) + assert(f_outstanding == 0); + + // ... and that while we are in maintenance mode, any incoming request + // is stalled. This guarantees that our assumptions above are kept + // valid. + always @(posedge i_clk) + if ((f_past_valid)&&(maintenance_mode)) + assume(o_wb_stall); + + // If there are no attempts to access memory while in maintenance + // mode, then there should never be any pending operations upon + // completion of maintenance mode + always @(posedge i_clk) + if ((f_past_valid)&&(maintenance_mode)) + assert(!r_pending); + + wire [(2+AW+DW+DW/8-1):0] f_pending, f_request; + assign f_pending = { r_pending, r_we, r_addr, r_data, r_sel }; + assign f_request = { i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel }; + + always @(posedge i_clk) + if ((f_past_valid)&&($past(r_pending))&&($past(i_wb_cyc)) + &&(($past(o_ram_cs_n)) + ||(!$past(o_ram_ras_n)) + ||($past(o_ram_cas_n))) ) + assert($stable(f_pending)); + + wire [4:0] f_cmd; + assign f_cmd = { o_ram_addr[10], + o_ram_cs_n, o_ram_ras_n, o_ram_cas_n, o_ram_we_n }; + +`define F_MODE_SET 5'b?0000 +`define F_BANK_PRECHARGE 5'b00010 +`define F_PRECHARGE_ALL 5'b10010 +`define F_BANK_ACTIVATE 5'b?0011 +`define F_WRITE 5'b00100 +`define F_READ 5'b00101 +`define F_REFRESH 5'b?0001 +`define F_NOOP 5'b?0111 + +`define F_BANK_ACTIVATE_S 4'b0011 +`define F_REFRESH_S 4'b0001 +`define F_NOOP_S 4'b0111 + + reg [(AW-1):0] f_next_addr; + always @(*) + begin + f_next_addr = 0; + f_next_addr[(AW-1):NCA-1] = r_addr[(AW-1):NCA-1] + 1'b1; + end + + wire [NRA-1:0] f_next_row, f_this_row; + wire [1:0] f_next_bank, f_this_bank; + assign f_next_row = f_next_addr[(AW-1):(NCA+1)]; + assign f_next_bank = f_next_addr[NCA:NCA-1]; + assign f_this_bank = r_bs; + assign f_this_row = r_row; + + always @(*) + if (o_ram_cs_n==1'b0) casez(f_cmd) + `F_MODE_SET: begin end + `F_BANK_PRECHARGE: begin end + `F_PRECHARGE_ALL: begin end + `F_BANK_ACTIVATE: begin end + `F_WRITE: begin end + `F_READ: begin end + `F_REFRESH: begin end + default: assert(f_cmd[3:0] == `F_NOOP_S); + endcase + + always @(posedge i_clk) + if ((f_past_valid)&&(!maintenance_mode)) + casez(f_cmd) + `F_BANK_ACTIVATE: begin + // Can only activate de-activated banks + assert(bank_active[o_ram_bs][1:0] == 0); + // Need to activate the right bank + if (o_ram_bs == $past(f_this_bank)) + assert($past(f_this_row)==o_ram_addr); + else if (o_ram_bs != 0) + begin + assert(o_ram_bs == $past(f_next_bank)); + assert($past(f_this_row)==o_ram_addr); + end else begin + assert(o_ram_bs == $past(f_next_bank)); + assert($past(f_next_row)==o_ram_addr); + end end + `F_BANK_PRECHARGE: begin + // Can only precharge (de-active) a fully active bank + assert(bank_active[o_ram_bs] == 3'b011); + end + `F_PRECHARGE_ALL: begin + // If pre-charging all, one of the banks must be active and in + // need of a pre-charge + assert( + (bank_active[0] == 3'b011) + ||(bank_active[1] == 3'b011) + ||(bank_active[2] == 3'b011) + ||(bank_active[3] == 3'b011) ); + end + `F_WRITE: begin + assert($past(r_we)); + assert(bank_active[o_ram_bs] == 3'b111); + assert(bank_row[o_ram_bs] == $past(f_this_row)); + assert(o_ram_bs == $past(f_this_bank)); + assert(o_ram_addr[0] == 1'b0); + end + `F_READ: begin + assert(!$past(r_we)); + assert(bank_active[o_ram_bs] == 3'b111); + assert(bank_row[o_ram_bs] == $past(f_this_row)); + assert(o_ram_bs == $past(f_this_bank)); + assert(o_ram_addr[0] == 1'b0); + end + `F_REFRESH: begin + // When giving a reset command, *all* banks must be inactive + assert( (bank_active[0] == 3'h0) + &&(bank_active[1] == 3'h0) + &&(bank_active[2] == 3'h0) + &&(bank_active[3] == 3'h0) ); + end + default: assert((o_ram_cs_n)||(f_cmd[3:0] == `F_NOOP_S)); + endcase + + integer f_k; + always @(posedge i_clk) + if ((f_past_valid)&&(!$past(maintenance_mode))) + begin + for(f_k=0; f_k<4; f_k=f_k+1) + if (((f_cmd[3:0] != `F_BANK_ACTIVATE_S)) + ||(o_ram_bs != f_k[1:0])) + assert($stable(bank_row[f_k[1:0]])); + end + + always @(posedge i_clk) + if ((f_past_valid)&&(!$past(maintenance_mode)) + &&($past(f_cmd) != `F_READ) + &&($past(f_cmd) != `F_WRITE) ) + begin + if (($past(r_pending))&&($past(i_wb_cyc))) + assert($stable(f_pending)); + end + + always @(posedge i_clk) + if ((f_past_valid)&&(!maintenance_mode)) + if ((r_pending)&&(f_cmd != `F_READ)&&(f_cmd != `F_WRITE)) + assert(o_wb_stall); + + always @(posedge i_clk) + if ((f_past_valid)&&(!$past(maintenance_mode))) + casez($past(f_cmd)) + `F_BANK_ACTIVATE: begin + assert(bank_active[$past(o_ram_bs)] == 3'b110); + assert(bank_row[$past(o_ram_bs)] == $past(o_ram_addr)); + end + `F_BANK_PRECHARGE: begin + assert(bank_active[$past(o_ram_bs)] == 3'b001); + end + `F_PRECHARGE_ALL: begin + assert(bank_active[0][2] == 1'b0); + assert(bank_active[1][2] == 1'b0); + assert(bank_active[2][2] == 1'b0); + assert(bank_active[3][2] == 1'b0); + end + // `F_WRITE: + // `F_READ: + `F_REFRESH: begin + assert(r_barrell_ack == 0); + end + default: begin end + endcase + + always @(posedge i_clk) + if ((f_past_valid)&&(!$past(maintenance_mode))) + begin + assert(bank_active[0][1:0] == $past(bank_active[0][2:1])); + assert(bank_active[1][1:0] == $past(bank_active[1][2:1])); + assert(bank_active[2][1:0] == $past(bank_active[2][2:1])); + assert(bank_active[3][1:0] == $past(bank_active[3][2:1])); + end + + always @(*) +`ifdef VERIFIC + if (in_refresh) +`else + if ((in_refresh)||(maintenance_mode)) +`endif + begin + assert(bank_active[0] == 0); + assert(bank_active[1] == 0); + assert(bank_active[2] == 0); + assert(bank_active[3] == 0); + end + + always @(posedge i_clk) + if ((f_past_valid)&&($past(o_wb_ack))) + assert(!o_wb_ack); + + reg [3:0] f_acks_pending; + always @(*) + begin + f_acks_pending = 0; + for(f_k=0; f_k +// +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// IPFS_FILES : gpio_ddro.vo +// RELATED_FILES: gpio_ddro.v, altera_gpio_lite.sv diff --git a/fw/rtl/intel/gpio/gpio_ddro/altera_gpio_lite.sv b/fw/rtl/intel/gpio/gpio_ddro/altera_gpio_lite.sv new file mode 100644 index 0000000..6d395bb --- /dev/null +++ b/fw/rtl/intel/gpio/gpio_ddro/altera_gpio_lite.sv @@ -0,0 +1,1200 @@ +// (C) 2001-2020 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1 ps / 1 ps + +module altgpio_one_bit( + inclock, + outclock, + phy_mem_clock, + inclocken, + outclocken, + oe, + din, + dout, + pad, + pad_b, + aset, + sclr, + hr_clock, + fr_clock, + mimic_clock, + nsleep +); + + parameter PIN_TYPE = "output"; + parameter BUFFER_TYPE = "single-ended"; + parameter REGISTER_MODE = "bypass"; + parameter ASYNC_MODE = "none"; + parameter SYNC_MODE = "none"; + parameter BUS_HOLD = "false"; + parameter SET_REGISTER_OUTPUTS_HIGH = "false"; + parameter USE_ENHANCED_DDR_HIO_REGISTER = "false"; + parameter BYPASS_THREE_QUARTER_REGISTER = "true"; + parameter INVERT_OUTPUT = "false"; + parameter INVERT_INPUT_CLOCK = "false"; + parameter INVERT_OUTPUT_CLOCK = "false"; + parameter INVERT_OE_INCLOCK = "false"; + parameter USE_ONE_REG_TO_DRIVE_OE = "false"; + parameter USE_DDIO_REG_TO_DRIVE_OE = "false"; + parameter OPEN_DRAIN_OUTPUT = "false"; + parameter ENABLE_OE_HALF_CYCLE_DELAY = "true"; + parameter USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY = "false"; + parameter ENABLE_CLOCK_ENA_PORT = "false"; + parameter ENABLE_HR_CLOCK = "false"; + parameter ENABLE_PHASE_DETECTOR_FOR_CK = "false"; + parameter ENABLE_NSLEEP_PORT = "false"; + + localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? 2:1; + localparam DDIO_REG_POWER_UP = (ASYNC_MODE == "preset" || SET_REGISTER_OUTPUTS_HIGH == "true") ? "high" : "low"; + + input inclock; + input outclock; + input inclocken; + input outclocken; + input oe; + input nsleep; + input [DATA_SIZE - 1:0] din; + output [DATA_SIZE - 1:0] dout; + inout pad; + inout pad_b; + input aset; + input sclr; + input phy_mem_clock; + input hr_clock; + (* altera_attribute = "-name GLOBAL_SIGNAL\"OFF\"" *) output fr_clock; + output mimic_clock; + + wire din_ddr; + wire buf_in; + + wire oe_out; + wire nsleep_in; + + generate + if (PIN_TYPE == "output" || PIN_TYPE == "bidir") + begin + wire [1:0] din_fr; + if (INVERT_OUTPUT == "false") + begin + assign din_fr = din; + end + else + begin + assign din_fr = ~din; + end + + wire outclock_wire; + if (REGISTER_MODE != "bypass") + begin + if (INVERT_OUTPUT_CLOCK == "false") + begin: normal_input_clock + assign outclock_wire = outclock; + end + else + begin: inverted_output_clock + assign outclock_wire = ~outclock; + end + end + + wire outclocken_wire; + assign outclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? outclocken : 1'b1; + + if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "true") + begin + if (ASYNC_MODE != "none") + begin: async_mode_out_path_enhanced_ddr + fiftyfivenm_ddio_out + #( + .async_mode(ASYNC_MODE), + .sync_mode(SYNC_MODE), + .use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER), + .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER), + .power_up(DDIO_REG_POWER_UP), + .use_new_clocking_model("true") + ) fr_out_data_ddio ( + .datainhi(din_fr[0]), + .datainlo(din_fr[1]), + .dataout(din_ddr), + .clkhi(outclock_wire), + .clklo(outclock_wire), + .muxsel(outclock_wire), + .areset(aset), + .ena(outclocken_wire), + .phymemclock(phy_mem_clock) + `ifndef ALTERA_RESERVED_QIS + , + .clk (outclock_wire), + .sreset(1'b0), + .dfflo(), + .dffhi(), + .devpor(1'b1), + .devclrn(1'b1) + `endif + ); + end + else if (SYNC_MODE != "none") + begin: sync_mode_out_path_enhanced_ddr + fiftyfivenm_ddio_out + #( + .async_mode(ASYNC_MODE), + .sync_mode(SYNC_MODE), + .use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER), + .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER), + .power_up(DDIO_REG_POWER_UP), + .use_new_clocking_model("true") + ) fr_out_data_ddio ( + .datainhi(din_fr[0]), + .datainlo(din_fr[1]), + .dataout(din_ddr), + .clkhi(outclock_wire), + .clklo(outclock_wire), + .muxsel(outclock_wire), + .sreset(sclr), + .ena(outclocken_wire), + .phymemclock(phy_mem_clock) + `ifndef ALTERA_RESERVED_QIS + , + .clk (outclock_wire), + .areset(1'b0), + .dfflo(), + .dffhi(), + .devpor(1'b1), + .devclrn(1'b1) + `endif + ); + end + else + begin: out_path_enhanced_ddr + fiftyfivenm_ddio_out + #( + .async_mode(ASYNC_MODE), + .sync_mode(SYNC_MODE), + .use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER), + .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER), + .power_up(DDIO_REG_POWER_UP), + .use_new_clocking_model("true") + ) fr_out_data_ddio ( + .datainhi(din_fr[0]), + .datainlo(din_fr[1]), + .dataout(din_ddr), + .clkhi(outclock_wire), + .clklo(outclock_wire), + .muxsel(outclock_wire), + .ena(outclocken_wire), + .phymemclock(phy_mem_clock) + `ifndef ALTERA_RESERVED_QIS + , + .areset(1'b0), + .clk(1'b0), + .sreset(1'b0), + .dfflo(), + .dffhi(), + .devpor(1'b1), + .devclrn(1'b1) + `endif + ); + end + end + else if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "false") + begin + if (ASYNC_MODE != "none") + begin: async_mode_out_path_ddr + fiftyfivenm_ddio_out + #( + .async_mode(ASYNC_MODE), + .sync_mode(SYNC_MODE), + .power_up(DDIO_REG_POWER_UP), + .use_new_clocking_model("true"), + .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER) + ) fr_out_data_ddio ( + .datainhi(din_fr[0]), + .datainlo(din_fr[1]), + .dataout(din_ddr), + .clkhi(outclock_wire), + .clklo(outclock_wire), + .muxsel(outclock_wire), + .areset(aset), + .ena(outclocken_wire) + `ifndef ALTERA_RESERVED_QIS + , + .clk(1'b0), + .phymemclock(1'b0), + .sreset(1'b0), + .dfflo(), + .dffhi(), + .devpor(1'b1), + .devclrn(1'b1) + `endif + ); + end + else if (SYNC_MODE != "none") + begin: sync_mode_out_path_ddr + fiftyfivenm_ddio_out + #( + .async_mode(ASYNC_MODE), + .sync_mode(SYNC_MODE), + .power_up(DDIO_REG_POWER_UP), + .use_new_clocking_model("true"), + .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER) + ) fr_out_data_ddio ( + .datainhi(din_fr[0]), + .datainlo(din_fr[1]), + .dataout(din_ddr), + .clkhi(outclock_wire), + .clklo(outclock_wire), + .muxsel(outclock_wire), + .sreset(sclr), + .ena(outclocken_wire) + `ifndef ALTERA_RESERVED_QIS + , + .areset(1'b0), + .clk(1'b0), + .phymemclock(1'b0), + .dfflo(), + .dffhi(), + .devpor(1'b1), + .devclrn(1'b1) + `endif + ); + end + else + begin: out_path_ddr + fiftyfivenm_ddio_out + #( + .async_mode(ASYNC_MODE), + .sync_mode(SYNC_MODE), + .power_up(DDIO_REG_POWER_UP), + .use_new_clocking_model("true"), + .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER) + ) fr_out_data_ddio ( + .datainhi(din_fr[0]), + .datainlo(din_fr[1]), + .dataout(din_ddr), + .clkhi(outclock_wire), + .clklo(outclock_wire), + .muxsel(outclock_wire), + .ena(outclocken_wire) + `ifndef ALTERA_RESERVED_QIS + , + .areset(1'b0), + .clk(1'b0), + .phymemclock(1'b0), + .sreset(1'b0), + .dfflo(), + .dffhi(), + .devpor(1'b1), + .devclrn(1'b1) + `endif + ); + end + end + else if (REGISTER_MODE == "single-register") + begin: out_path_sdr + reg reg_data_out /* synthesis altera_attribute="FAST_OUTPUT_REGISTER=on" */; + always @(posedge outclock_wire) + reg_data_out <= din_fr[0]; + + assign din_ddr = reg_data_out; + end + else + begin: out_path_reg_none + assign din_ddr = din_fr[0]; + end + end + endgenerate + + generate + + if (PIN_TYPE == "bidir" || PIN_TYPE == "output") + begin + wire oe_inclk_wire; + if (USE_ONE_REG_TO_DRIVE_OE == "true" || USE_DDIO_REG_TO_DRIVE_OE == "true") + begin + if (INVERT_OE_INCLOCK == "false") + begin: normal_oe_inclock + assign oe_inclk_wire = outclock; + end + else + begin: inverted_oe_inclock + assign oe_inclk_wire = ~outclock; + end + end + + wire oe_outclocken_wire; + assign oe_outclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? outclocken : 1'b1; + + if (USE_DDIO_REG_TO_DRIVE_OE == "true") + begin + if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "true") + begin + if (ASYNC_MODE != "none") + begin: async_mode_oe_path_enhanced_ddr + fiftyfivenm_ddio_oe + #( + .async_mode(ASYNC_MODE), + .sync_mode(SYNC_MODE), + .use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER), + .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER), + .enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY), + .power_up(DDIO_REG_POWER_UP) + ) fr_oe_data_ddio ( + .oe(~oe), + .dataout(oe_out), + .clk(oe_inclk_wire), + .areset(aset), + .ena(oe_outclocken_wire), + .phymemclock(phy_mem_clock) + `ifndef ALTERA_RESERVED_QIS + , + .sreset(1'b0), + .dfflo(), + .dffhi(), + .devpor(1'b1), + .devclrn(1'b1) + `endif + ); + end + else if (SYNC_MODE != "none") + begin: sync_mode_oe_path_enhanced_ddr + fiftyfivenm_ddio_oe + #( + .async_mode(ASYNC_MODE), + .sync_mode(SYNC_MODE), + .use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER), + .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER), + .enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY), + .power_up(DDIO_REG_POWER_UP) + ) fr_oe_data_ddio ( + .oe(~oe), + .dataout(oe_out), + .clk(oe_inclk_wire), + .sreset(sclr), + .ena(oe_outclocken_wire), + .phymemclock(phy_mem_clock) + `ifndef ALTERA_RESERVED_QIS + , + .areset(1'b0), + .dfflo(), + .dffhi(), + .devpor(1'b1), + .devclrn(1'b1) + `endif + ); + end + else + begin: oe_path_enhanced_ddr + fiftyfivenm_ddio_oe + #( + .async_mode(ASYNC_MODE), + .sync_mode(SYNC_MODE), + .use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER), + .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER), + .enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY), + .power_up(DDIO_REG_POWER_UP) + ) fr_oe_data_ddio ( + .oe(~oe), + .dataout(oe_out), + .clk(oe_inclk_wire), + .ena(oe_outclocken_wire), + .phymemclock(phy_mem_clock) + `ifndef ALTERA_RESERVED_QIS + , + .areset(1'b0), + .sreset(1'b0), + .dfflo(), + .dffhi(), + .devpor(1'b1), + .devclrn(1'b1) + `endif + ); + end + end + else if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "false") + begin + if (ASYNC_MODE != "none") + begin: async_mode_oe_path_ddr + fiftyfivenm_ddio_oe + #( + .async_mode(ASYNC_MODE), + .sync_mode(SYNC_MODE), + .enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY), + .power_up(DDIO_REG_POWER_UP), + .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER) + ) fr_oe_data_ddio ( + .oe(~oe), + .dataout(oe_out), + .clk(oe_inclk_wire), + .areset(aset), + .ena(oe_outclocken_wire) + `ifndef ALTERA_RESERVED_QIS + , + .phymemclock(1'b0), + .sreset(1'b0), + .dfflo(), + .dffhi(), + .devpor(1'b1), + .devclrn(1'b1) + `endif + ); + end + else if (SYNC_MODE != "none") + begin: sync_mode_oe_path_ddr + fiftyfivenm_ddio_oe + #( + .async_mode(ASYNC_MODE), + .sync_mode(SYNC_MODE), + .enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY), + .power_up(DDIO_REG_POWER_UP), + .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER) + ) fr_oe_data_ddio ( + .oe(~oe), + .dataout(oe_out), + .clk(oe_inclk_wire), + .sreset(sclr), + .ena(oe_outclocken_wire) + `ifndef ALTERA_RESERVED_QIS + , + .areset(1'b0), + .phymemclock(1'b0), + .dfflo(), + .dffhi(), + .devpor(1'b1), + .devclrn(1'b1) + `endif + ); + end + else + begin: oe_path_ddr + fiftyfivenm_ddio_oe + #( + .async_mode(ASYNC_MODE), + .sync_mode(SYNC_MODE), + .enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY), + .power_up(DDIO_REG_POWER_UP), + .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER) + ) fr_oe_data_ddio ( + .oe(~oe), + .dataout(oe_out), + .clk(oe_inclk_wire), + .ena(oe_outclocken_wire) + `ifndef ALTERA_RESERVED_QIS + , + .areset(1'b0), + .phymemclock(1'b0), + .sreset(1'b0), + .dfflo(), + .dffhi(), + .devpor(1'b1), + .devclrn(1'b1) + `endif + ); + end + end + end + else if (USE_ONE_REG_TO_DRIVE_OE == "true") + begin: oe_path_sdr + fiftyfivenm_ff oe_reg ( + .clk(oe_inclk_wire), + .d(~oe), + .clrn(1'b1), + .ena(1'b1), + .q(oe_out) + ); + end + else if (USE_ONE_REG_TO_DRIVE_OE == "false" && USE_DDIO_REG_TO_DRIVE_OE == "false") + begin: oe_path_reg_none + assign oe_out = ~oe; + end + end + endgenerate + + generate + if (PIN_TYPE == "input" || PIN_TYPE == "bidir") + begin + wire [1:0] ddr_input; + wire inclock_wire; + + if (REGISTER_MODE != "bypass") + begin + if (INVERT_INPUT_CLOCK == "false") + begin: normal_input_clock + assign inclock_wire = inclock; + end + else + begin: inverted_input_clock + assign inclock_wire = ~inclock; + end + end + + wire inclocken_wire; + assign inclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? inclocken : 1'b1; + + if (REGISTER_MODE == "ddr") + begin + if (USE_ENHANCED_DDR_HIO_REGISTER == "true" || USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY == "true") + begin + if (ENABLE_HR_CLOCK == "true") + begin + if (ASYNC_MODE != "none") + begin: async_mode_in_path_enhanced_ddr_with_halfrateresyncclk + fiftyfivenm_ddio_in + #( + .async_mode(ASYNC_MODE), + .sync_mode(SYNC_MODE), + .power_up(DDIO_REG_POWER_UP), + .invert_input_clock(INVERT_INPUT_CLOCK) + ) fr_in_ddio ( + .datain(buf_in), + .clk(inclock_wire), + .ena(inclocken_wire), + .halfrateresyncclk(hr_clock), + .regouthi(ddr_input[1]), + .regoutlo(ddr_input[0]), + .clkout(fr_clock), + .areset(aset) + `ifndef ALTERA_RESERVED_QIS + , + .sreset(1'b0), + .dfflo(), + .devpor(1'b1), + .devclrn(1'b1) + `endif + ); + end + else if (SYNC_MODE != "none") + begin:sync_mode_in_path_enhanced_ddr_with_halfrateresyncclk + fiftyfivenm_ddio_in + #( + .async_mode(ASYNC_MODE), + .sync_mode(SYNC_MODE), + .power_up(DDIO_REG_POWER_UP), + .invert_input_clock(INVERT_INPUT_CLOCK) + ) fr_in_ddio ( + .datain(buf_in), + .clk (inclock_wire), + .ena(inclocken_wire), + .sreset(sclr), + .halfrateresyncclk(hr_clock), + .regouthi(ddr_input[1]), + .regoutlo(ddr_input[0]), + .clkout(fr_clock) + `ifndef ALTERA_RESERVED_QIS + , + .areset(1'b0), + .dfflo(), + .devpor(1'b1), + .devclrn(1'b1) + `endif + ); + end + else + begin:in_path_enhanced_ddr_with_halfrateresyncclk + fiftyfivenm_ddio_in + #( + .async_mode(ASYNC_MODE), + .sync_mode(SYNC_MODE), + .power_up(DDIO_REG_POWER_UP), + .invert_input_clock(INVERT_INPUT_CLOCK) + ) fr_in_ddio ( + .datain(buf_in), + .clk (inclock_wire), + .ena(inclocken_wire), + .halfrateresyncclk(hr_clock), + .regouthi(ddr_input[1]), + .regoutlo(ddr_input[0]), + .clkout(fr_clock) + `ifndef ALTERA_RESERVED_QIS + , + .sreset(1'b0), + .areset(1'b0), + .dfflo(), + .devpor(1'b1), + .devclrn(1'b1) + `endif + ); + end + end + else + begin + if (ASYNC_MODE != "none") + begin: async_mode_in_path_enhanced_ddr + fiftyfivenm_ddio_in + #( + .async_mode(ASYNC_MODE), + .sync_mode(SYNC_MODE), + .power_up(DDIO_REG_POWER_UP), + .invert_input_clock(INVERT_INPUT_CLOCK) + ) fr_in_ddio ( + .datain(buf_in), + .clk(inclock_wire), + .ena(inclocken_wire), + .regouthi(ddr_input[1]), + .regoutlo(ddr_input[0]), + .clkout(fr_clock), + .areset(aset) + `ifndef ALTERA_RESERVED_QIS + , + .sreset(1'b0), + .dfflo(), + .devpor(1'b1), + .devclrn(1'b1), + .halfrateresyncclk(1'b0) + `endif + ); + end + else if (SYNC_MODE != "none") + begin:sync_mode_in_path_enhanced_ddr + fiftyfivenm_ddio_in + #( + .async_mode(ASYNC_MODE), + .sync_mode(SYNC_MODE), + .power_up(DDIO_REG_POWER_UP), + .invert_input_clock(INVERT_INPUT_CLOCK) + ) fr_in_ddio ( + .datain(buf_in), + .clk (inclock_wire), + .ena(inclocken_wire), + .sreset(sclr), + .regouthi(ddr_input[1]), + .regoutlo(ddr_input[0]), + .clkout(fr_clock) + `ifndef ALTERA_RESERVED_QIS + , + .areset(1'b0), + .dfflo(), + .devpor(1'b1), + .devclrn(1'b1), + .halfrateresyncclk(1'b0) + `endif + ); + end + else + begin:in_path_enhanced_ddr + fiftyfivenm_ddio_in + #( + .async_mode(ASYNC_MODE), + .sync_mode(SYNC_MODE), + .power_up(DDIO_REG_POWER_UP), + .invert_input_clock(INVERT_INPUT_CLOCK) + ) fr_in_ddio ( + .datain(buf_in), + .clk (inclock_wire), + .ena(inclocken_wire), + .regouthi(ddr_input[1]), + .regoutlo(ddr_input[0]), + .clkout(fr_clock) + `ifndef ALTERA_RESERVED_QIS + , + .sreset(1'b0), + .areset(1'b0), + .dfflo(), + .devpor(1'b1), + .devclrn(1'b1), + .halfrateresyncclk(1'b0) + `endif + ); + end + end + end + else if (ENABLE_PHASE_DETECTOR_FOR_CK == "true") + begin + assign mimic_clock = buf_in; + end + else + begin: in_path_ddr + wire input_cell_l_q; + wire input_aset; + + assign input_aset = ( ASYNC_MODE == "clear") ? !aset : aset; + + fiftyfivenm_ff input_cell_l ( + .clk(inclock_wire), + .d(buf_in), + .clrn(input_aset), + .ena(inclocken_wire), + .q(input_cell_l_q) + ); + + fiftyfivenm_ff input_latch_l ( + .clk(~inclock_wire), + .d(input_cell_l_q), + .clrn(input_aset), + .ena(inclocken_wire), + .q(ddr_input[0]) + ); + + fiftyfivenm_ff input_cell_h ( + .clk(~inclock_wire), + .d(buf_in), + .clrn(input_aset), + .ena(inclocken_wire), + .q(ddr_input[1]) + ); + + end + end + else if (REGISTER_MODE == "single-register") + begin: in_path_sdr + reg reg_data_in /* synthesis altera_attribute="FAST_INPUT_REGISTER=on" */; + always @(posedge inclock_wire) begin + reg_data_in <= buf_in; + end + assign ddr_input[0] = reg_data_in; + end + else + begin: in_path_reg_none + assign ddr_input[0] = buf_in; + end + + assign dout[DATA_SIZE - 1:0] = ddr_input[DATA_SIZE - 1:0]; + + end + endgenerate + + generate + if (PIN_TYPE == "output" || PIN_TYPE == "bidir") + begin + if(BUFFER_TYPE == "pseudo_differential") + begin: pseudo_diff_output_buf + + wire wire_pseudo_diff_o; + wire wire_pseudo_diff_o_bar; + + fiftyfivenm_io_obuf + #( + .bus_hold(BUS_HOLD), + .open_drain_output(OPEN_DRAIN_OUTPUT) + ) obuf_a ( + .i(wire_pseudo_diff_o), + .oe(~oe_out), + .o(pad), + .obar() + `ifndef ALTERA_RESERVED_QIS + , + .seriesterminationcontrol(16'b0), + .devoe(1'b1) + `endif + ); + + fiftyfivenm_io_obuf + #( + .bus_hold(BUS_HOLD), + .open_drain_output(OPEN_DRAIN_OUTPUT) + ) obuf_a_bar ( + .i(wire_pseudo_diff_o_bar), + .oe(~oe_out), + .o(pad_b), + .obar() + `ifndef ALTERA_RESERVED_QIS + , + .seriesterminationcontrol(16'b0), + .devoe(1'b1) + `endif + ); + + fiftyfivenm_pseudo_diff_out pseudo_diff_a + ( + .i(din_ddr), + .o(wire_pseudo_diff_o), + .obar(wire_pseudo_diff_o_bar) + ); + + + + end + else if (BUFFER_TYPE == "true_differential") + begin: true_diff_output_buf + fiftyfivenm_io_obuf + #( + .bus_hold(BUS_HOLD), + .open_drain_output(OPEN_DRAIN_OUTPUT) + ) obuf ( + .i(din_ddr), + .oe(~oe_out), + .o(pad), + .obar(pad_b) + `ifndef ALTERA_RESERVED_QIS + , + .seriesterminationcontrol(16'b0), + .devoe(1'b1) + `endif + ); + end + else + begin: output_buf + fiftyfivenm_io_obuf + #( + .bus_hold(BUS_HOLD), + .open_drain_output(OPEN_DRAIN_OUTPUT) + ) obuf ( + .i(din_ddr), + .oe(~oe_out), + .o(pad), + .obar() + `ifndef ALTERA_RESERVED_QIS + , + .seriesterminationcontrol(16'b0), + .devoe(1'b1) + `endif + ); + end + end + endgenerate + + assign nsleep_in = (ENABLE_NSLEEP_PORT == "true") ? nsleep : 1'b1; + + generate + if (PIN_TYPE == "input" || PIN_TYPE == "bidir") + begin + if(BUFFER_TYPE == "true_differential" || BUFFER_TYPE == "pseudo_differential") + begin: diff_input_buf + if (ENABLE_NSLEEP_PORT == "true") + begin: diff_input_buf_with_nsleep + fiftyfivenm_io_ibuf + #( + .bus_hold(BUS_HOLD) + ) ibuf ( + .i(pad), + .ibar(pad_b), + .o(buf_in), + .nsleep(nsleep_in) + ); + end + else + begin: diff_input_buf_without_nsleep + fiftyfivenm_io_ibuf + #( + .bus_hold(BUS_HOLD) + ) ibuf ( + .i(pad), + .ibar(pad_b), + .o(buf_in) + ); + end + end + else + begin:input_buf + if (ENABLE_NSLEEP_PORT == "true") + begin: input_buf_with_nsleep + fiftyfivenm_io_ibuf + #( + .bus_hold(BUS_HOLD) + ) ibuf ( + .i(pad), + .o(buf_in), + .nsleep(nsleep_in) + `ifndef ALTERA_RESERVED_QIS + , + .ibar(1'b0) + `endif + ); + end + else + begin: input_buf_without_nsleep + fiftyfivenm_io_ibuf + #( + .bus_hold(BUS_HOLD) + ) ibuf ( + .i(pad), + .o(buf_in) + `ifndef ALTERA_RESERVED_QIS + , + .ibar(1'b0) + `endif + ); + end + end + end + endgenerate + + generate + if (PIN_TYPE == "output") + begin + assign dout = {DATA_SIZE{1'b0}}; + end + + if (PIN_TYPE == "output" || REGISTER_MODE != "ddr" || USE_ENHANCED_DDR_HIO_REGISTER == "false") + begin + assign fr_clock = 1'b0; + end + + if (PIN_TYPE == "input" || PIN_TYPE == "output" || REGISTER_MODE != "ddr" || ENABLE_PHASE_DETECTOR_FOR_CK == "false") + begin + assign mimic_clock = 1'b0; + end + endgenerate + +endmodule + +module altera_gpio_lite( + inclock, + outclock, + inclocken, + outclocken, + oe, + din, + dout, + pad_io, + pad_io_b, + pad_in, + pad_in_b, + pad_out, + pad_out_b, + aset, + aclr, + phy_mem_clock, + sclr, + hr_clock, + fr_clock, + invert_hr_clock, + mimic_clock, + nsleep +); + + parameter PIN_TYPE = "output"; + parameter BUFFER_TYPE = "single-ended"; + parameter REGISTER_MODE = "bypass"; + parameter SIZE = 4; + parameter ASYNC_MODE = "none"; + parameter SYNC_MODE = "none"; + parameter BUS_HOLD = "false"; + parameter SET_REGISTER_OUTPUTS_HIGH = "false"; + parameter INVERT_OUTPUT = "false"; + parameter INVERT_INPUT_CLOCK = "false"; + parameter INVERT_OUTPUT_CLOCK = "false"; + parameter INVERT_OE_INCLOCK = "false"; + parameter USE_ONE_REG_TO_DRIVE_OE = "false"; + parameter USE_DDIO_REG_TO_DRIVE_OE = "false"; + parameter OPEN_DRAIN_OUTPUT = "false"; + parameter USE_ADVANCED_DDR_FEATURES = "false"; + parameter USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY = "false"; + parameter INVERT_CLKDIV_INPUT_CLOCK = "false"; + parameter ENABLE_HR_CLOCK = "false"; + parameter ENABLE_OE_HALF_CYCLE_DELAY = "true"; + parameter ENABLE_OE_PORT = "false"; + parameter ENABLE_CLOCK_ENA_PORT = "false"; + parameter ENABLE_PHASE_INVERT_CTRL_PORT = "false"; + parameter ENABLE_PHASE_DETECTOR_FOR_CK = "false"; + parameter ENABLE_NSLEEP_PORT = "false"; + + localparam USE_ENHANCED_DDR_HIO_REGISTER = USE_ADVANCED_DDR_FEATURES; + localparam BYPASS_THREE_QUARTER_REGISTER = (USE_ADVANCED_DDR_FEATURES == "true") ? "false" : "true"; + localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? 2 : 1; + + input inclock; + input outclock; + input inclocken; + input outclocken; + input [SIZE - 1:0] oe; + input [SIZE - 1:0] nsleep; + input [SIZE * DATA_SIZE - 1:0] din; + output [SIZE * DATA_SIZE - 1:0] dout; + inout [SIZE - 1:0] pad_io; + inout [SIZE - 1:0] pad_io_b; + input [SIZE - 1:0] pad_in; + input [SIZE - 1:0] pad_in_b; + output [SIZE - 1:0] pad_out; + output [SIZE - 1:0] pad_out_b; + input aset; + input aclr; + input sclr; + input phy_mem_clock; + input invert_hr_clock; + output [SIZE - 1:0] fr_clock; + output wire hr_clock; + output [SIZE - 1:0] mimic_clock; + + wire [SIZE * DATA_SIZE - 1:0] din_reordered; + wire [SIZE * DATA_SIZE - 1:0] dout_reordered; + wire aclr_aset_wire; + wire sclr_wire; + wire [SIZE - 1:0] pad_io; + wire [SIZE - 1:0] pad_io_b; + + + assign aclr_aset_wire = (ASYNC_MODE == "clear") ? aclr : (ASYNC_MODE == "preset") ? aset : 1'b1; + assign sclr_wire = (SYNC_MODE == "clear") ? sclr : 1'b0; + + generate + if (PIN_TYPE == "input") + begin + assign pad_io = pad_in; + assign pad_io_b = pad_in_b; + assign pad_out = {SIZE{1'b0}}; + assign pad_out_b = {SIZE{1'b0}}; + end + else if (PIN_TYPE == "output") + begin + assign pad_out = pad_io; + assign pad_out_b = pad_io_b; + end + else begin + assign pad_out = {SIZE{1'b0}}; + assign pad_out_b = {SIZE{1'b0}}; + end + endgenerate + + genvar j, k; + generate + begin : reorder + for(j = 0; j < SIZE ; j = j + 1) begin : j_loop + for(k = 0; k < DATA_SIZE; k = k + 1) begin : k_d_loop + assign din_reordered[j * DATA_SIZE + k] = din[j + k * SIZE]; + assign dout[j + k * SIZE] = dout_reordered[j * DATA_SIZE + k]; + end + end + end + endgenerate + + genvar i; + generate + begin : gpio_one_bit + for(i = 0 ; i < SIZE ; i = i + 1) begin : i_loop + wire oe_wire; + wire nsleep_wire; + + + assign oe_wire = (PIN_TYPE == "output" && ENABLE_OE_PORT == "false") ? 1'b1 : + (PIN_TYPE == "input") ? 1'b0 : oe[i]; + + + assign nsleep_wire = (PIN_TYPE == "input" && ENABLE_NSLEEP_PORT == "false") ? 1'b1 : + (PIN_TYPE == "output") ? 1'b0 : nsleep[i]; + + altgpio_one_bit #( + .PIN_TYPE(PIN_TYPE), + .BUFFER_TYPE(BUFFER_TYPE), + .REGISTER_MODE(REGISTER_MODE), + .ASYNC_MODE(ASYNC_MODE), + .SYNC_MODE(SYNC_MODE), + .BUS_HOLD(BUS_HOLD), + .SET_REGISTER_OUTPUTS_HIGH(SET_REGISTER_OUTPUTS_HIGH), + .USE_ENHANCED_DDR_HIO_REGISTER(USE_ENHANCED_DDR_HIO_REGISTER), + .USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY(USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY), + .BYPASS_THREE_QUARTER_REGISTER(BYPASS_THREE_QUARTER_REGISTER), + .INVERT_OUTPUT(INVERT_OUTPUT), + .INVERT_INPUT_CLOCK(INVERT_INPUT_CLOCK), + .INVERT_OUTPUT_CLOCK(INVERT_OUTPUT_CLOCK), + .INVERT_OE_INCLOCK(INVERT_OE_INCLOCK), + .USE_ONE_REG_TO_DRIVE_OE(USE_ONE_REG_TO_DRIVE_OE), + .USE_DDIO_REG_TO_DRIVE_OE(USE_DDIO_REG_TO_DRIVE_OE), + .OPEN_DRAIN_OUTPUT(OPEN_DRAIN_OUTPUT), + .ENABLE_OE_HALF_CYCLE_DELAY(ENABLE_OE_HALF_CYCLE_DELAY), + .ENABLE_CLOCK_ENA_PORT(ENABLE_CLOCK_ENA_PORT), + .ENABLE_HR_CLOCK(ENABLE_HR_CLOCK), + .ENABLE_PHASE_DETECTOR_FOR_CK(ENABLE_PHASE_DETECTOR_FOR_CK), + .ENABLE_NSLEEP_PORT(ENABLE_NSLEEP_PORT) + ) altgpio_bit_i ( + .inclock(inclock), + .outclock(outclock), + .phy_mem_clock(phy_mem_clock), + .inclocken(inclocken), + .outclocken(outclocken), + .oe(oe_wire), + .din(din_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]), + .dout(dout_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]), + .pad(pad_io[i]), + .pad_b(pad_io_b[i]), + .aset(aclr_aset_wire), + .sclr(sclr_wire), + .fr_clock(fr_clock[i]), + .hr_clock(hr_clock), + .mimic_clock(mimic_clock[i]), + .nsleep(nsleep_wire) + ); + end + end + endgenerate + + generate + if ((PIN_TYPE == "input" || PIN_TYPE == "bidir") && (ENABLE_HR_CLOCK == "true")) + begin + if (ENABLE_PHASE_INVERT_CTRL_PORT == "true") + begin + if (SYNC_MODE == "clear") + begin : clock_divider_sync_mode_invert_hr_clock + fiftyfivenm_io_clock_divider + #( + .invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK), + .use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT), + .sync_mode(SYNC_MODE) + ) io_clkdiv ( + .clk(inclock), + .phaseinvertctrl(invert_hr_clock), + .sreset(sclr_wire), + .clkout(hr_clock) + ); + end + else + begin : clock_divider_invert_hr_clock + fiftyfivenm_io_clock_divider + #( + .invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK), + .use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT), + .sync_mode(SYNC_MODE) + ) io_clkdiv ( + .clk(inclock), + .phaseinvertctrl(invert_hr_clock), + .clkout(hr_clock) + `ifndef ALTERA_RESERVED_QIS + , + .sreset(1'b0) + `endif + ); + end + end + else + begin + if (SYNC_MODE == "clear") + begin : clock_divider_sync_mode + fiftyfivenm_io_clock_divider + #( + .invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK), + .use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT), + .sync_mode(SYNC_MODE) + ) io_clkdiv ( + .clk(inclock), + .sreset(sclr_wire), + .clkout(hr_clock) + `ifndef ALTERA_RESERVED_QIS + , + .phaseinvertctrl(1'b0) + `endif + ); + end + else + begin : clock_divider + fiftyfivenm_io_clock_divider + #( + .invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK), + .use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT), + .sync_mode(SYNC_MODE) + ) io_clkdiv ( + .clk(inclock), + .clkout(hr_clock) + `ifndef ALTERA_RESERVED_QIS + , + .sreset(1'b0), + .phaseinvertctrl(1'b0) + `endif + ); + end + end + end + else begin + assign hr_clock = 1'b0; + end + endgenerate + +endmodule diff --git a/fw/rtl/intel/pll/pll.ppf b/fw/rtl/intel/pll/pll.ppf new file mode 100644 index 0000000..4c05ee3 --- /dev/null +++ b/fw/rtl/intel/pll/pll.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/fw/rtl/intel/pll/pll.qip b/fw/rtl/intel/pll/pll.qip new file mode 100644 index 0000000..694a4dc --- /dev/null +++ b/fw/rtl/intel/pll/pll.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "20.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/fw/rtl/intel/pll/pll.v b/fw/rtl/intel/pll/pll.v new file mode 100644 index 0000000..493b114 --- /dev/null +++ b/fw/rtl/intel/pll/pll.v @@ -0,0 +1,341 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 20.1.0 Build 711 06/05/2020 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2020 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + inclk0, + c0, + c1, + locked); + + input inclk0; + output c0; + output c1; + output locked; + + wire [0:0] sub_wire2 = 1'h0; + wire [4:0] sub_wire3; + wire sub_wire6; + wire sub_wire0 = inclk0; + wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; + wire [1:1] sub_wire5 = sub_wire3[1:1]; + wire [0:0] sub_wire4 = sub_wire3[0:0]; + wire c0 = sub_wire4; + wire c1 = sub_wire5; + wire locked = sub_wire6; + + altpll altpll_component ( + .inclk (sub_wire1), + .clk (sub_wire3), + .locked (sub_wire6), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 5, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 9, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 5, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 9, + altpll_component.clk1_phase_shift = "-2778", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = "MAX 10", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "ON", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "90.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "90.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "90.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "90.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-90.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2778" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/fw/rtl/n64_pi.v b/fw/rtl/n64_pi.v new file mode 100644 index 0000000..10f2009 --- /dev/null +++ b/fw/rtl/n64_pi.v @@ -0,0 +1,95 @@ +module n64_pi ( + input i_clk, + input i_reset, + + input [1:0] i_n64_pi_alel, + input [1:0] i_n64_pi_aleh, + input i_n64_pi_read, + input i_n64_pi_write, + input [15:0] i_n64_pi_ad, + output reg [15:0] o_n64_pi_ad, + output o_n64_pi_ad_mode, + + output reg o_read_rq, + output reg o_write_rq, + input i_ack, + output reg [31:0] o_address, + input [31:0] i_data, + output reg [31:0] o_data, + + input i_address_valid +); + + reg r_last_n64_pi_alel; + reg r_last_n64_pi_aleh; + reg r_last_n64_pi_read; + reg r_last_n64_pi_write; + + reg r_first_transfer; + reg r_word_select; + reg [31:0] r_data_i_buffer; + reg [15:0] r_word_buffer; + reg r_address_valid; + reg r_address_valid_buffer; + + wire w_aleh_valid = (&i_n64_pi_alel) && (&i_n64_pi_aleh); + wire w_alel_valid = (&i_n64_pi_alel) && (~|i_n64_pi_aleh); + wire w_address_op = r_last_n64_pi_alel && !i_n64_pi_alel[0] && !i_n64_pi_aleh[0]; + wire w_read_op = r_last_n64_pi_read && !i_n64_pi_read; + wire w_write_op = r_last_n64_pi_write && !i_n64_pi_write; + wire w_bus_read_op = w_read_op && r_word_select; + wire w_bus_write_op = w_write_op && !r_word_select; + + wire w_address_increment = w_bus_read_op || (w_bus_write_op && !r_first_transfer); + + assign o_n64_pi_ad_mode = !i_reset && !i_n64_pi_alel[0] && !i_n64_pi_aleh[0] && !i_n64_pi_read && !r_last_n64_pi_read && r_address_valid; + + always @(posedge i_clk) begin + r_last_n64_pi_alel <= i_n64_pi_alel[0]; + r_last_n64_pi_aleh <= i_n64_pi_aleh[0]; + r_last_n64_pi_read <= i_n64_pi_read; + r_last_n64_pi_write <= i_n64_pi_write; + + o_read_rq <= 1'b0; + o_write_rq <= 1'b0; + + if (!i_reset) begin + o_read_rq <= w_bus_read_op || w_address_op; + o_write_rq <= w_bus_write_op; + + if (w_aleh_valid) begin + o_address <= {i_n64_pi_ad, o_address[15:0]}; + end + if (w_alel_valid) begin + o_address <= {o_address[31:16], i_n64_pi_ad[15:1], 1'b0}; + end + if (w_address_op) begin + r_first_transfer <= 1'b1; + r_word_select <= 1'b1; + end + if (w_read_op || w_write_op) begin + r_word_select <= ~r_word_select; + o_address <= {o_address[31:10], (o_address[9:0] + {w_address_increment, 2'b00})}; + end + if (w_write_op && !r_word_select) begin + r_first_transfer <= 1'b0; + end + if (w_read_op) begin + {o_n64_pi_ad, r_word_buffer} <= r_word_select ? r_data_i_buffer : {r_word_buffer, 16'hXXXX}; + end + if (w_write_op) begin + o_data <= {o_data[15:0], i_n64_pi_ad}; + end + if (w_bus_read_op) begin + r_address_valid <= r_address_valid_buffer; + end + if (o_read_rq) begin + r_address_valid_buffer <= i_address_valid; + end + if (i_ack) begin + r_data_i_buffer <= i_data; + end + end + end + +endmodule diff --git a/fw/rtl/pc.v b/fw/rtl/pc.v new file mode 100644 index 0000000..d3f8964 --- /dev/null +++ b/fw/rtl/pc.v @@ -0,0 +1,289 @@ +module pc ( + input i_clk, + input i_reset, + + input i_ftdi_clk, + input i_ftdi_cs, + input i_ftdi_do, + output reg o_ftdi_di, + + output reg o_read_rq, + output reg o_write_rq, + input i_ack, + output reg [31:0] o_address, + input [31:0] i_data, + output reg [31:0] o_data, + + input i_bus_active, + output reg o_n64_disable +); + + // Command ids + + localparam [7:0] CMD_STATUS = 8'h00; + localparam [7:0] CMD_CONFIG = 8'h10; + localparam [7:0] CMD_ADDR = 8'h20; + localparam [7:0] CMD_READ_LENGTH = 8'h30; + localparam [7:0] CMD_WRITE = 8'h40; + localparam [7:0] CMD_READ = 8'h50; + localparam [7:0] CMD_CART_RESET = 8'hFC; + localparam [7:0] CMD_FLUSH_WRITE = 8'hFD; + localparam [7:0] CMD_FLUSH_READ = 8'hFE; + localparam [7:0] CMD_SPI_RESET = 8'hFF; + + // SPI [de]serializer + + reg [4:0] r_spi_bit_counter; + reg [30:0] r_spi_i_shift; + reg [7:0] r_spi_cmd; + reg r_spi_cmd_valid; + + reg r_fifo_pc_to_bus_flush; + reg r_fifo_bus_to_pc_flush; + + reg r_fifo_pc_to_bus_rq; + reg r_fifo_bus_to_pc_rq; + + wire [31:0] w_fifo_bus_to_pc_data; + + wire [10:0] w_fifo_pc_to_bus_usedw; + wire [10:0] w_fifo_bus_to_pc_usedw; + + reg r_n64_disabled_ff1, r_n64_disabled_ff2; + reg r_address_inc_ff1, r_address_inc_ff2; + + wire [31:0] w_spi_status = { + 8'hAA, // Test control byte + r_address_inc_ff2, + r_n64_disabled_ff2, + w_fifo_pc_to_bus_usedw, + w_fifo_bus_to_pc_usedw, + }; + + // SPI bit control and command stage + + always @(posedge i_ftdi_clk or posedge i_ftdi_cs or posedge i_reset) begin + if (i_ftdi_cs || i_reset) begin + r_spi_bit_counter <= 5'd0; + r_spi_cmd <= 8'd0; + r_spi_cmd_valid <= 1'b0; + end else begin + r_spi_bit_counter <= r_spi_bit_counter + 5'd1; + if (&r_spi_bit_counter[2:0] && !r_spi_cmd_valid) begin + r_spi_bit_counter <= 5'd0; + r_spi_cmd <= {r_spi_i_shift[6:0], i_ftdi_do}; + r_spi_cmd_valid <= 1'b1; + end + end + end + + // SPI input shift register + + always @(posedge i_ftdi_clk) begin + r_spi_i_shift <= {r_spi_i_shift[29:0], i_ftdi_do}; + end + + // SPI command control signals + + always @(posedge i_ftdi_clk or posedge i_ftdi_cs or posedge i_reset) begin + if (i_ftdi_cs || i_reset) begin + r_fifo_pc_to_bus_flush <= 1'b0; + r_fifo_bus_to_pc_flush <= 1'b0; + r_fifo_pc_to_bus_rq <= 1'b0; + r_fifo_bus_to_pc_rq <= 1'b0; + end else begin + if (&r_spi_bit_counter[2:0] && !r_spi_cmd_valid) begin + case ({r_spi_i_shift[6:0], i_ftdi_do}) + CMD_FLUSH_WRITE: r_fifo_pc_to_bus_flush <= 1'b1; + CMD_FLUSH_READ: r_fifo_bus_to_pc_flush <= 1'b1; + CMD_SPI_RESET: begin + r_fifo_pc_to_bus_flush <= 1'b1; + r_fifo_bus_to_pc_flush <= 1'b1; + end + endcase + end + if (r_spi_bit_counter == 5'd30) begin + case (r_spi_cmd) + CMD_CONFIG, CMD_ADDR, CMD_READ_LENGTH, CMD_WRITE, CMD_CART_RESET: begin + r_fifo_pc_to_bus_rq <= 1'b1; + end + CMD_READ: r_fifo_bus_to_pc_rq <= 1'b1; + endcase + end else begin + r_fifo_pc_to_bus_rq <= 1'b0; + r_fifo_bus_to_pc_rq <= 1'b0; + end + end + end + + // SPI output data stage + + always @(negedge i_ftdi_clk or posedge i_ftdi_cs or posedge i_reset) begin + if (i_ftdi_cs || i_reset) begin + o_ftdi_di <= 1'b0; + end else begin + if (r_spi_cmd_valid) begin + case (r_spi_cmd) + CMD_STATUS: o_ftdi_di <= w_spi_status[5'd31 - r_spi_bit_counter]; + CMD_READ: o_ftdi_di <= w_fifo_bus_to_pc_data[5'd31 - r_spi_bit_counter]; + default: o_ftdi_di <= 1'b1; + endcase + end else begin + o_ftdi_di <= 1'b0; + end + end + end + + // sys_clk -> spi_clk signal synchronization + + reg r_address_inc; + + always @(posedge i_ftdi_clk) begin + {r_n64_disabled_ff2, r_n64_disabled_ff1} <= {r_n64_disabled_ff1, o_n64_disable}; + {r_address_inc_ff2, r_address_inc_ff1} <= {r_address_inc_ff1, r_address_inc}; + end + + // FIFOs + + reg r_fifo_pc_to_bus_rdreq; + wire [39:0] w_fifo_pc_to_bus_q; + wire w_fifo_pc_to_bus_rdempty; + + wire [7:0] w_fifo_pc_to_bus_cmd; + wire [31:0] w_fifo_pc_to_bus_data; + + assign {w_fifo_pc_to_bus_cmd, w_fifo_pc_to_bus_data} = w_fifo_pc_to_bus_q; + + wire w_fifo_bus_to_pc_wrfull; + + reg r_bus_read_in_progress; + + fifo_pc_to_bus fifo_pc_to_bus_inst ( + .aclr(r_fifo_pc_to_bus_flush), + + .wrclk(i_ftdi_clk || i_ftdi_cs), + .wrreq(r_fifo_pc_to_bus_rq), + .data({r_spi_cmd, r_spi_i_shift, i_ftdi_do}), + .wrusedw(w_fifo_pc_to_bus_usedw), + + .rdclk(i_clk), + .rdreq(r_fifo_pc_to_bus_rdreq), + .q(w_fifo_pc_to_bus_q), + .rdempty(w_fifo_pc_to_bus_rdempty) + ); + + fifo_bus_to_pc fifo_bus_to_pc_inst ( + .aclr(r_fifo_bus_to_pc_flush), + + .rdclk(i_ftdi_clk || i_ftdi_cs), + .rdreq(r_fifo_bus_to_pc_rq), + .q(w_fifo_bus_to_pc_data), + .rdusedw(w_fifo_bus_to_pc_usedw), + + .wrclk(i_clk), + .wrreq(i_ack && r_bus_read_in_progress), + .data(i_data), + .wrfull(w_fifo_bus_to_pc_wrfull), + ); + + // Bus controller + + reg r_cmd_config; + reg r_cmd_addr; + reg r_cmd_read_length; + reg r_cmd_write; + reg r_cmd_cart_reset; + + always @(posedge i_clk) begin + r_cmd_config <= w_fifo_pc_to_bus_cmd == CMD_CONFIG; + r_cmd_addr <= w_fifo_pc_to_bus_cmd == CMD_ADDR; + r_cmd_read_length <= w_fifo_pc_to_bus_cmd == CMD_READ_LENGTH; + r_cmd_write <= w_fifo_pc_to_bus_cmd == CMD_WRITE; + r_cmd_cart_reset <= w_fifo_pc_to_bus_cmd == CMD_CART_RESET; + end + + reg r_bus_read_pending_rq; + reg [23:0] r_bus_read_remaining_words; // Max 64 MB + + reg r_bus_write_in_progress; + + always @(posedge i_clk or posedge i_reset) begin + if (i_reset) begin + o_read_rq <= 1'b0; + o_write_rq <= 1'b0; + o_n64_disable <= 1'b0; + r_address_inc <= 1'b1; + r_fifo_pc_to_bus_rdreq <= 1'b0; + r_bus_read_pending_rq <= 1'b0; + r_bus_read_in_progress <= 1'b0; + r_bus_write_in_progress <= 1'b0; + end else begin + o_read_rq <= 1'b0; + o_write_rq <= 1'b0; + r_fifo_pc_to_bus_rdreq <= 1'b0; + + if (!w_fifo_pc_to_bus_rdempty && !r_fifo_pc_to_bus_rdreq && !r_bus_read_in_progress && !r_bus_write_in_progress) begin + if (r_cmd_config && !i_bus_active) begin + {r_address_inc, o_n64_disable} <= w_fifo_pc_to_bus_data[1:0]; + r_fifo_pc_to_bus_rdreq <= 1'b1; + end + if (r_cmd_addr) begin + o_address <= w_fifo_pc_to_bus_data; + r_fifo_pc_to_bus_rdreq <= 1'b1; + end + if (r_cmd_read_length) begin + if (o_n64_disable) begin + r_bus_read_pending_rq <= 1'b1; + r_bus_read_remaining_words <= w_fifo_pc_to_bus_data[23:0]; + r_bus_read_in_progress <= 1'b1; + end else begin + r_fifo_pc_to_bus_rdreq <= 1'b1; + end + end + if (r_cmd_write) begin + if (o_n64_disable) begin + o_write_rq <= 1'b1; + o_data <= w_fifo_pc_to_bus_data; + r_bus_write_in_progress <= 1'b1; + end else begin + r_fifo_pc_to_bus_rdreq <= 1'b1; + end + end + end + + if (i_ack) o_address[31:2] <= o_address[31:2] + r_address_inc; + + if (!w_fifo_bus_to_pc_wrfull && r_bus_read_pending_rq) begin + o_read_rq <= 1'b1; + r_bus_read_pending_rq <= 1'b0; + end + + if (i_ack && r_bus_read_in_progress) begin + if (r_bus_read_remaining_words > 24'd0) begin + r_bus_read_pending_rq <= 1'b1; + r_bus_read_remaining_words <= r_bus_read_remaining_words - 24'd1; + end else begin + r_fifo_pc_to_bus_rdreq <= 1'b1; + r_bus_read_in_progress <= 1'b0; + end + end + + if (i_ack && r_bus_write_in_progress) begin + r_fifo_pc_to_bus_rdreq <= 1'b1; + r_bus_write_in_progress <= 1'b0; + end + + if (!w_fifo_pc_to_bus_rdempty && !r_fifo_pc_to_bus_rdreq && r_cmd_cart_reset) begin + o_read_rq <= 1'b0; + o_write_rq <= 1'b0; + o_n64_disable <= 1'b0; + r_address_inc <= 1'b1; + r_fifo_pc_to_bus_rdreq <= 1'b1; + r_bus_read_pending_rq <= 1'b0; + r_bus_read_in_progress <= 1'b0; + r_bus_write_in_progress <= 1'b0; + end + end + end + +endmodule diff --git a/fw/rtl/sdram.v b/fw/rtl/sdram.v new file mode 100644 index 0000000..e18b0e8 --- /dev/null +++ b/fw/rtl/sdram.v @@ -0,0 +1,133 @@ +module sdram ( + input i_clk, + input i_reset, + + output o_sdram_cs, + output o_sdram_ras, + output o_sdram_cas, + output o_sdram_we, + output [1:0] o_sdram_ba, + output [12:0] o_sdram_a, + input [15:0] i_sdram_dq, + output [15:0] o_sdram_dq, + output o_sdram_dq_mode, + + input i_select, + input i_read_rq, + input i_write_rq, + output reg o_ack, + input [31:0] i_address, + input [31:0] i_data, + output reg [31:0] o_data +); + + reg r_wb_cyc; + reg r_wb_stb; + + wire w_wb_cyc; + wire w_wb_stb; + wire [31:0] w_wb_addr; + wire w_wb_ack; + wire w_wb_stall; + wire [31:0] w_wb_o_data; + + assign w_wb_cyc = w_wb_stb || r_wb_cyc; + assign w_wb_stb = i_select && !w_wb_stall && (i_read_rq || i_write_rq || r_wb_stb); + + always @(posedge i_clk or posedge i_reset) begin + if (i_reset) begin + r_wb_cyc <= 1'b0; + end else begin + if (w_wb_stb) begin + r_wb_cyc <= 1'b1; + end else if (w_wb_ack) begin + r_wb_cyc <= 1'b0; + end + end + end + + // FIXME: Ugly solution for 16-bit address read align + + reg r_unaligned_access; + reg r_next_word; + + assign w_wb_addr = i_address + {r_next_word, 2'b00}; + + always @(posedge i_clk or posedge i_reset) begin + if (i_reset) begin + o_ack <= 1'b0; + r_wb_stb <= 1'b0; + r_unaligned_access <= 1'b0; + r_next_word <= 1'b0; + end else begin + o_ack <= 1'b0; + r_wb_stb <= 1'b0; + + if (i_read_rq) begin + if (!i_address[1]) begin + r_unaligned_access <= 1'b0; + r_next_word <= 1'b0; + end else begin + r_unaligned_access <= 1'b1; + r_next_word <= 1'b0; + end + end + if (w_wb_ack) begin + if (!r_unaligned_access) begin + o_data <= w_wb_o_data; + o_ack <= 1'b1; + end else begin + if (!r_next_word) begin + o_data[31:16] <= w_wb_o_data[15:0]; + r_wb_stb <= 1'b1; + r_next_word <= 1'b1; + end else begin + o_ack <= 1'b1; + o_data[15:0] <= w_wb_o_data[31:16]; + r_unaligned_access <= 1'b0; + r_next_word <= 1'b0; + end + end + end + end + end + + // Weird shift register required by this module + // https://github.com/ZipCPU/arrowzip/blob/master/rtl/arrowzip/toplevel.v#L176 + + reg [15:0] r_sdram_dq_ext_clk; + reg [15:0] r_sdram_dq; + + always @(posedge i_clk) begin + {r_sdram_dq, r_sdram_dq_ext_clk} <= {r_sdram_dq_ext_clk, i_sdram_dq}; + end + + wbsdram wbsdram_inst ( + .i_clk(i_clk), + + .i_wb_cyc(w_wb_cyc), + .i_wb_stb(w_wb_stb), // FIXME: Currently strobe can be missed when w_wb_stall is high + .i_wb_we(i_write_rq), + .i_wb_addr(w_wb_addr[31:2]), + .i_wb_data(i_data), + .i_wb_sel({4'b1111}), // No need to control this signal + .o_wb_ack(w_wb_ack), + .o_wb_stall(w_wb_stall), + .o_wb_data(w_wb_o_data), + + .o_ram_cs_n(o_sdram_cs), + // .o_ram_cke(), // No connection on PCB + .o_ram_ras_n(o_sdram_ras), + .o_ram_cas_n(o_sdram_cas), + .o_ram_we_n(o_sdram_we), + .o_ram_bs(o_sdram_ba), + .o_ram_addr(o_sdram_a), + .o_ram_dmod(o_sdram_dq_mode), + .i_ram_data(r_sdram_dq), + .o_ram_data(o_sdram_dq) + // .o_ram_dqm(), // No connection on PCB + + // .o_debug() // No need for this signal + ); + +endmodule diff --git a/fw/rtl/top.v b/fw/rtl/top.v new file mode 100644 index 0000000..21eac5d --- /dev/null +++ b/fw/rtl/top.v @@ -0,0 +1,387 @@ +module top ( + input i_clk, + + input i_ftdi_clk, + input i_ftdi_cs, + input i_ftdi_do, + output o_ftdi_di, + + input i_n64_nmi, + input i_n64_reset, + + input i_n64_pi_alel, + input i_n64_pi_aleh, + input i_n64_pi_read, + input i_n64_pi_write, + inout [15:0] io_n64_pi_ad, + + input i_n64_si_clk, + inout io_n64_si_dq, + + input i_n64_cic_clk, + inout io_n64_cic_dq, + + output o_sdram_clk, + output o_sdram_cs, + output o_sdram_cas, + output o_sdram_ras, + output o_sdram_we, + output [1:0] o_sdram_ba, + output [12:0] o_sdram_a, + inout [15:0] io_sdram_dq, + + output o_sd_clk, + inout io_sd_cmd, + inout [3:0] io_sd_dat, + + output o_flash_clk, + output o_flash_cs, + inout [3:0] io_flash_dq, + + output o_sram_clk, + output o_sram_cs, + inout [3:0] io_sram_dq, + + output o_rtc_scl, + inout io_rtc_sda, + + output o_led, + + inout [7:0] io_pmod +); + + // Clock and reset + + wire w_sys_clk; + wire w_sdram_clk; + wire w_pll_lock; + wire w_sys_reset = ~w_pll_lock; + + pll sys_pll( + .inclk0(i_clk), + .c0(w_sys_clk), + .c1(w_sdram_clk), + .locked(w_pll_lock) + ); + + gpio_ddro sdram_clk_ddro( + .outclock(w_sdram_clk), + .outclocken(1'b1), + .din({1'b0, 1'b1}), + .pad_out(o_sdram_clk) + ); + + // Input synchronization + + reg r_n64_nmi_ff1, r_n64_nmi_ff2; + reg r_n64_reset_ff1, r_n64_reset_ff2; + + reg r_n64_alel_ff1, r_n64_alel_ff2; + reg r_n64_aleh_ff1, r_n64_aleh_ff2; + reg r_n64_read_ff1, r_n64_read_ff2; + reg r_n64_write_ff1, r_n64_write_ff2; + + reg r_n64_si_clk_ff1, r_n64_si_clk_ff2; + + reg r_n64_cic_clk_ff1, r_n64_cic_clk_ff2; + + always @(posedge w_sys_clk or posedge w_sys_reset) begin + if (w_sys_reset) begin + r_n64_nmi_ff1 <= 1'b0; + r_n64_nmi_ff2 <= 1'b0; + + r_n64_reset_ff1 <= 1'b0; + r_n64_reset_ff2 <= 1'b0; + + r_n64_alel_ff1 <= 1'b0; + r_n64_alel_ff2 <= 1'b0; + + r_n64_aleh_ff1 <= 1'b0; + r_n64_aleh_ff2 <= 1'b0; + + r_n64_read_ff1 <= 1'b0; + r_n64_read_ff2 <= 1'b0; + + r_n64_write_ff1 <= 1'b0; + r_n64_write_ff2 <= 1'b0; + + r_n64_si_clk_ff1 <= 1'b0; + r_n64_si_clk_ff2 <= 1'b0; + + r_n64_cic_clk_ff1 <= 1'b0; + r_n64_cic_clk_ff2 <= 1'b0; + end else begin + {r_n64_nmi_ff2, r_n64_nmi_ff1} <= {r_n64_nmi_ff1, i_n64_nmi}; + {r_n64_reset_ff2, r_n64_reset_ff1} <= {r_n64_reset_ff1, i_n64_reset}; + + {r_n64_alel_ff2, r_n64_alel_ff1} <= {r_n64_alel_ff1, i_n64_pi_alel}; + {r_n64_aleh_ff2, r_n64_aleh_ff1} <= {r_n64_aleh_ff1, i_n64_pi_aleh}; + {r_n64_read_ff2, r_n64_read_ff1} <= {r_n64_read_ff1, i_n64_pi_read}; + {r_n64_write_ff2, r_n64_write_ff1} <= {r_n64_write_ff1, i_n64_pi_write}; + + {r_n64_si_clk_ff2, r_n64_si_clk_ff1} <= {r_n64_si_clk_ff1, i_n64_si_clk}; + + {r_n64_cic_clk_ff2, r_n64_cic_clk_ff1} <= {r_n64_cic_clk_ff1, i_n64_cic_clk}; + end + end + + // Tri-state connection management + + wire w_n64_pi_ad_mode; + wire [15:0] w_n64_pi_ad_o; + assign io_n64_pi_ad = w_n64_pi_ad_mode ? w_n64_pi_ad_o : 16'hZZZZ; + + wire w_n64_si_dq_o; + assign io_n64_si_dq = w_n64_si_dq_o ? 1'bZ : 1'b0; + + wire w_n64_cic_dq_o; + assign io_n64_cic_dq = w_n64_cic_dq_o ? 1'bZ : 1'b0; + + wire w_sdram_dq_mode; + wire [15:0] w_sdram_dq_o; + assign io_sdram_dq = w_sdram_dq_mode ? w_sdram_dq_o : 16'hZZZZ; + + wire w_sd_cmd_mode; + wire [1:0] w_sd_dat_mode; + wire w_sd_cmd_o; + wire [3:0] w_sd_dat_o; + assign io_sd_cmd = w_sd_cmd_mode ? w_sd_cmd_o : 1'bZ; + assign io_sd_dat = w_sd_dat_mode == 2'b00 ? {3'bZZZ, w_sd_dat_o[0]} : + w_sd_dat_mode == 2'b10 ? w_sd_dat_o : 4'bZZZZ; + + wire [1:0] w_flash_dq_mode; + wire [3:0] w_flash_dq_o; + assign io_flash_dq = w_flash_dq_mode == 2'b00 ? {3'bZZZ, w_flash_dq_o[0]} : + w_flash_dq_mode == 2'b10 ? w_flash_dq_o : 4'bZZZZ; + + wire [1:0] w_sram_dq_mode; + wire [3:0] w_sram_dq_o; + assign io_sram_dq = w_sram_dq_mode == 2'b00 ? {3'bZZZ, w_sram_dq_o[0]} : + w_sram_dq_mode == 2'b10 ? w_sram_dq_o : 4'bZZZZ; + + wire w_rtc_sda_o; + assign io_rtc_sda = w_rtc_sda_o ? 1'bZ : 1'b0; + + // Temporary assignments + + assign w_n64_si_dq_o = 1'b1; + assign w_n64_cic_dq_o = 1'b1; + assign w_sd_cmd_mode = 1'b0; + assign w_sd_dat_mode = 2'b00; + assign w_sram_dq_mode = 2'b00; + assign w_rtc_sda_o = 1'b1; + assign io_pmod = 8'hZZ; + + // Modules connection + + wire w_n64_read_rq; + wire w_n64_write_rq; + wire w_n64_ack; + wire [31:0] w_n64_address; + wire [31:0] w_n64_i_data; + wire [31:0] w_n64_o_data; + + wire w_pc_read_rq; + wire w_pc_write_rq; + wire w_pc_ack; + wire [31:0] w_pc_address; + wire [31:0] w_pc_i_data; + wire [31:0] w_pc_o_data; + + wire w_n64_disable; + + wire w_bus_read_rq; + wire w_bus_write_rq; + wire w_bus_ack; + wire [31:0] w_bus_address; + wire [31:0] w_bus_i_data; + wire [31:0] w_bus_o_data; + + assign w_n64_ack = !w_n64_disable && w_bus_ack; + assign w_pc_ack = w_n64_disable && w_bus_ack; + + assign w_bus_read_rq = w_n64_disable ? w_pc_read_rq : w_n64_read_rq; + assign w_bus_write_rq = w_n64_disable ? w_pc_write_rq : w_n64_write_rq; + assign w_bus_address = w_n64_disable ? w_pc_address : w_n64_address; + assign w_bus_o_data = w_n64_disable ? w_pc_o_data : w_n64_o_data; + + wire w_cart_config_select; + wire w_flash_select; + wire w_flash_cfg_select; + wire w_sdram_select; + + wire w_flash_enable; + wire w_sdram_enable; + + wire w_address_valid; + + wire w_cart_config_ack; + wire [31:0] w_cart_config_o_data; + + wire w_flash_ack; + wire [31:0] w_flash_o_data; + + wire w_sdram_ack; + wire [31:0] w_sdram_o_data; + + reg r_empty_ack; + + assign w_bus_ack = w_cart_config_ack || w_flash_ack || w_sdram_ack || r_empty_ack; + assign w_bus_i_data = w_cart_config_select ? w_cart_config_o_data : + (w_flash_select || w_flash_cfg_select) ? w_flash_o_data : + w_sdram_select ? w_sdram_o_data : 32'hFFFF_FFFF; + + always @(posedge w_sys_clk) begin + r_empty_ack <= !w_address_valid && (w_bus_read_rq || w_bus_write_rq); + end + + // Bus activity signal + + reg r_bus_active; + wire w_bus_active = r_bus_active && !w_bus_ack; + + always @(posedge w_sys_clk or posedge w_sys_reset) begin + if (w_sys_reset) begin + r_bus_active <= 1'b0; + end else begin + if (w_bus_read_rq || w_bus_write_rq) r_bus_active <= 1'b1; + if (w_bus_ack) r_bus_active <= 1'b0; + end + end + + // Modules + + pc pc_inst ( + .i_clk(w_sys_clk), + .i_reset(w_sys_reset), + + .i_ftdi_clk(i_ftdi_clk), + .i_ftdi_cs(i_ftdi_cs), + .i_ftdi_do(i_ftdi_do), + .o_ftdi_di(o_ftdi_di), + + .o_read_rq(w_pc_read_rq), + .o_write_rq(w_pc_write_rq), + .i_ack(w_pc_ack), + .o_address(w_pc_address), + .i_data(w_bus_i_data), + .o_data(w_pc_o_data), + + .i_bus_active(w_bus_active), + .o_n64_disable(w_n64_disable) + ); + + n64_pi n64_pi_inst ( + .i_clk(w_sys_clk), + .i_reset(~r_n64_reset_ff2), + + .i_n64_pi_alel({i_n64_pi_alel, r_n64_alel_ff2}), + .i_n64_pi_aleh({i_n64_pi_aleh, r_n64_aleh_ff2}), + .i_n64_pi_read(r_n64_read_ff2), + .i_n64_pi_write(r_n64_write_ff2), + .i_n64_pi_ad(io_n64_pi_ad), + .o_n64_pi_ad(w_n64_pi_ad_o), + .o_n64_pi_ad_mode(w_n64_pi_ad_mode), + + .o_read_rq(w_n64_read_rq), + .o_write_rq(w_n64_write_rq), + .i_ack(w_n64_ack), + .o_address(w_n64_address), + .i_data(w_bus_i_data), + .o_data(w_n64_o_data), + + .i_address_valid(w_address_valid) + ); + + address_decoder address_decoder_inst ( + .i_address(w_bus_address), + + .o_cart_config(w_cart_config_select), + .o_flash(w_flash_select), + .o_flash_cfg(w_flash_cfg_select), + .o_sdram(w_sdram_select), + + .i_flash_enable(w_flash_enable), + .i_sdram_enable(w_sdram_enable), + + .o_address_valid(w_address_valid) + ); + + cart_config cart_config_inst ( + .i_clk(w_sys_clk), + .i_reset(w_sys_reset), + + .i_n64_reset(~r_n64_reset_ff2), + .i_n64_nmi(~r_n64_nmi_ff2), + + .i_select(w_cart_config_select), + .i_read_rq(w_bus_read_rq), + .i_write_rq(w_bus_write_rq), + .o_ack(w_cart_config_ack), + .i_address(w_bus_address), + .i_data(w_bus_o_data), + .o_data(w_cart_config_o_data), + + .i_n64_disabled(w_n64_disable), + + .o_flash_enable(w_flash_enable), + .o_sdram_enable(w_sdram_enable) + ); + + flash flash_inst ( + .i_clk(w_sys_clk), + .i_reset(w_sys_reset), + + .o_flash_clk(o_flash_clk), + .o_flash_cs(o_flash_cs), + .i_flash_dq(io_flash_dq), + .o_flash_dq(w_flash_dq_o), + .o_flash_dq_mode(w_flash_dq_mode), + + .i_select(w_flash_select), + .i_cfg_select(w_flash_cfg_select), + .i_read_rq(w_bus_read_rq), + .i_write_rq(w_bus_write_rq), + .o_ack(w_flash_ack), + .i_address(w_bus_address), + .i_data(w_bus_o_data), + .o_data(w_flash_o_data) + ); + + sdram sdram_inst ( + .i_clk(w_sys_clk), + .i_reset(w_sys_reset), + + .o_sdram_cs(o_sdram_cs), + .o_sdram_ras(o_sdram_ras), + .o_sdram_cas(o_sdram_cas), + .o_sdram_we(o_sdram_we), + .o_sdram_ba(o_sdram_ba), + .o_sdram_a(o_sdram_a), + .i_sdram_dq(io_sdram_dq), + .o_sdram_dq(w_sdram_dq_o), + .o_sdram_dq_mode(w_sdram_dq_mode), + + .i_select(w_sdram_select), + .i_read_rq(w_bus_read_rq), + .i_write_rq(w_bus_write_rq), + .o_ack(w_sdram_ack), + .i_address(w_bus_address), + .i_data(w_bus_o_data), + .o_data(w_sdram_o_data) + ); + + // LED + + localparam ROLLING_LED_WIDTH = 8; + + reg [(ROLLING_LED_WIDTH-1):0] r_rolling_led; + + assign o_led = |r_rolling_led; + + always @(posedge w_sys_clk or posedge w_sys_reset) begin + if (w_sys_reset) r_rolling_led <= {(ROLLING_LED_WIDTH){1'b0}}; + else r_rolling_led <= {r_rolling_led[(ROLLING_LED_WIDTH-2):0], w_bus_active}; + end + +endmodule diff --git a/hw/.gitignore b/hw/.gitignore new file mode 100644 index 0000000..0e05548 --- /dev/null +++ b/hw/.gitignore @@ -0,0 +1,6 @@ +*.b#* +*.l#* +*.s#* +*.pdf +*.zip +eagle.epf diff --git a/hw/README.md b/hw/README.md index e69de29..4960309 100644 --- a/hw/README.md +++ b/hw/README.md @@ -0,0 +1,7 @@ +# SummerCart64 Hardware + +Schematics and PCB design for SummerCart64 done in Autodesk Eagle software. + +## TODO + +- Expand documentation diff --git a/hw/SummerCart64.brd b/hw/SummerCart64.brd new file mode 100644 index 0000000..6a1940b --- /dev/null +++ b/hw/SummerCart64.brd @@ -0,0 +1,5643 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +SummerCart64 +N64 FlashCart/DevKit +SummerCart64 +N64 FlashCart/DevKit +HW version: 1.0a +Designed by Polprzewodnikowy + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + +Footprint for Nintendo 64 cartridge edge connector. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +26 +30 +35 +40 +45 +50 +1 +5 +10 +15 +20 +25 +BACK +FRONT + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + +<b>MICRON Flash Memory</b><p> +www.micron.com<br> +<author>Created by librarian@cadsoft.de</author><p> + + +<b>54-Pin Plastic TSOP</b> (400 mil)<p> +Source: http://download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +54-Pin Plastic TSOP (400 mil) +Source: http://download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf + + + + + + + +<b>Resistors in DIL Packages</b><p> +<author>Created by librarian@cadsoft.de</author> + + +<b>BOURNS</b> Chip Resistor Array<p> +Source: RS Component / BUORNS + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + +BOURNS Chip Resistor Array +Source: RS Component / BUORNS + + + + + + + +<b>Resistors, Capacitors, Inductors</b><p> +Based on the previous libraries: +<ul> +<li>r.lbr +<li>cap.lbr +<li>cap-fe.lbr +<li>captant.lbr +<li>polcap.lbr +<li>ipc-smd.lbr +</ul> +All SMD packages are defined according to the IPC specifications and CECC<p> +<author>Created by librarian@cadsoft.de</author><p> +<p> +for Electrolyt Capacitors see also :<p> +www.bccomponents.com <p> +www.panasonic.com<p> +www.kemet.com<p> +http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b> +<p> +for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p> + +<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0> +<tr valign="top"> + +<! <td width="10">&nbsp;</td> +<td width="90%"> + +<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b> +<P> +<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2> + <TR> + <TD COLSPAN=8> + <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI&nbsp;TECH</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT> + </B> + </TD><TD>&nbsp;</TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 > + 3005P<BR> + 3006P<BR> + 3006W<BR> + 3006Y<BR> + 3009P<BR> + 3009W<BR> + 3009Y<BR> + 3057J<BR> + 3057L<BR> + 3057P<BR> + 3057Y<BR> + 3059J<BR> + 3059L<BR> + 3059P<BR> + 3059Y<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 89P<BR> + 89W<BR> + 89X<BR> + 89PH<BR> + 76P<BR> + 89XH<BR> + 78SLT<BR> + 78L&nbsp;ALT<BR> + 56P&nbsp;ALT<BR> + 78P&nbsp;ALT<BR> + T8S<BR> + 78L<BR> + 56P<BR> + 78P<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + T18/784<BR> + 783<BR> + 781<BR> + -<BR> + -<BR> + -<BR> + 2199<BR> + 1697/1897<BR> + 1680/1880<BR> + 2187<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 8035EKP/CT20/RJ-20P<BR> + -<BR> + RJ-20X<BR> + -<BR> + -<BR> + -<BR> + 1211L<BR> + 8012EKQ&nbsp;ALT<BR> + 8012EKR&nbsp;ALT<BR> + 1211P<BR> + 8012EKJ<BR> + 8012EKL<BR> + 8012EKQ<BR> + 8012EKR<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 2101P<BR> + 2101W<BR> + 2101Y<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 2102L<BR> + 2102S<BR> + 2102Y<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + EVMCOG<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 43P<BR> + 43W<BR> + 43Y<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 40L<BR> + 40P<BR> + 40Y<BR> + 70Y-T602<BR> + 70L<BR> + 70P<BR> + 70Y<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + RT/RTR12<BR> + RT/RTR12<BR> + RT/RTR12<BR> + -<BR> + RJ/RJR12<BR> + RJ/RJR12<BR> + RJ/RJR12<BR></FONT> + </TD> + </TR> + <TR> + <TD COLSPAN=8>&nbsp; + </TD> + </TR> + <TR> + <TD COLSPAN=8> + <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3250L<BR> + 3250P<BR> + 3250W<BR> + 3250X<BR> + 3252P<BR> + 3252W<BR> + 3252X<BR> + 3260P<BR> + 3260W<BR> + 3260X<BR> + 3262P<BR> + 3262W<BR> + 3262X<BR> + 3266P<BR> + 3266W<BR> + 3266X<BR> + 3290H<BR> + 3290P<BR> + 3290W<BR> + 3292P<BR> + 3292W<BR> + 3292X<BR> + 3296P<BR> + 3296W<BR> + 3296X<BR> + 3296Y<BR> + 3296Z<BR> + 3299P<BR> + 3299W<BR> + 3299X<BR> + 3299Y<BR> + 3299Z<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 66P&nbsp;ALT<BR> + 66W&nbsp;ALT<BR> + 66X&nbsp;ALT<BR> + 66P&nbsp;ALT<BR> + 66W&nbsp;ALT<BR> + 66X&nbsp;ALT<BR> + -<BR> + 64W&nbsp;ALT<BR> + -<BR> + 64P&nbsp;ALT<BR> + 64W&nbsp;ALT<BR> + 64X&nbsp;ALT<BR> + 64P<BR> + 64W<BR> + 64X<BR> + 66X&nbsp;ALT<BR> + 66P&nbsp;ALT<BR> + 66W&nbsp;ALT<BR> + 66P<BR> + 66W<BR> + 66X<BR> + 67P<BR> + 67W<BR> + 67X<BR> + 67Y<BR> + 67Z<BR> + 68P<BR> + 68W<BR> + 68X<BR> + 67Y&nbsp;ALT<BR> + 67Z&nbsp;ALT<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 5050<BR> + 5091<BR> + 5080<BR> + 5087<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + T63YB<BR> + T63XB<BR> + -<BR> + -<BR> + -<BR> + 5887<BR> + 5891<BR> + 5880<BR> + -<BR> + -<BR> + -<BR> + T93Z<BR> + T93YA<BR> + T93XA<BR> + T93YB<BR> + T93XB<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 8026EKP<BR> + 8026EKW<BR> + 8026EKM<BR> + 8026EKP<BR> + 8026EKB<BR> + 8026EKM<BR> + 1309X<BR> + 1309P<BR> + 1309W<BR> + 8024EKP<BR> + 8024EKW<BR> + 8024EKN<BR> + RJ-9P/CT9P<BR> + RJ-9W<BR> + RJ-9X<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3103P<BR> + 3103Y<BR> + 3103Z<BR> + 3103P<BR> + 3103Y<BR> + 3103Z<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3105P/3106P<BR> + 3105W/3106W<BR> + 3105X/3106X<BR> + 3105Y/3106Y<BR> + 3105Z/3105Z<BR> + 3102P<BR> + 3102W<BR> + 3102X<BR> + 3102Y<BR> + 3102Z<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + EVMCBG<BR> + EVMCCG<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 55-1-X<BR> + 55-4-X<BR> + 55-3-X<BR> + 55-2-X<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 50-2-X<BR> + 50-4-X<BR> + 50-3-X<BR> + -<BR> + -<BR> + -<BR> + 64P<BR> + 64W<BR> + 64X<BR> + 64Y<BR> + 64Z<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + RT/RTR22<BR> + RT/RTR22<BR> + RT/RTR22<BR> + RT/RTR22<BR> + RJ/RJR22<BR> + RJ/RJR22<BR> + RJ/RJR22<BR> + RT/RTR26<BR> + RT/RTR26<BR> + RT/RTR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RT/RTR24<BR> + RT/RTR24<BR> + RT/RTR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> + <TR> + <TD COLSPAN=8>&nbsp; + </TD> + </TR> + <TR> + <TD COLSPAN=8> + <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3323P<BR> + 3323S<BR> + 3323W<BR> + 3329H<BR> + 3329P<BR> + 3329W<BR> + 3339H<BR> + 3339P<BR> + 3339W<BR> + 3352E<BR> + 3352H<BR> + 3352K<BR> + 3352P<BR> + 3352T<BR> + 3352V<BR> + 3352W<BR> + 3362H<BR> + 3362M<BR> + 3362P<BR> + 3362R<BR> + 3362S<BR> + 3362U<BR> + 3362W<BR> + 3362X<BR> + 3386B<BR> + 3386C<BR> + 3386F<BR> + 3386H<BR> + 3386K<BR> + 3386M<BR> + 3386P<BR> + 3386S<BR> + 3386W<BR> + 3386X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 25P<BR> + 25S<BR> + 25RX<BR> + 82P<BR> + 82M<BR> + 82PA<BR> + -<BR> + -<BR> + -<BR> + 91E<BR> + 91X<BR> + 91T<BR> + 91B<BR> + 91A<BR> + 91V<BR> + 91W<BR> + 25W<BR> + 25V<BR> + 25P<BR> + -<BR> + 25S<BR> + 25U<BR> + 25RX<BR> + 25X<BR> + 72XW<BR> + 72XL<BR> + 72PM<BR> + 72RX<BR> + -<BR> + 72PX<BR> + 72P<BR> + 72RXW<BR> + 72RXL<BR> + 72X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + T7YB<BR> + T7YA<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + TXD<BR> + TYA<BR> + TYP<BR> + -<BR> + TYD<BR> + TX<BR> + -<BR> + 150SX<BR> + 100SX<BR> + 102T<BR> + 101S<BR> + 190T<BR> + 150TX<BR> + 101<BR> + -<BR> + -<BR> + 101SX<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + ET6P<BR> + ET6S<BR> + ET6X<BR> + RJ-6W/8014EMW<BR> + RJ-6P/8014EMP<BR> + RJ-6X/8014EMX<BR> + TM7W<BR> + TM7P<BR> + TM7X<BR> + -<BR> + 8017SMS<BR> + -<BR> + 8017SMB<BR> + 8017SMA<BR> + -<BR> + -<BR> + CT-6W<BR> + CT-6H<BR> + CT-6P<BR> + CT-6R<BR> + -<BR> + CT-6V<BR> + CT-6X<BR> + -<BR> + -<BR> + 8038EKV<BR> + -<BR> + 8038EKX<BR> + -<BR> + -<BR> + 8038EKP<BR> + 8038EKZ<BR> + 8038EKW<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + 3321H<BR> + 3321P<BR> + 3321N<BR> + 1102H<BR> + 1102P<BR> + 1102T<BR> + RVA0911V304A<BR> + -<BR> + RVA0911H413A<BR> + RVG0707V100A<BR> + RVA0607V(H)306A<BR> + RVA1214H213A<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3104B<BR> + 3104C<BR> + 3104F<BR> + 3104H<BR> + -<BR> + 3104M<BR> + 3104P<BR> + 3104S<BR> + 3104W<BR> + 3104X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + EVMQ0G<BR> + EVMQIG<BR> + EVMQ3G<BR> + EVMS0G<BR> + EVMQ0G<BR> + EVMG0G<BR> + -<BR> + -<BR> + -<BR> + EVMK4GA00B<BR> + EVM30GA00B<BR> + EVMK0GA00B<BR> + EVM38GA00B<BR> + EVMB6<BR> + EVLQ0<BR> + -<BR> + EVMMSG<BR> + EVMMBG<BR> + EVMMAG<BR> + -<BR> + -<BR> + EVMMCS<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + EVMM1<BR> + -<BR> + -<BR> + EVMM0<BR> + -<BR> + -<BR> + EVMM3<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + 62-3-1<BR> + 62-1-2<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 67R<BR> + -<BR> + 67P<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 67X<BR> + 63V<BR> + 63S<BR> + 63M<BR> + -<BR> + -<BR> + 63H<BR> + 63P<BR> + -<BR> + -<BR> + 63X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + RJ/RJR50<BR> + RJ/RJR50<BR> + RJ/RJR50<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> +</TABLE> +<P>&nbsp;<P> +<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3> + <TR> + <TD COLSPAN=7> + <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT> + <P> + <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3224G<BR> + 3224J<BR> + 3224W<BR> + 3269P<BR> + 3269W<BR> + 3269X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 44G<BR> + 44J<BR> + 44W<BR> + 84P<BR> + 84W<BR> + 84X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + ST63Z<BR> + ST63Y<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + ST5P<BR> + ST5W<BR> + ST5X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> + <TR> + <TD COLSPAN=7>&nbsp; + </TD> + </TR> + <TR> + <TD COLSPAN=7> + <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT> + </TD> + </TR> + <TR> + <TD> + <FONT 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Meg x 16 x 4 banks<p> +Source: http://download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>Resistors in DIL Packages</b><p> +<author>Created by librarian@cadsoft.de</author> + + +<b>Chip Resistor Array</b> size 4 × 0603<p> +concave termination - Phycomp Components<br> +Source: RS Components + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>Chip Resistor Array</b> size 4 × 0603<p> +convex termination - Phycomp Components<br> +Source: RS Components + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + +<b>BOURNS</b> Chip Resistor Array<p> +Source: RS Component / BUORNS + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>BOURNS</b> Chip Resistor Array<p> +Source: RS Component / BUORNS + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>ARRAY CHIP RESISTOR</b> Size 4 x 0402<p> +Source: www.yageo.com .. Pu-YC124_51_PbFree_L_1.pdf + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + +<b>Array chip resistor</b> size 4 × 0402<p> +Source: http://docs-europe.electrocomponents.com/webdocs/0114/0900766b80114d99.pdf + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + +<b>Chip Resistor Array 0201x4</b> 4 resistors in 1.4 mm x 0.6 mm size<p> +Source: PANASONIC .. aoc0000ce1.pdf + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p> +Source: PANASONIC .. aoc0000ce1.pdf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.2 mm x 1.6 mm size (EXB38V, V8V)<p> +Source: PANASONIC .. aoc0000ce1.pdf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p> +Source: PANASONIC .. aoc0000ce1.pdf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>Chip Resistor Array 0805x4</b> 4 resistors in 5.08 mm x 2.20 mm size<p> +Source: PANASONIC .. aoc0000ce1.pdf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p> +Source: PANASONIC .. aoc0000ce1.pdf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + +Chip Resistor Array size 4 × 0603 +concave termination - Phycomp Components +Source: RS Components + + + + + +Chip Resistor Array size 4 × 0603 +convex termination - Phycomp Components +Source: RS Components + + + + + +BOURNS Chip Resistor Array +Source: RS Component / BUORNS + + + + + +BOURNS Chip Resistor Array +Source: RS Component / BUORNS + + + + + +ARRAY CHIP RESISTOR Size 4 x 0402 +Source: www.yageo.com .. Pu-YC124_51_PbFree_L_1.pdf + + + + + +Array chip resistor size 4 × 0402 +Source: http://docs-europe.electrocomponents.com/webdocs/0114/0900766b80114d99.pdf + + + + + +Chip Resistor Array 0201x4 4 resistors in 1.4 mm x 0.6 mm size +Source: PANASONIC .. aoc0000ce1.pdf + + + + + +Chip Resistor Array 0402x4 4 resistors in 2.0 mm x 1.0 mm size +Source: PANASONIC .. aoc0000ce1.pdf + + + + + +Chip Resistor Array 0603x4 4 resistors in 3.2 mm x 1.6 mm size (EXB38V, V8V) +Source: PANASONIC .. aoc0000ce1.pdf + + + + + +Chip Resistor Array 0402x4 4 resistors in 2.0 mm x 1.0 mm size +Source: PANASONIC .. aoc0000ce1.pdf + + + + + +Chip Resistor Array 0805x4 4 resistors in 5.08 mm x 2.20 mm size +Source: PANASONIC .. aoc0000ce1.pdf + + + + + +Chip Resistor Array 0603x4 4 resistors in 3.20 mm x 1.60 mm size +Source: PANASONIC .. aoc0000ce1.pdf + + + + + + + + + + + +>VALUE +>NAME + + + + + + +<b>Array Chip Resistor</b><p> +Source: RS Component / Phycomp + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>Resistors, Capacitors, Inductors</b><p> +Based on the previous libraries: +<ul> +<li>r.lbr +<li>cap.lbr +<li>cap-fe.lbr +<li>captant.lbr +<li>polcap.lbr +<li>ipc-smd.lbr +</ul> +All SMD packages are defined according to the IPC specifications and CECC<p> +<author>Created by librarian@cadsoft.de</author><p> +<p> +for Electrolyt Capacitors see also :<p> +www.bccomponents.com <p> +www.panasonic.com<p> +www.kemet.com<p> +http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b> +<p> +for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p> + +<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0> +<tr valign="top"> + +<! <td width="10">&nbsp;</td> +<td width="90%"> + +<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b> +<P> +<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2> + <TR> + <TD COLSPAN=8> + <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI&nbsp;TECH</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 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70Y-T602<BR> + 70L<BR> + 70P<BR> + 70Y<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + RT/RTR12<BR> + RT/RTR12<BR> + RT/RTR12<BR> + -<BR> + RJ/RJR12<BR> + RJ/RJR12<BR> + RJ/RJR12<BR></FONT> + </TD> + </TR> + <TR> + <TD COLSPAN=8>&nbsp; + </TD> + </TR> + <TR> + <TD COLSPAN=8> + <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT> + 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+ 68P<BR> + 68W<BR> + 68X<BR> + 67Y&nbsp;ALT<BR> + 67Z&nbsp;ALT<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 5050<BR> + 5091<BR> + 5080<BR> + 5087<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + T63YB<BR> + T63XB<BR> + -<BR> + -<BR> + -<BR> + 5887<BR> + 5891<BR> + 5880<BR> + -<BR> + -<BR> + -<BR> + T93Z<BR> + T93YA<BR> + T93XA<BR> + T93YB<BR> + T93XB<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 8026EKP<BR> + 8026EKW<BR> + 8026EKM<BR> + 8026EKP<BR> + 8026EKB<BR> + 8026EKM<BR> + 1309X<BR> + 1309P<BR> + 1309W<BR> + 8024EKP<BR> + 8024EKW<BR> + 8024EKN<BR> + RJ-9P/CT9P<BR> + RJ-9W<BR> + RJ-9X<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3103P<BR> + 3103Y<BR> + 3103Z<BR> + 3103P<BR> + 3103Y<BR> + 3103Z<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3105P/3106P<BR> + 3105W/3106W<BR> + 3105X/3106X<BR> + 3105Y/3106Y<BR> + 3105Z/3105Z<BR> + 3102P<BR> + 3102W<BR> + 3102X<BR> + 3102Y<BR> + 3102Z<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + EVMCBG<BR> + EVMCCG<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 55-1-X<BR> + 55-4-X<BR> + 55-3-X<BR> + 55-2-X<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 50-2-X<BR> + 50-4-X<BR> + 50-3-X<BR> + -<BR> + -<BR> + -<BR> + 64P<BR> + 64W<BR> + 64X<BR> + 64Y<BR> + 64Z<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + RT/RTR22<BR> + RT/RTR22<BR> + RT/RTR22<BR> + RT/RTR22<BR> + RJ/RJR22<BR> + RJ/RJR22<BR> + RJ/RJR22<BR> + RT/RTR26<BR> + RT/RTR26<BR> + RT/RTR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RT/RTR24<BR> + RT/RTR24<BR> + RT/RTR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> + <TR> + <TD COLSPAN=8>&nbsp; + </TD> + </TR> + <TR> + <TD COLSPAN=8> + <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3323P<BR> + 3323S<BR> + 3323W<BR> + 3329H<BR> + 3329P<BR> + 3329W<BR> + 3339H<BR> + 3339P<BR> + 3339W<BR> + 3352E<BR> + 3352H<BR> + 3352K<BR> + 3352P<BR> + 3352T<BR> + 3352V<BR> + 3352W<BR> + 3362H<BR> + 3362M<BR> + 3362P<BR> + 3362R<BR> + 3362S<BR> + 3362U<BR> + 3362W<BR> + 3362X<BR> + 3386B<BR> + 3386C<BR> + 3386F<BR> + 3386H<BR> + 3386K<BR> + 3386M<BR> + 3386P<BR> + 3386S<BR> + 3386W<BR> + 3386X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 25P<BR> + 25S<BR> + 25RX<BR> + 82P<BR> + 82M<BR> + 82PA<BR> + -<BR> + -<BR> + -<BR> + 91E<BR> + 91X<BR> + 91T<BR> + 91B<BR> + 91A<BR> + 91V<BR> + 91W<BR> + 25W<BR> + 25V<BR> + 25P<BR> + -<BR> + 25S<BR> + 25U<BR> + 25RX<BR> + 25X<BR> + 72XW<BR> + 72XL<BR> + 72PM<BR> + 72RX<BR> + -<BR> + 72PX<BR> + 72P<BR> + 72RXW<BR> + 72RXL<BR> + 72X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + T7YB<BR> + T7YA<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + TXD<BR> + TYA<BR> + TYP<BR> + -<BR> + TYD<BR> + TX<BR> + -<BR> + 150SX<BR> + 100SX<BR> + 102T<BR> + 101S<BR> + 190T<BR> + 150TX<BR> + 101<BR> + -<BR> + -<BR> + 101SX<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + ET6P<BR> + ET6S<BR> + ET6X<BR> + RJ-6W/8014EMW<BR> + RJ-6P/8014EMP<BR> + RJ-6X/8014EMX<BR> + TM7W<BR> + TM7P<BR> + TM7X<BR> + -<BR> + 8017SMS<BR> + -<BR> + 8017SMB<BR> + 8017SMA<BR> + -<BR> + -<BR> + CT-6W<BR> + CT-6H<BR> + CT-6P<BR> + CT-6R<BR> + -<BR> + CT-6V<BR> + CT-6X<BR> + -<BR> + -<BR> + 8038EKV<BR> + -<BR> + 8038EKX<BR> + -<BR> + -<BR> + 8038EKP<BR> + 8038EKZ<BR> + 8038EKW<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + 3321H<BR> + 3321P<BR> + 3321N<BR> + 1102H<BR> + 1102P<BR> + 1102T<BR> + RVA0911V304A<BR> + -<BR> + RVA0911H413A<BR> + RVG0707V100A<BR> + RVA0607V(H)306A<BR> + RVA1214H213A<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3104B<BR> + 3104C<BR> + 3104F<BR> + 3104H<BR> + -<BR> + 3104M<BR> + 3104P<BR> + 3104S<BR> + 3104W<BR> + 3104X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + EVMQ0G<BR> + EVMQIG<BR> + EVMQ3G<BR> + EVMS0G<BR> + EVMQ0G<BR> + EVMG0G<BR> + -<BR> + -<BR> + -<BR> + EVMK4GA00B<BR> + EVM30GA00B<BR> + EVMK0GA00B<BR> + EVM38GA00B<BR> + EVMB6<BR> + EVLQ0<BR> + -<BR> + EVMMSG<BR> + EVMMBG<BR> + EVMMAG<BR> + -<BR> + -<BR> + EVMMCS<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + EVMM1<BR> + -<BR> + -<BR> + EVMM0<BR> + -<BR> + -<BR> + EVMM3<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + 62-3-1<BR> + 62-1-2<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 67R<BR> + -<BR> + 67P<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 67X<BR> + 63V<BR> + 63S<BR> + 63M<BR> + -<BR> + -<BR> + 63H<BR> + 63P<BR> + -<BR> + -<BR> + 63X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + RJ/RJR50<BR> + RJ/RJR50<BR> + RJ/RJR50<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> +</TABLE> +<P>&nbsp;<P> +<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3> + <TR> + <TD COLSPAN=7> + <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT> + <P> + <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3224G<BR> + 3224J<BR> + 3224W<BR> + 3269P<BR> + 3269W<BR> + 3269X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 44G<BR> + 44J<BR> + 44W<BR> + 84P<BR> + 84W<BR> + 84X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + ST63Z<BR> + ST63Y<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + ST5P<BR> + ST5W<BR> + ST5X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> + <TR> + <TD COLSPAN=7>&nbsp; + </TD> + </TR> + <TR> + <TD COLSPAN=7> + <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT> + </TD> + </TR> + <TR> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3314G<BR> + 3314J<BR> + 3364A/B<BR> + 3364C/D<BR> + 3364W/X<BR> + 3313G<BR> + 3313J<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 23B<BR> + 23A<BR> + 21X<BR> + 21W<BR> + -<BR> + 22B<BR> + 22A<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + ST5YL/ST53YL<BR> + ST5YJ/5T53YJ<BR> + ST-23A<BR> + ST-22B<BR> + ST-22<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + ST-4B<BR> + ST-4A<BR> + -<BR> + -<BR> + -<BR> + ST-3B<BR> + ST-3A<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + EVM-6YS<BR> + EVM-1E<BR> + EVM-1G<BR> + EVM-1D<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + G4B<BR> + G4A<BR> + TR04-3S1<BR> + TRG04-2S1<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + DVR-43A<BR> + CVR-42C<BR> + CVR-42A/C<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> +</TABLE> +<P> +<FONT SIZE=4 FACE=ARIAL><B>ALT =&nbsp;ALTERNATE</B></FONT> +<P> + +&nbsp; +<P> +</td> +</tr> +</table> + + +<b>Chip RESISTOR 0402 EIA (1005 Metric)</b> + + + + + + + + +>NAME +>VALUE + + + + + +<b>RESISTOR</b> + + + + + + + + +>NAME +>VALUE + + + + + +<b>RESISTOR</b><p> + + + + + + + + +>NAME +>VALUE + + + + + +<b>RESISTOR</b> wave soldering<p> + + + + + + + + +>NAME +>VALUE + + + + + +<b>RESISTOR</b> + + + + + + + + +>NAME +>VALUE + + + + + +<b>RESISTOR</b><p> +wave soldering + + + + + + + + +>NAME +>VALUE + + + + + +<b>RESISTOR</b> + + + + + + + + +>NAME +>VALUE + + + + + +<b>RESISTOR</b><p> +wave soldering + + + + + + + + +>NAME +>VALUE + + + + + +<b>RESISTOR</b> + + + + + + + + +>NAME +>VALUE + + + + +<b>RESISTOR</b><p> +wave soldering + + + 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CH291-1220LF<br> +Source: <a href="http://www.farnell.com/datasheets/1505860.pdf"> Data sheet </a> + + + + + + + + + + + + + + + + + + + + + + + +<b>Diodes</b><p> +Based on the following sources: +<ul> +<li>Motorola : www.onsemi.com +<li>Fairchild : www.fairchildsemi.com +<li>Philips : www.semiconductors.com +<li>Vishay : www.vishay.de +</ul> +<author>Created by librarian@cadsoft.de</author> + + +<b>SOD-323</b><p> +Source: www.st.com, BAT60J.pdf + + + + + + +>NAME +>VALUE + + + + + + + + +SOD-323 +Source: www.st.com, BAT60J.pdf + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + +<b>Schottky barrier diode</b><p> +Source: www.st.com, BAT60J.pdf + + + + + + + + + + + + + + + + + + + + + + + +<b>Samtec Connectors</b><p> +<author>Created by librarian@cadsoft.de</author> + + +<b>THROUGH-HOLE .025" SQ POST SOCKET</b><p> +Source: Samtec SSW.pdf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +1 +2 +>NAME +>VALUE + + +<b>THROUGH-HOLE .025" SQ POST SOCKET</b><p> +Source: Samtec SSW.pdf + + + + + + + + + + + + + + + + +1 +2 +>NAME +>VALUE + + + + + + + + +<b>THROUGH-HOLE .025" SQ POST SOCKET</b><p> +Source: Samtec SSW.pdf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +1 +2 +>NAME +>VALUE + + +<b>THROUGH-HOLE .025" SQ POST SOCKET</b><p> +Source: Samtec SSW.pdf + + + + + + + + + + + + + + + + +1 +2 +>NAME +>VALUE + + + + + + + + + + + + + +>VALUE +>NAME + + + + + + +>NAME + + + + + +<b>THROUGH-HOLE .025" SQ POST SOCKET</b><p> +Source: Samtec SSW.pdf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>LEDs</b><p> +<author>Created by librarian@cadsoft.de</author><br> +Extended by Federico Battaglin <author>&lt;federico.rd@fdpinternational.com&gt;</author> with DUOLED + + +<b>CHICAGO MINIATURE LAMP, INC.</b><p> +7022X Series SMT LEDs 1206 Package Size + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + +<B>LED</B><p> +5 mm, square, Siemens + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + +<B>LED</B><p> +2 x 5 mm, rectangle + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + +<B>LED</B><p> +3 mm, round + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<B>LED</B><p> +5 mm, round + + + + + + + + + + + +>NAME +>VALUE + + +<B>LED</B><p> +1 mm, round, Siemens + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + +<B>LED BLOCK</B><p> +1 LED, Siemens + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + +<b>LED HOLDER</b><p> +Siemens + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>LED HOLDER</b><p> +Siemens + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>LED HOLDER</b><p> +Siemens + + + + + + + + + + + + + + + + + +A+ +K- +>NAME +>VALUE + + + + + +<b>LED HOLDER</b><p> +Siemens + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE ++ +- + + +<B>IR LED</B><p> +infrared emitting diode, Infineon +TO-18, lead spacing 2.54 mm, cathode marking<p> +Inifineon + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<B>IR LED</B><p> +infrared emitting diode, Infineon +TO-18, lead spacing 2.54 mm, cathode marking<p> +Inifineon + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<B>LED</B><p> +rectangle, 5.7 x 3.2 mm + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<B>IR LED</B><p> +IR transmitter Siemens + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>TOPLED® High-optical Power LED (HOP)</b><p> +Source: http://www.osram.convergy.de/ ... ls_t675.pdf + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +A +C + + + + + + + +<b>BLUE LINETM Hyper Mini TOPLED® Hyper-Bright LED</b><p> +Source: http://www.osram.convergy.de/ ... LB M676.pdf + + + + + + + + + + + + + + +A +C +>NAME +>VALUE + + + + + + + +<b>Super SIDELED® High-Current LED</b><p> +LG A672, LP A672 <br> +Source: http://www.osram.convergy.de/ ... LG_LP_A672.pdf (2004.05.13) + + + + + + + + + + + + + + + + + + + +C +A +>NAME +>VALUE + + + + + + + +<b>SmartLEDTM Hyper-Bright LED</b><p> +Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY L896.pdf + + + + + + + + +>NAME +>VALUE + + + + + +<b>Hyper TOPLED® RG Hyper-Bright LED</b><p> +Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY T776.pdf + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +A +C + + + + + + + + + + +<b>Hyper Micro SIDELED®</b><p> +Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY Y876.pdf + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + +<b>Power TOPLED®</b><p> +Source: http://www.osram.convergy.de/ ... LA_LO_LA_LY E67B.pdf + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +C +A +C +C + + + + + + + + + + + +<b>Hyper CHIPLED Hyper-Bright LED</b><p> +LB Q993<br> +Source: http://www.osram.convergy.de/ ... Lb_q993.pdf + + + + +>NAME +>VALUE + + + + + + + +<b>Hyper CHIPLED Hyper-Bright LED</b><p> +LB R99A<br> +Source: http://www.osram.convergy.de/ ... lb_r99a.pdf + + + + +>NAME +>VALUE + + + + + + + +<b>Mini TOPLED Santana®</b><p> +Source: http://www.osram.convergy.de/ ... LG M470.pdf + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + +<b>CHIPLED</b><p> +Source: http://www.osram.convergy.de/ ... LG_R971.pdf + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + +<b>CHIPLED</b><p> +Source: http://www.osram.convergy.de/ ... LG_LY N971.pdf + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + +<b>CHIPLED</b><p> +Source: http://www.osram.convergy.de/ ... LG_LY Q971.pdf + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + +<b>CHIPLED-0603</b><p> +Recommended Solder Pad useable for SmartLEDTM and Chipled - Package 0603<br> +Package able to withstand TTW-soldering heat<br> +Package suitable for TTW-soldering<br> +Source: http://www.osram.convergy.de/ ... LO_LS_LY L89K.pdf + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + +<b>SmartLED TTW</b><p> +Recommended Solder Pad useable for SmartLEDTM and Chipled - Package 0603<br> +Package able to withstand TTW-soldering heat<br> +Package suitable for TTW-soldering<br> +Source: http://www.osram.convergy.de/ ... LO_LS_LY L89K.pdf + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + +<b>Lumileds Lighting. LUXEON®</b> with cool pad<p> +Source: K2.pdf + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>Lumileds Lighting. LUXEON®</b> without cool pad<p> +Source: K2.pdf + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + +<B>LED</B><p> +10 mm, round + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>SURFACE MOUNT LED LAMP</b> 3.5x2.8mm<p> +Source: http://www.kingbright.com/manager/upload/pdf/KA-3528ASYC(Ver1189474662.1) + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + +<b>SML0805-2CW-TR (0805 PROFILE)</b> COOL WHITE<p> +Source: http://www.ledtronics.com/ds/smd-0603/Dstr0093.pdf + + + + + + + + + + + +>NAME +>VALUE + + +<b>SML10XXKH-TR (HIGH INTENSITY) LED</b><p> +<table> +<tr><td>SML10R3KH-TR</td><td>ULTRA RED</td></tr> +<tr><td>SML10E3KH-TR</td><td>SUPER REDSUPER BLUE</td></tr> +<tr><td>SML10O3KH-TR</td><td>SUPER ORANGE</td></tr> +<tr><td>SML10PY3KH-TR</td><td>PURE YELLOW</td></tr> +<tr><td>SML10OY3KH-TR</td><td>ULTRA YELLOW</td></tr> +<tr><td>SML10AG3KH-TR</td><td>AQUA GREEN</td></tr> +<tr><td>SML10BG3KH-TR</td><td>BLUE GREEN</td></tr> +<tr><td>SML10PB1KH-TR</td><td>SUPER BLUE</td></tr> +<tr><td>SML10CW1KH-TR</td><td>WHITE</td></tr> +</table> + +Source: http://www.ledtronics.com/ds/smd-1206/dstr0094.PDF + + + + + + + +>NAME +>VALUE + + + + + + + + + +<b>SML0603-XXX (HIGH INTENSITY) LED</b><p> +<table> +<tr><td>AG3K</td><td>AQUA GREEN</td></tr> +<tr><td>B1K</td><td>SUPER BLUE</td></tr> +<tr><td>R1K</td><td>SUPER RED</td></tr> +<tr><td>R3K</td><td>ULTRA RED</td></tr> +<tr><td>O3K</td><td>SUPER ORANGE</td></tr> +<tr><td>O3KH</td><td>SOFT ORANGE</td></tr> +<tr><td>Y3KH</td><td>SUPER YELLOW</td></tr> +<tr><td>Y3K</td><td>SUPER YELLOW</td></tr> +<tr><td>2CW</td><td>WHITE</td></tr> +</table> +Source: http://www.ledtronics.com/ds/smd-0603/Dstr0092.pdf + + + + + + + + + + +>NAME +>VALUE + + + + + + +CHICAGO MINIATURE LAMP, INC. +7022X Series SMT LEDs 1206 Package Size + + + + + +LED +5 mm, square, Siemens + + + + + +LED +2 x 5 mm, rectangle + + + + + +LED +3 mm, round + + + + + +LED +5 mm, round + + + + + +LED +1 mm, round, Siemens + + + + + +LED BLOCK +1 LED, Siemens + + + + + +LED HOLDER +Siemens + + + + + +LED HOLDER +Siemens + + + + + +LED HOLDER +Siemens + + + + + +LED HOLDER +Siemens + + + + + +IR LED +infrared emitting diode, Infineon +TO-18, lead spacing 2.54 mm, cathode marking +Inifineon + + + + + +IR LED +infrared emitting diode, Infineon +TO-18, lead spacing 2.54 mm, cathode marking +Inifineon + + + + + +LED +rectangle, 5.7 x 3.2 mm + + + + + +IR LED +IR transmitter Siemens + + + + + +TOPLED® High-optical Power LED (HOP) +Source: http://www.osram.convergy.de/ ... ls_t675.pdf + + + + + +BLUE LINETM Hyper Mini TOPLED® Hyper-Bright LED +Source: http://www.osram.convergy.de/ ... LB M676.pdf + + + + + +Super SIDELED® High-Current LED +LG A672, LP A672 +Source: http://www.osram.convergy.de/ ... LG_LP_A672.pdf (2004.05.13) + + + + + +SmartLEDTM Hyper-Bright LED +Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY L896.pdf + + + + + +Hyper TOPLED® RG Hyper-Bright LED +Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY T776.pdf + + + + + +Hyper Micro SIDELED® +Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY Y876.pdf + + + + + +Power TOPLED® +Source: http://www.osram.convergy.de/ ... LA_LO_LA_LY E67B.pdf + + + + + +Hyper CHIPLED Hyper-Bright LED +LB Q993 +Source: http://www.osram.convergy.de/ ... Lb_q993.pdf + + + + + +Hyper CHIPLED Hyper-Bright LED +LB R99A +Source: http://www.osram.convergy.de/ ... lb_r99a.pdf + + + + + +Mini TOPLED Santana® +Source: http://www.osram.convergy.de/ ... LG M470.pdf + + + + + +CHIPLED +Source: http://www.osram.convergy.de/ ... LG_R971.pdf + + + + + +CHIPLED +Source: http://www.osram.convergy.de/ ... LG_LY N971.pdf + + + + + +CHIPLED +Source: http://www.osram.convergy.de/ ... LG_LY Q971.pdf + + + + + +CHIPLED-0603 +Recommended Solder Pad useable for SmartLEDTM and Chipled - Package 0603 +Package able to withstand TTW-soldering heat +Package suitable for TTW-soldering +Source: http://www.osram.convergy.de/ ... LO_LS_LY L89K.pdf + + + + + +SmartLED TTW +Recommended Solder Pad useable for SmartLEDTM and Chipled - Package 0603 +Package able to withstand TTW-soldering heat +Package suitable for TTW-soldering +Source: http://www.osram.convergy.de/ ... LO_LS_LY L89K.pdf + + + + + +Lumileds Lighting. LUXEON® with cool pad +Source: K2.pdf + + + + + +Lumileds Lighting. LUXEON® without cool pad +Source: K2.pdf + + + + + +LED +10 mm, round + + + + + +SURFACE MOUNT LED LAMP 3.5x2.8mm +Source: http://www.kingbright.com/manager/upload/pdf/KA-3528ASYC(Ver1189474662.1) + + + + + +SML0805-2CW-TR (0805 PROFILE) COOL WHITE +Source: http://www.ledtronics.com/ds/smd-0603/Dstr0093.pdf + + + + + +SML10XXKH-TR (HIGH INTENSITY) LED + +SML10R3KH-TRULTRA RED +SML10E3KH-TRSUPER REDSUPER BLUE +SML10O3KH-TRSUPER ORANGE +SML10PY3KH-TRPURE YELLOW +SML10OY3KH-TRULTRA YELLOW +SML10AG3KH-TRAQUA GREEN +SML10BG3KH-TRBLUE GREEN +SML10PB1KH-TRSUPER BLUE +SML10CW1KH-TRWHITE + + +Source: http://www.ledtronics.com/ds/smd-1206/dstr0094.PDF + + + + + +SML0603-XXX (HIGH INTENSITY) LED + +AG3KAQUA GREEN +B1KSUPER BLUE +R1KSUPER RED +R3KULTRA RED +O3KSUPER ORANGE +O3KHSOFT ORANGE +Y3KHSUPER YELLOW +Y3KSUPER YELLOW +2CWWHITE + +Source: http://www.ledtronics.com/ds/smd-0603/Dstr0092.pdf + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + +<b>LED</b><p> +<u>OSRAM</u>:<br> + +- <u>CHIPLED</u><br> +LG R971, LG N971, LY N971, LG Q971, LY Q971, LO R971, LY R971 +LH N974, LH R974<br> +LS Q976, LO Q976, LY Q976<br> +LO Q996<br> + +- <u>Hyper CHIPLED</u><br> +LW Q18S<br> +LB Q993, LB Q99A, LB R99A<br> + +- <u>SideLED</u><br> +LS A670, LO A670, LY A670, LG A670, LP A670<br> +LB A673, LV A673, LT A673, LW A673<br> +LH A674<br> +LY A675<br> +LS A676, LA A676, LO A676, LY A676, LW A676<br> +LS A679, LY A679, LG A679<br> + +- <u>Hyper Micro SIDELED®</u><br> +LS Y876, LA Y876, LO Y876, LY Y876<br> +LT Y87S<br> + +- <u>SmartLED</u><br> +LW L88C, LW L88S<br> +LB L89C, LB L89S, LG L890<br> +LS L89K, LO L89K, LY L89K<br> +LS L896, LA L896, LO L896, LY L896<br> + +- <u>TOPLED</u><br> +LS T670, LO T670, LY T670, LG T670, LP T670<br> +LSG T670, LSP T670, LSY T670, LOP T670, LYG T670<br> +LG T671, LOG T671, LSG T671<br> +LB T673, LV T673, LT T673, LW T673<br> +LH T674<br> +LS T676, LA T676, LO T676, LY T676, LB T676, LH T676, LSB T676, LW T676<br> +LB T67C, LV T67C, LT T67C, LS T67K, LO T67K, LY T67K, LW E67C<br> +LS E67B, LA E67B, LO E67B, LY E67B, LB E67C, LV E67C, LT E67C<br> +LW T67C<br> +LS T679, LY T679, LG T679<br> +LS T770, LO T770, LY T770, LG T770, LP T770<br> +LB T773, LV T773, LT T773, LW T773<br> +LH T774<br> +LS E675, LA E675, LY E675, LS T675<br> +LS T776, LA T776, LO T776, LY T776, LB T776<br> +LHGB T686<br> +LT T68C, LB T68C<br> + +- <u>Hyper Mini TOPLED®</u><br> +LB M676<br> + +- <u>Mini TOPLED Santana®</u><br> +LG M470<br> +LS M47K, LO M47K, LY M47K +<p> +Source: http://www.osram.convergy.de<p> + +<u>LUXEON:</u><br> +- <u>LUMILED®</u><br> +LXK2-PW12-R00, LXK2-PW12-S00, LXK2-PW14-U00, LXK2-PW14-V00<br> +LXK2-PM12-R00, LXK2-PM12-S00, LXK2-PM14-U00<br> +LXK2-PE12-Q00, LXK2-PE12-R00, LXK2-PE12-S00, LXK2-PE14-T00, LXK2-PE14-U00<br> +LXK2-PB12-K00, LXK2-PB12-L00, LXK2-PB12-M00, LXK2-PB14-N00, LXK2-PB14-P00, LXK2-PB14-Q00<br> +LXK2-PR12-L00, LXK2-PR12-M00, LXK2-PR14-Q00, LXK2-PR14-R00<br> +LXK2-PD12-Q00, LXK2-PD12-R00, LXK2-PD12-S00<br> +LXK2-PH12-R00, LXK2-PH12-S00<br> +LXK2-PL12-P00, LXK2-PL12-Q00, LXK2-PL12-R00 +<p> +Source: www.luxeon.com<p> + +<u>KINGBRIGHT:</U><p> +KA-3528ASYC<br> +Source: www.kingbright.com + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>Voltage Regulators</b><p> +<author>Created by librarian@cadsoft.de</author> + + +<b>DPAK</b><p> +PLASTIC PACKAGE CASE 369C-01<br> +Source: http://www.onsemi.co.jp .. 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LM137M-D.PDF + + + + + +D2PACK +INTERNATIONAL RECTIFIER, irg4bc15ud-s.pdf + + + + + + + + + + + +>NAME +>VALUE +ADJ +IN +OUT + + + + + + + +<b>Low drop fixed and adjustable positive voltage regulators</b> 1 A<p> +Source: http://www.st.com/stonline/products/literature/ds/7194/ld1117axx.pdf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + +Since Version 8.2, EAGLE supports online libraries. The ids +of those online libraries will not be understood (or retained) +with this version. + + +Since Version 8.3, EAGLE supports URNs for individual library +assets (packages, symbols, and devices). The URNs of those assets +will not be understood (or retained) with this version. + + +Since Version 8.3, EAGLE supports the association of 3D packages +with devices in libraries, schematics, and board files. Those 3D +packages will not be understood (or retained) with this version. + + +Since Version 8.4, EAGLE supports properties for SPICE simulation. +Probes in schematics and SPICE mapping objects found in parts and library devices +will not be understood with this version. Update EAGLE to the latest version +for full support of SPICE simulation. + + + diff --git a/sw/README.md b/sw/README.md deleted file mode 100644 index e69de29..0000000 diff --git a/sw/SummerBanger/README.md b/sw/SummerBanger/README.md deleted file mode 100644 index e69de29..0000000 diff --git a/sw/SummerBanger64/.gitignore b/sw/SummerBanger64/.gitignore new file mode 100644 index 0000000..3af5c0b --- /dev/null +++ b/sw/SummerBanger64/.gitignore @@ -0,0 +1,3 @@ +/__pycache__ +/roms +*.z64 diff --git a/sw/SummerBanger64/README.md b/sw/SummerBanger64/README.md new file mode 100644 index 0000000..4c20443 --- /dev/null +++ b/sw/SummerBanger64/README.md @@ -0,0 +1,7 @@ +# SummerBanger64 + +A PC communication program for SummerCart64. + +## TODO + +- Expand documentation diff --git a/sw/SummerBanger64/SummerBanger64.py b/sw/SummerBanger64/SummerBanger64.py new file mode 100644 index 0000000..08ec77d --- /dev/null +++ b/sw/SummerBanger64/SummerBanger64.py @@ -0,0 +1,391 @@ +#!/usr/bin/env python3 + +import argparse +import progressbar +import struct +import sys +import time +from pyftdi.spi import SpiController + + + +class SummerBanger64: + + # Command ids + + __CMD_STATUS = 0x00 + __CMD_CONFIG = 0x10 + __CMD_ADDR = 0x20 + __CMD_READ_LENGTH = 0x30 + __CMD_WRITE = 0x40 + __CMD_READ = 0x50 + __CMD_CART_RESET = 0xFC + __CMD_FLUSH_WRITE = 0xFD + __CMD_FLUSH_READ = 0xFE + __CMD_SPI_RESET = 0xFF + + # Size declarations + + __FIFO_SIZE = 1024 + __FIFO_SIZE_BYTES = __FIFO_SIZE * 4 + __FLASH_PAGE_SIZE = 256 + + # Cart addresses + + __SDRAM_ADDRESS = 0x10000000 + __FLASH_ADDRESS = 0x18000000 + __FLASH_CFG_ADDRESS = 0x1C000000 + __CART_CONFIG_ADDRESS = 0x1E000000 + __CIC_TYPE_ADDRESS = 0x1E000004 + + # Cart config register bits + + __FLASH_ENABLE = (1 << 0) + __SDRAM_ENABLE = (1 << 1) + + + def __init__(self, config = {}): + self.__spi_controller = SpiController(cs_count=1) + self.__spi_controller.configure('ftdi://ftdi:2232h/1') + self.__spi = self.__spi_controller.get_port(0, float(config['spi_speed'])) + + self.__update_progress = config['update_progress'] + + if (not config['no_init']): + self.__reset() + self.__set_config(n64_disable=True, address_increment=True) + self.__write_word(self.__CART_CONFIG_ADDRESS, (self.__SDRAM_ENABLE | self.__FLASH_ENABLE)) + + self.__config = config + + + def __del__(self): + if (not self.__config['no_init']): + self.__reset() + self.__spi_controller.terminate() + + + def __get_status(self, field=None): + status_word = struct.unpack('>I', self.__spi.exchange([self.__CMD_STATUS], 4))[0] + status = { + 'status': hex(status_word), + 'control_byte': (status_word & (0xFF << 24)) >> 24, + 'address_increment': (status_word & (0x1 << 23)) >> 23, + 'n64_disabled': (status_word & (0x1 << 22)) >> 22, + 'write_used': (status_word & (0x7FF << 11)) >> 11, + 'read_used': (status_word & (0x7FF << 0)) >> 0, + } + return status.get(field) if field else status + + + def __set_config(self, n64_disable=False, address_increment=True): + config = ( + ((1 if address_increment else 0) << 1) | + ((1 if n64_disable else 0) << 0) + ) + self.__spi.write(bytearray([self.__CMD_CONFIG]) + struct.pack('>I', int(config))) + + + def __set_address(self, address): + self.__spi.write(bytearray([self.__CMD_ADDR]) + struct.pack('>I', int(address))) + + + def __set_read_length(self, length): + self.__spi.write(bytearray([self.__CMD_READ_LENGTH]) + struct.pack('>I', int(length - 1))) + + + def __read_data(self, length): + return self.__spi.exchange([self.__CMD_READ], int(length * 4)) + + + def __write_data(self, data): + self.__spi.write(bytearray([self.__CMD_WRITE]) + data) + + + def __cart_reset(self): + self.__spi.write([self.__CMD_CART_RESET, 0x00, 0x00, 0x00, 0x00]) + + + def __spi_reset(self): + self.__spi.write([self.__CMD_SPI_RESET]) + + + def __reset(self): + self.__spi_reset() + self.__cart_reset() + + + def __wait_for_read_fill(self, length): + while (self.__get_status('read_used') < int(length)): + pass + + + def __wait_for_write_space(self, length): + while ((self.__FIFO_SIZE - self.__get_status('write_used')) < int(length)): + pass + + + def __wait_for_write_completion(self): + while (self.__get_status('write_used') > 0): + pass + + + def __read_word(self, address): + self.__set_address(address) + self.__set_read_length(1) + self.__wait_for_read_fill(1) + return struct.unpack('>I', self.__read_data(1))[0] + + + def __write_word(self, address, data): + self.__set_address(address) + self.__wait_for_write_space(1) + self.__write_data(struct.pack('>I', data)) + + + def __flash_operation(self, byte, mode='s', direction='w', select=False, cfg_mode=True): + return int( + ((1 if cfg_mode else 0) << 12) | + ((1 if mode == 'q' else 0) << 11) | + ((1 if direction == 'w' else 0) << 9) | + ((1 if select else 0) << 8) | + (byte & 0xFF) + ) + + + def __flash_create_operation(self, byte, mode='s', direction='w', select=False, cfg_mode=True): + return bytearray(struct.pack('>I', self.__flash_operation(byte, mode, direction, select, cfg_mode))) + + + def __flash_issue_operation(self, byte, mode='s', direction='w', select=False, cfg_mode=True): + self.__write_word(self.__FLASH_CFG_ADDRESS, self.__flash_operation(byte, mode, direction, select, cfg_mode)) + return ((self.__read_word(self.__FLASH_CFG_ADDRESS) & 0xFF) if direction == 'r' else 0x00).to_bytes(1, 'big') + + + def __flash_exchange(self, command, address=None, data=[], length=0, address_mode='s', write_mode='s', read_mode='s', cfg_mode=True): + operations = bytearray([]) + + operations += self.__flash_create_operation(command) + + if (address != None): + for byte in bytearray(struct.pack('>I', address))[1:4]: + operations += self.__flash_create_operation(byte, mode=address_mode) + + for byte in data: + operations += self.__flash_create_operation(byte, mode=write_mode) + + if (not length): + operations += self.__flash_create_operation(0x00, select=True, cfg_mode=cfg_mode) + + self.__set_address(self.__FLASH_CFG_ADDRESS) + self.__write_data(operations) + self.__wait_for_write_completion() + + data_read = bytearray([]) + + for _ in range(length): + data_read += self.__flash_issue_operation(0x00, mode=read_mode, direction='r') + + if (length > 0): + self.__flash_issue_operation(0x00, select=True, cfg_mode=cfg_mode) + + return data_read + + + def __flash_exit_xip(self): + self.__flash_exchange(0xFF, data=[0xFF, 0xFF]) + + + def __flash_enter_xip(self): + self.__flash_exchange( + 0xEB, + address=0, + data=[0xA0, 0x00, 0x00], + length=1, + address_mode='q', + write_mode='q', + read_mode='q', + cfg_mode=False + ) + + + def __flash_read_status(self): + return self.__flash_exchange(0x05, length=1)[0] + + + def __flash_write_enable(self): + self.__flash_exchange(0x06) + + + def __flash_write_disable(self): + self.__flash_exchange(0x04) + + + def __flash_sector_erase(self, address): + self.__flash_exchange(0x20, address=address) + + + def __flash_chip_erase(self): + self.__flash_exchange(0xC7) + self.__flash_exchange(0x60) + + + def __flash_program_page(self, address, data): + self.__flash_exchange(0x32, address=address, data=data, address_mode='s', write_mode='q') + + + def __flash_wait_for_not_busy(self): + while (self.__flash_read_status() & 0x01): + pass + + + def __flash_wait_for_write_enable_latch(self): + while (not (self.__flash_read_status() & 0x02)): + pass + + + def __calculate_length_in_words(self, length): + return int((length + 3) / 4) + + + def __get_chunk_iterator(self, data, chunk_size): + for i in range(0, len(data), chunk_size): + yield (data[i:i + chunk_size], i) + + + def print_status(self): + print(self.__get_status()) + + + def read_rom(self, length, from_flash=False): + length_in_words = self.__calculate_length_in_words(length) + chunk_size = int((self.__FIFO_SIZE_BYTES * 3) / 4) + data = bytearray([]) + + self.__set_address(self.__FLASH_ADDRESS if from_flash else self.__SDRAM_ADDRESS) + self.__set_read_length(length_in_words) + + while (length > 0): + current_chunk_size = min(length, chunk_size) + read_length_in_words = self.__calculate_length_in_words(current_chunk_size) + self.__wait_for_read_fill(read_length_in_words) + data += self.__read_data(read_length_in_words) + length -= current_chunk_size + if (self.__update_progress): self.__update_progress(len(data)) + + return data + + + def write_sdram(self, data): + length = len(data) + chunk_size = int((self.__FIFO_SIZE_BYTES * 3) / 4) + + self.__set_address(self.__SDRAM_ADDRESS) + + for (chunk, offset) in self.__get_chunk_iterator(data, chunk_size): + current_chunk_size = min(chunk_size, length - offset) + self.__wait_for_write_space(self.__calculate_length_in_words(current_chunk_size)) + self.__write_data(chunk) + if (self.__update_progress): self.__update_progress(offset) + + if (self.__update_progress): self.__update_progress(length) + + self.__wait_for_write_completion() + + + def write_flash(self, data): + self.__set_config(n64_disable=True, address_increment=False) + + self.__flash_exit_xip() + + print('\rErasing Flash, this may take a while...', end=' ') + + self.__flash_write_enable() + self.__flash_wait_for_write_enable_latch() + self.__flash_chip_erase() + self.__flash_wait_for_not_busy() + + print('Done') + + for (page, offset) in self.__get_chunk_iterator(data, self.__FLASH_PAGE_SIZE): + self.__flash_write_enable() + self.__flash_wait_for_write_enable_latch() + self.__flash_program_page(offset, page) + self.__flash_wait_for_not_busy() + if (self.__update_progress): self.__update_progress(offset) + + self.__flash_write_disable() + + self.__flash_enter_xip() + + self.__set_config(n64_disable=True, address_increment=True) + + + def set_cic_type(self, cic_type=0): + cic_lut = { + 6101: 0x11, + 6102: 0x12, + 6103: 0x13, + 6105: 0x14, + 6106: 0x15, + 7101: 0x02, + 7102: 0x01, + 7103: 0x03, + 7105: 0x04, + 7106: 0x05, + } + self.__write_word(self.__CIC_TYPE_ADDRESS, int(cic_lut.get(cic_type) or 0)) + + + +if __name__ == "__main__": + formatter = lambda prog: argparse.HelpFormatter(prog, max_help_position=30) + parser = argparse.ArgumentParser(description='Write/Read N64 ROM to SummerCart', formatter_class=formatter) + parser.add_argument('-s', '--speed', default=30E6, required=False, help='set SPI communication speed (in Hz, 30MHz max)') + parser.add_argument('-r', '--read', action='store_true', required=False, help='read ROM instead of writing') + parser.add_argument('-l', '--length', required=False, help='specify ROM length to read (in bytes)', default=2**26) + parser.add_argument('-f', '--flash', action='store_true', required=False, help='use Flash instead of SDRAM') + parser.add_argument('-c', '--cic', type=int, required=False, help='set CIC type to use by bootloader') + parser.add_argument('-q', '--status', action='store_true', required=False, help='just query and print the status word') + parser.add_argument('rom', help='path to ROM file (only .z64 files are supported)', nargs='?') + args = parser.parse_args() + + if ((len(sys.argv) == 1) or (not args.rom and (args.read or args.flash))): + parser.print_help() + parser.exit() + + bar = progressbar.DataTransferBar() + + def update_progress(length): + bar.update(length) + + config = { + 'no_init': args.status, + 'spi_speed': args.speed, + 'update_progress': update_progress, + } + + banger = SummerBanger64(config) + + if (args.cic != None): + banger.set_cic_type(args.cic) + elif (args.rom and not args.flash): + banger.set_cic_type() + + if (args.status): + banger.print_status() + elif (args.rom): + if (args.read): + with open(args.rom, 'wb') as f: + length = int(args.length) + bar.max_value = length + data = banger.read_rom(length, from_flash=args.flash) + f.write(data) + else: + with open(args.rom, 'rb') as f: + data = f.read() + bar.max_value = len(data) + if (args.flash): + banger.write_flash(data) + else: + banger.write_sdram(data) diff --git a/sw/SummerBanger64/bang_flash.bat b/sw/SummerBanger64/bang_flash.bat new file mode 100644 index 0000000..7d7b7e9 --- /dev/null +++ b/sw/SummerBanger64/bang_flash.bat @@ -0,0 +1,3 @@ +@echo off +cd /d "%~dp0" +python SummerBanger64.py -f "%~1" diff --git a/sw/SummerBanger64/bang_sdram.bat b/sw/SummerBanger64/bang_sdram.bat new file mode 100644 index 0000000..384f8de --- /dev/null +++ b/sw/SummerBanger64/bang_sdram.bat @@ -0,0 +1,3 @@ +@echo off +cd /d "%~dp0" +python SummerBanger64.py "%~1" diff --git a/sw/SummerBanger64/requirements.txt b/sw/SummerBanger64/requirements.txt new file mode 100644 index 0000000..e2f93e0 --- /dev/null +++ b/sw/SummerBanger64/requirements.txt @@ -0,0 +1,2 @@ +pyftdi>=0.51.2 +progressbar2>=3.53.1 diff --git a/sw/SummerLoader/README.md b/sw/SummerLoader/README.md deleted file mode 100644 index e69de29..0000000 diff --git a/sw/SummerLoader64/.gitignore b/sw/SummerLoader64/.gitignore new file mode 100644 index 0000000..796b96d --- /dev/null +++ b/sw/SummerLoader64/.gitignore @@ -0,0 +1 @@ +/build diff --git a/sw/SummerLoader64/Makefile b/sw/SummerLoader64/Makefile new file mode 100644 index 0000000..6f4715d --- /dev/null +++ b/sw/SummerLoader64/Makefile @@ -0,0 +1,57 @@ +ROOTDIR = $(N64_INST) +GCCN64PREFIX = $(ROOTDIR)/bin/mips64-elf- +CHKSUM64PATH = $(ROOTDIR)/bin/chksum64 +MKDFSPATH = $(ROOTDIR)/bin/mkdfs +HEADERPATH = $(ROOTDIR)/mips64-elf/lib +N64TOOL = $(ROOTDIR)/bin/n64tool +HEADERNAME = header +LINK_FLAGS = -L$(ROOTDIR)/mips64-elf/lib -ldragon -lc -lm -ldragonsys -Tn64.ld +CFLAGS = -std=gnu99 -march=vr4300 -mtune=vr4300 -Os -Wall -Werror -I$(ROOTDIR)/mips64-elf/include +ASFLAGS = -mtune=vr4300 -march=vr4300 +CC = $(GCCN64PREFIX)gcc +AS = $(GCCN64PREFIX)as +LD = $(GCCN64PREFIX)ld +OBJCOPY = $(GCCN64PREFIX)objcopy +OBJDUMP = $(GCCN64PREFIX)objdump + +SRC_DIRS = src +SRC_FILES = $(wildcard $(patsubst %, %/*.c, . $(SRC_DIRS))) +OBJ_FILES = $(addprefix build/, $(notdir $(SRC_FILES:.c=.o))) +VPATH = $(SRC_DIRS) + +ROM_SIZE = 1028k + +ifeq ($(N64_BYTE_SWAP),true) +ROM_EXTENSION = .v64 +N64_FLAGS = -b -l $(ROM_SIZE) -h $(HEADERPATH)/$(HEADERNAME) -o build/$(PROG_NAME)$(ROM_EXTENSION) +else +ROM_EXTENSION = .z64 +N64_FLAGS = -l $(ROM_SIZE) -h $(HEADERPATH)/$(HEADERNAME) -o build/$(PROG_NAME)$(ROM_EXTENSION) +endif + +PROG_NAME = SummerLoader64 + +all: make_output_dir build/$(PROG_NAME)$(ROM_EXTENSION) + +$(OBJ_FILES): Makefile + +build/$(PROG_NAME)$(ROM_EXTENSION): build/$(PROG_NAME).elf + $(OBJCOPY) build/$(PROG_NAME).elf build/$(PROG_NAME).bin -O binary + $(OBJDUMP) -S build/$(PROG_NAME).elf > build/$(PROG_NAME).lst + rm -f build/$(PROG_NAME)$(ROM_EXTENSION) + $(N64TOOL) $(N64_FLAGS) -t $(PROG_NAME) build/$(PROG_NAME).bin + $(CHKSUM64PATH) build/$(PROG_NAME)$(ROM_EXTENSION) + +build/$(PROG_NAME).elf: $(OBJ_FILES) + $(LD) -o build/$(PROG_NAME).elf $(OBJ_FILES) $(LINK_FLAGS) + +build/%.o: %.c + $(COMPILE.c) $(OUTPUT_OPTION) $< + +make_output_dir: + $(shell mkdir ./build 2>/dev/null) + +clean: + rm -rf ./build + +.PHONY: all clean make_output_dir diff --git a/sw/SummerLoader64/README.md b/sw/SummerLoader64/README.md new file mode 100644 index 0000000..d034c11 --- /dev/null +++ b/sw/SummerLoader64/README.md @@ -0,0 +1,7 @@ +# SummerLoader64 + +A N64 bootloader for SummerCart64. This project is mainly based on work by **`jago85`** contained in [Brutzelkarte_Bootloader repository](https://github.com/jago85/Brutzelkarte_Bootloader) with some modifications that made code a little bit more readable. + +## TODO + +- Expand documentation diff --git a/sw/SummerLoader64/src/boot.c b/sw/SummerLoader64/src/boot.c new file mode 100644 index 0000000..fd4175c --- /dev/null +++ b/sw/SummerLoader64/src/boot.c @@ -0,0 +1,210 @@ +#include + +#include "boot.h" +#include "crc32.h" +#include "n64_regs.h" + +cart_header_t global_cart_header __attribute__((aligned(8))); + +cart_header_t *boot_load_cart_header(void) { + cart_header_t *cart_header_pointer = &global_cart_header; + + data_cache_hit_writeback_invalidate(cart_header_pointer, sizeof(cart_header_t)); + dma_read(cart_header_pointer, CART_BASE, sizeof(cart_header_t)); + data_cache_hit_invalidate(cart_header_pointer, sizeof(cart_header_t)); + + return cart_header_pointer; +} + +cic_type_t boot_get_cic_type(cart_header_t *cart_header) { + switch (crc32_calculate(cart_header->boot_code, sizeof(cart_header->boot_code))) { + case BOOT_CRC32_6101: + case BOOT_CRC32_7102: + return E_CIC_TYPE_6101; + case BOOT_CRC32_X102: + return E_CIC_TYPE_6102; + case BOOT_CRC32_X103: + return E_CIC_TYPE_6103; + case BOOT_CRC32_X105: + return E_CIC_TYPE_6105; + case BOOT_CRC32_X106: + return E_CIC_TYPE_6106; + default: + return E_CIC_TYPE_UNKNOWN; + } +} + +tv_type_t boot_get_tv_type(cart_header_t *cart_header) { + switch (cart_header->country_code) { + case 'D': + case 'F': + case 'H': + case 'I': + case 'P': + case 'S': + case 'W': + case 'X': + case 'Y': + return E_TV_TYPE_PAL; + case '7': + case 'A': + case 'C': + case 'E': + case 'J': + case 'K': + case 'N': + case 'U': + return E_TV_TYPE_NTSC; + case 'B': + return E_TV_TYPE_MPAL; + default: + return E_TV_TYPE_UNKNOWN; + } +} + +void boot(cic_type_t cic_type, tv_type_t tv_type) { + tv_type_t os_tv_type = tv_type == E_TV_TYPE_UNKNOWN ? OS_BOOT_CONFIG->tv_type : tv_type; + + volatile uint64_t gpr_regs[32]; + + const uint8_t cic_seeds[] = { + BOOT_SEED_X102, + BOOT_SEED_X101, + BOOT_SEED_X102, + BOOT_SEED_X103, + BOOT_SEED_X105, + BOOT_SEED_X106, + }; + + while (!(SP->status & SP_STATUS_HALT)); + + SP->status = SP_STATUS_CLEAR_INTERRUPT | SP_STATUS_SET_HALT; + + while (SP->dma_busy & SP_DMA_BUSY); + + PI->status = PI_STATUS_CLEAR_INTERRUPT | PI_STATUS_RESET_CONTROLLER; + VI->v_intr = 0x3FF; + VI->h_limits = 0; + VI->current_line = 0; + AI->dram_addr = 0; + AI->len = 0; + + while (SP->status & SP_STATUS_DMA_BUSY); + + if (DP_CMD->status & DP_CMD_STATUS_XBUS_DMEM_DMA) { + while (DP_CMD->status & DP_CMD_STATUS_PIPE_BUSY); + } + + DP_CMD->status = DP_CMD_STATUS_CLEAR_FLUSH | DP_CMD_STATUS_CLEAR_FREEZE | DP_CMD_STATUS_CLEAR_XBUS_DMEM_DMA; + + for (size_t i = 0; i < ARRAY_ITEMS(SP_MEM->dmem); i++) { + SP_MEM->dmem[i] = CART[i]; + } + + while (PI->status & (PI_STATUS_IO_BUSY | PI_STATUS_DMA_BUSY)); + + PI->status = PI_STATUS_CLEAR_INTERRUPT | PI_STATUS_RESET_CONTROLLER; + + if (cic_type == E_CIC_TYPE_6105) { + OS_BOOT_CONFIG->mem_size_6105 = OS_BOOT_CONFIG->mem_size; + } + + for (size_t i = 0; i < ARRAY_ITEMS(SP_MEM->imem); i++) { + SP_MEM->imem[i] = 0; + } + + if (cic_type == E_CIC_TYPE_6105) { + SP_MEM->imem[0] = 0x3C0DBFC0; + SP_MEM->imem[1] = os_tv_type == E_TV_TYPE_PAL ? 0xBDA807FC : 0x8DA807FC; + SP_MEM->imem[2] = 0x25AD07C0; + SP_MEM->imem[3] = 0x31080080; + SP_MEM->imem[4] = 0x5500FFFC; + SP_MEM->imem[5] = 0x3C0DBFC0; + SP_MEM->imem[6] = 0x8DA80024; + SP_MEM->imem[7] = 0x3C0BB000; + } + + for (size_t i = 0; i < ARRAY_ITEMS(gpr_regs); i++) { + gpr_regs[i] = 0; + } + + gpr_regs[CPU_REG_T3] = (0xFFFFFFFFLL << 32) | ((uint32_t) &SP_MEM->dmem[16]); + gpr_regs[CPU_REG_S4] = os_tv_type; + gpr_regs[CPU_REG_S6] = cic_seeds[cic_type]; + if (os_tv_type == E_TV_TYPE_PAL) { + gpr_regs[CPU_REG_S7] = 6; + } + gpr_regs[CPU_REG_SP] = (0xFFFFFFFFLL << 32) | ((uint32_t) &SP_MEM->imem[ARRAY_ITEMS(SP_MEM->imem) - 4]); + gpr_regs[CPU_REG_RA] = (0xFFFFFFFFLL << 32) | ((uint32_t) &SP_MEM->imem[(os_tv_type == E_TV_TYPE_PAL) ? 341 : 340]); + + __asm__ ( + ".set noat \n\t" + ".set noreorder \n\t" + "li $t0, 0x34000000 \n\t" + "mtc0 $t0, $12 \n\t" + "nop \n\t" + "li $t0, 0x0006E463 \n\t" + "mtc0 $t0, $16 \n\t" + "nop \n\t" + "li $t0, 0x00005000 \n\t" + "mtc0 $t0, $9 \n\t" + "nop \n\t" + "li $t0, 0x0000005C \n\t" + "mtc0 $t0, $13 \n\t" + "nop \n\t" + "li $t0, 0x007FFFF0 \n\t" + "mtc0 $t0, $4 \n\t" + "nop \n\t" + "li $t0, 0xFFFFFFFF \n\t" + "mtc0 $t0, $14 \n\t" + "nop \n\t" + "mtc0 $t0, $30 \n\t" + "nop \n\t" + "lui $t0, 0x0000 \n\t" + "mthi $t0 \n\t" + "nop \n\t" + "mtlo $t0 \n\t" + "nop \n\t" + "ctc1 $t0, $31 \n\t" + "nop \n\t" + "add $ra, $zero, %[gpr_regs] \n\t" + "ld $at, 0x08($ra) \n\t" + "ld $v0, 0x10($ra) \n\t" + "ld $v1, 0x18($ra) \n\t" + "ld $a0, 0x20($ra) \n\t" + "ld $a1, 0x28($ra) \n\t" + "ld $a2, 0x30($ra) \n\t" + "ld $a3, 0x38($ra) \n\t" + "ld $t0, 0x40($ra) \n\t" + "ld $t1, 0x48($ra) \n\t" + "ld $t2, 0x50($ra) \n\t" + "ld $t3, 0x58($ra) \n\t" + "ld $t4, 0x60($ra) \n\t" + "ld $t5, 0x68($ra) \n\t" + "ld $t6, 0x70($ra) \n\t" + "ld $t7, 0x78($ra) \n\t" + "ld $s0, 0x80($ra) \n\t" + "ld $s1, 0x88($ra) \n\t" + "ld $s2, 0x90($ra) \n\t" + "ld $s3, 0x98($ra) \n\t" + "ld $s4, 0xA0($ra) \n\t" + "ld $s5, 0xA8($ra) \n\t" + "ld $s6, 0xB0($ra) \n\t" + "ld $s7, 0xB8($ra) \n\t" + "ld $t8, 0xC0($ra) \n\t" + "ld $t9, 0xC8($ra) \n\t" + "ld $k0, 0xD0($ra) \n\t" + "ld $k1, 0xD8($ra) \n\t" + "ld $gp, 0xE0($ra) \n\t" + "ld $sp, 0xE8($ra) \n\t" + "ld $fp, 0xF0($ra) \n\t" + "ld $ra, 0xF8($ra) \n\t" + "jr $t3 \n\t" + "nop" + : + : [gpr_regs] "r" (gpr_regs) + : "t0" + ); + + while (1); +} diff --git a/sw/SummerLoader64/src/boot.h b/sw/SummerLoader64/src/boot.h new file mode 100644 index 0000000..c059abb --- /dev/null +++ b/sw/SummerLoader64/src/boot.h @@ -0,0 +1,77 @@ +#ifndef BOOT_H__ +#define BOOT_H__ + +#define BOOT_CRC32_6101 (0x6170A4A1) +#define BOOT_CRC32_7102 (0x009E9EA3) +#define BOOT_CRC32_X102 (0x90BB6CB5) +#define BOOT_CRC32_X103 (0x0B050EE0) +#define BOOT_CRC32_X105 (0x98BC2C86) +#define BOOT_CRC32_X106 (0xACC8580A) + +#define BOOT_SEED_X102 (0x3F) +#define BOOT_SEED_X101 (0x3F) +#define BOOT_SEED_X102 (0x3F) +#define BOOT_SEED_X103 (0x78) +#define BOOT_SEED_X105 (0x91) +#define BOOT_SEED_X106 (0x85) + +typedef enum cic_type_e { + E_CIC_TYPE_UNKNOWN, + E_CIC_TYPE_6101, + E_CIC_TYPE_6102, + E_CIC_TYPE_6103, + E_CIC_TYPE_6105, + E_CIC_TYPE_6106, + E_CIC_TYPE_END, +} cic_type_t; + +typedef enum tv_type_e { + E_TV_TYPE_PAL, + E_TV_TYPE_NTSC, + E_TV_TYPE_MPAL, + E_TV_TYPE_UNKNOWN, +} tv_type_t; + +struct cart_header_s { + uint32_t pi_conf; + uint32_t clock_rate; + uint32_t boot_addr; + uint32_t release_addr; + uint32_t crc_1; + uint32_t crc_2; + uint32_t __unused_1[2]; + char name[20]; + uint32_t __unused_2; + uint32_t format; + char id[2]; + char country_code; + uint8_t version; + uint32_t boot_code[1008]; +} __attribute__((packed, aligned(1))); + +typedef struct cart_header_s cart_header_t; + +struct os_boot_config_s { + uint32_t tv_type; + uint32_t rom_type; + uint32_t rom_base; + uint32_t reset_type; + uint32_t cic_id; + uint32_t version; + uint32_t mem_size; + uint8_t app_nmi_buffer[64]; + uint32_t __unused[37]; + uint32_t mem_size_6105; +} __attribute__((packed, aligned(1))); + +typedef struct os_boot_config_s os_boot_config_t; + +#define OS_BOOT_CONFIG_BASE (0xA0000300) +#define OS_BOOT_CONFIG ((os_boot_config_t *) OS_BOOT_CONFIG_BASE) + +cart_header_t *boot_load_cart_header(void); +cic_type_t boot_get_cic_type(cart_header_t *cart_header); +tv_type_t boot_get_tv_type(cart_header_t *cart_header); +void boot(cic_type_t cic_type, tv_type_t tv_type); + +#endif diff --git a/sw/SummerLoader64/src/crc32.c b/sw/SummerLoader64/src/crc32.c new file mode 100644 index 0000000..5f99f8b --- /dev/null +++ b/sw/SummerLoader64/src/crc32.c @@ -0,0 +1,50 @@ +#include + +#include "crc32.h" + +const uint32_t crc_table[256] = { + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3, + 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7, + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5, + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172, 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940, 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59, + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F, + 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D, + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A, 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433, + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01, + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E, 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, + 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65, + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB, + 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9, + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086, 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F, + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD, + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683, + 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1, + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7, + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5, + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B, + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79, + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236, 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, + 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04, 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D, + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713, + 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21, + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E, 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777, + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45, + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2, 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB, + 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0, 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9, + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF, + 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D, +}; + +uint32_t crc32_calculate(void *buffer, size_t length) { + uint32_t crc32 = 0xFFFFFFFF; + + uint8_t *byte_pointer = (uint8_t *) buffer; + + while (length--) { + crc32 = (crc32 >> 8) ^ crc_table[(crc32 & 0xFF) ^ (*byte_pointer++)]; + } + + return ~crc32; +} diff --git a/sw/SummerLoader64/src/crc32.h b/sw/SummerLoader64/src/crc32.h new file mode 100644 index 0000000..07c625c --- /dev/null +++ b/sw/SummerLoader64/src/crc32.h @@ -0,0 +1,8 @@ +#ifndef CRC32_H__ +#define CRC32_H__ + +#include + +uint32_t crc32_calculate(void *buffer, size_t length); + +#endif diff --git a/sw/SummerLoader64/src/main.c b/sw/SummerLoader64/src/main.c new file mode 100644 index 0000000..5b93fb4 --- /dev/null +++ b/sw/SummerLoader64/src/main.c @@ -0,0 +1,32 @@ +#include + +#include "boot.h" +#include "sc64.h" + +int main(void) { + init_interrupts(); + + sc64_enable_sdram(); + sc64_disable_flash(); + + cic_type_t cic_type = sc64_get_cic_type(); + tv_type_t tv_type = sc64_get_tv_type(); + + if (cic_type == E_CIC_TYPE_UNKNOWN || tv_type == E_TV_TYPE_UNKNOWN) { + // Try to guess CIC and TV type from ROM in SDRAM if no override is provided + + cart_header_t *cart_header = boot_load_cart_header(); + + if (cic_type == E_CIC_TYPE_UNKNOWN) { + cic_type = boot_get_cic_type(cart_header); + } + + if (tv_type == E_TV_TYPE_UNKNOWN) { + tv_type = boot_get_tv_type(cart_header); + } + } + + disable_interrupts(); + + boot(cic_type, tv_type); +} diff --git a/sw/SummerLoader64/src/n64_regs.h b/sw/SummerLoader64/src/n64_regs.h new file mode 100644 index 0000000..7036b41 --- /dev/null +++ b/sw/SummerLoader64/src/n64_regs.h @@ -0,0 +1,143 @@ +#ifndef N64_REGS_H__ +#define N64_REGS_H__ + +#include + +#define ARRAY_ITEMS(x) (sizeof(x) / sizeof(x[0])) + +#define CPU_REG_Z0 (0) +#define CPU_REG_AT (1) +#define CPU_REG_V0 (2) +#define CPU_REG_V1 (3) +#define CPU_REG_A0 (4) +#define CPU_REG_A1 (5) +#define CPU_REG_A2 (6) +#define CPU_REG_A3 (7) +#define CPU_REG_T0 (8) +#define CPU_REG_T1 (9) +#define CPU_REG_T2 (10) +#define CPU_REG_T3 (11) +#define CPU_REG_T4 (12) +#define CPU_REG_T5 (13) +#define CPU_REG_T6 (14) +#define CPU_REG_T7 (15) +#define CPU_REG_S0 (16) +#define CPU_REG_S1 (17) +#define CPU_REG_S2 (18) +#define CPU_REG_S3 (19) +#define CPU_REG_S4 (20) +#define CPU_REG_S5 (21) +#define CPU_REG_S6 (22) +#define CPU_REG_S7 (23) +#define CPU_REG_T8 (24) +#define CPU_REG_T9 (25) +#define CPU_REG_K0 (26) +#define CPU_REG_K1 (27) +#define CPU_REG_GP (28) +#define CPU_REG_SP (29) +#define CPU_REG_FP (30) +#define CPU_REG_RA (31) + +typedef struct SP_MEM_s { + volatile uint32_t dmem[1024]; + volatile uint32_t imem[1024]; +} SP_MEM_t; + +typedef struct SP_regs_s { + volatile void *mem_addr; + volatile void *dram_addr; + volatile uint32_t rd_len; + volatile uint32_t wr_len; + volatile uint32_t status; + volatile uint32_t dma_full; + volatile uint32_t dma_busy; + volatile uint32_t semaphore; +} SP_regs_t; + +typedef struct DP_CMD_regs_s { + volatile void *start; + volatile void *end; + volatile void *current; + volatile uint32_t status; + volatile uint32_t clock; + volatile uint32_t buf_busy; + volatile uint32_t pipe_busy; + volatile uint32_t tmem; +} DP_CMD_regs_t; + +typedef struct VI_regs_s { + volatile uint32_t control; + volatile void *dram_addr; + volatile uint32_t h_width; + volatile uint32_t v_intr; + volatile uint32_t current_line; + volatile uint32_t timing; + volatile uint32_t v_sync; + volatile uint32_t h_sync; + volatile uint32_t h_sync_leap; + volatile uint32_t h_limits; + volatile uint32_t v_limits; + volatile uint32_t color_burst; + volatile uint32_t h_scale; + volatile uint32_t v_scale; +} VI_regs_t; + +typedef struct AI_regs_s { + volatile void *dram_addr; + volatile uint32_t len; + volatile uint32_t control; + volatile uint32_t status; + volatile uint32_t dacrate; + volatile uint32_t bitrate; +} AI_regs_t; + +typedef struct PI_regs_s { + volatile void *dram_addr; + volatile uint32_t cart_addr; + volatile uint32_t rd_len; + volatile uint32_t wr_len; + volatile uint32_t status; + volatile uint32_t dom1_lat; + volatile uint32_t dom1_pwd; + volatile uint32_t dom1_pgs; + volatile uint32_t dom1_rls; + volatile uint32_t dom2_lat; + volatile uint32_t dom2_pwd; + volatile uint32_t dom2_pgs; + volatile uint32_t dom2_rls; +} PI_regs_t; + +#define SP_MEM_BASE (0xA4000000) +#define SP_REGS_BASE (0xA4040000) +#define DP_CMD_REGS_BASE (0xA4100000) +#define VI_REGS_BASE (0xA4400000) +#define AI_REGS_BASE (0xA4500000) +#define PI_REGS_BASE (0xA4600000) +#define CART_BASE (0xB0000000) + +#define SP_MEM ((volatile SP_MEM_t *) SP_MEM_BASE) +#define SP ((volatile SP_regs_t *) SP_REGS_BASE) +#define DP_CMD ((volatile DP_CMD_regs_t *) DP_CMD_REGS_BASE) +#define VI ((volatile VI_regs_t *) VI_REGS_BASE) +#define AI ((volatile AI_regs_t *) AI_REGS_BASE) +#define PI ((volatile PI_regs_t *) PI_REGS_BASE) +#define CART ((volatile uint32_t *) CART_BASE) + +#define SP_STATUS_HALT (1 << 0) +#define SP_STATUS_DMA_BUSY (1 << 2) +#define SP_STATUS_SET_HALT (1 << 1) +#define SP_STATUS_CLEAR_INTERRUPT (1 << 3) +#define SP_DMA_BUSY (1 << 0) + +#define DP_CMD_STATUS_XBUS_DMEM_DMA (1 << 0) +#define DP_CMD_STATUS_PIPE_BUSY (1 << 5) +#define DP_CMD_STATUS_CLEAR_XBUS_DMEM_DMA (1 << 0) +#define DP_CMD_STATUS_CLEAR_FREEZE (1 << 2) +#define DP_CMD_STATUS_CLEAR_FLUSH (1 << 4) + +#define PI_STATUS_DMA_BUSY (1 << 0) +#define PI_STATUS_IO_BUSY (1 << 1) +#define PI_STATUS_RESET_CONTROLLER (1 << 0) +#define PI_STATUS_CLEAR_INTERRUPT (1 << 1) + +#endif diff --git a/sw/SummerLoader64/src/sc64.c b/sw/SummerLoader64/src/sc64.c new file mode 100644 index 0000000..8fea3e9 --- /dev/null +++ b/sw/SummerLoader64/src/sc64.c @@ -0,0 +1,55 @@ +#include +#include + +#include "sc64.h" +#include "sc64_regs.h" + +static void sc64_enable_peripheral(uint32_t mask) { + uint32_t config = io_read(SC64_CONFIG_REG); + + config |= mask; + + io_write(SC64_CONFIG_REG, config); +} + +static void sc64_disable_peripheral(uint32_t mask) { + uint32_t config = io_read(SC64_CONFIG_REG); + + config &= ~mask; + + io_write(SC64_CONFIG_REG, config); +} + +void sc64_enable_sdram(void) { + sc64_enable_peripheral(SC64_CONFIG_SDRAM_ENABLE); +} + +void sc64_disable_sdram(void) { + sc64_disable_peripheral(SC64_CONFIG_SDRAM_ENABLE); +} + +void sc64_enable_flash(void) { + sc64_enable_peripheral(SC64_CONFIG_FLASH_ENABLE); +} + +void sc64_disable_flash(void) { + sc64_disable_peripheral(SC64_CONFIG_FLASH_ENABLE); +} + +cic_type_t sc64_get_cic_type(void) { + uint32_t boot = io_read(SC64_BOOT_REG); + + cic_type_t cic_type = (cic_type_t)(SC64_BOOT_CIC_TYPE(boot)); + + return (cic_type >= E_CIC_TYPE_END) ? E_CIC_TYPE_UNKNOWN : cic_type; +} + +tv_type_t sc64_get_tv_type(void) { + uint32_t boot = io_read(SC64_BOOT_REG); + + if ((SC64_BOOT_CIC_TYPE(boot) == E_CIC_TYPE_UNKNOWN) || (SC64_BOOT_CIC_TYPE(boot) >= E_CIC_TYPE_END)) { + return E_TV_TYPE_UNKNOWN; + } else { + return (tv_type_t)(SC64_BOOT_TV_TYPE(boot)); + } +} diff --git a/sw/SummerLoader64/src/sc64.h b/sw/SummerLoader64/src/sc64.h new file mode 100644 index 0000000..1206276 --- /dev/null +++ b/sw/SummerLoader64/src/sc64.h @@ -0,0 +1,13 @@ +#ifndef SC64_H__ +#define SC64_H__ + +#include "boot.h" + +void sc64_enable_flash(void); +void sc64_disable_flash(void); +void sc64_enable_sdram(void); +void sc64_disable_sdram(void); +cic_type_t sc64_get_cic_type(void); +tv_type_t sc64_get_tv_type(void); + +#endif diff --git a/sw/SummerLoader64/src/sc64_regs.h b/sw/SummerLoader64/src/sc64_regs.h new file mode 100644 index 0000000..0ce10b7 --- /dev/null +++ b/sw/SummerLoader64/src/sc64_regs.h @@ -0,0 +1,26 @@ +#ifndef SC64_REGS_H__ +#define SC64_REGS_H__ + +// SummerCart64 config register + +#define SC64_CONFIG_REG (0x1E000000) + +#define SC64_CONFIG_FLASH_ENABLE (1 << 0) +#define SC64_CONFIG_SDRAM_ENABLE (1 << 1) + +// Boot CIC and TV type override register + +#define SC64_BOOT_REG (0x1E000004) + +#define SC64_BOOT_CIC_TYPE_MSK (0x0F) +#define SC64_BOOT_CIC_TYPE_BIT (0) +#define SC64_BOOT_CIC_TYPE(x) (((x) & SC64_BOOT_CIC_TYPE_MSK) >> SC64_BOOT_CIC_TYPE_BIT) +#define SC64_BOOT_TV_TYPE_MSK (0x30) +#define SC64_BOOT_TV_TYPE_BIT (4) +#define SC64_BOOT_TV_TYPE(x) (((x) & SC64_BOOT_TV_TYPE_MSK) >> SC64_BOOT_TV_TYPE_BIT) + +// Flash arbitrary command register + +#define SC64_FLASH_CFG_REG (0x1C000000) + +#endif