From c78a67949b8fdd9b4f19fd9ee37b20e7d8d674e8 Mon Sep 17 00:00:00 2001 From: Polprzewodnikowy Date: Sat, 28 Aug 2021 04:15:24 +0200 Subject: [PATCH] cpu to sdram --- fw/SummerCart64.qsf | 9 ++-- fw/cpu/controller/process.c | 27 ++++++++++++ fw/cpu/controller/prv32_rwx.ld | 8 ++-- fw/cpu/controller/sys.h | 6 ++- fw/rtl/SummerCart64.sv | 4 ++ fw/rtl/cpu/cpu_sdram.sv | 76 ++++++++++++++++++++++++++++++++++ fw/rtl/cpu/cpu_soc.sv | 7 ++++ fw/rtl/n64/n64_sdram.sv | 39 ++++++++++++----- fw/rtl/n64/n64_soc.sv | 2 + fw/rtl/system/sc64.sv | 1 + 10 files changed, 160 insertions(+), 19 deletions(-) create mode 100644 fw/rtl/cpu/cpu_sdram.sv diff --git a/fw/SummerCart64.qsf b/fw/SummerCart64.qsf index fd34a93..cd12b94 100644 --- a/fw/SummerCart64.qsf +++ b/fw/SummerCart64.qsf @@ -19,7 +19,7 @@ # # Quartus Prime # Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition -# Date created = 00:43:07 August 26, 2021 +# Date created = 03:59:09 August 28, 2021 # # -------------------------------------------------------------------------- # # @@ -61,6 +61,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_dma.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_gpio.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_i2c.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_ram.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_sdram.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_soc.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_uart.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_usb.sv @@ -80,6 +81,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/sc64.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/system.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/usb/usb_ft1248.sv set_global_assignment -name SIGNALTAP_FILE output_files/signaltap.stp +set_global_assignment -name SLD_FILE db/signaltap_auto_stripped.stp # Pin & Location Assignments # ========================== @@ -298,6 +300,7 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- @@ -321,6 +324,4 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - # ======================== # end ENTITY(intel_gpio_ddro) -# --------------------------- -set_global_assignment -name SLD_FILE db/signaltap_auto_stripped.stp -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +# --------------------------- \ No newline at end of file diff --git a/fw/cpu/controller/process.c b/fw/cpu/controller/process.c index 85e02c5..42c4ba0 100644 --- a/fw/cpu/controller/process.c +++ b/fw/cpu/controller/process.c @@ -8,12 +8,14 @@ static const uint8_t err_token[3] = { 'E', 'R', 'R' }; static uint8_t save_type = 0; static uint16_t cic_type = 0xFFFF; static uint8_t tv_type = 0xFF; +static volatile uint32_t *save_pointer = &SDRAM + DEFAULT_SAVE_OFFSET; void process_usb (void); void process_cfg (void); void process_dd (void); void process_si (void); void process_uart (void); +void process_rtc (void); void cfg_set_save_type (uint8_t type); void cfg_update_config (uint32_t *args); @@ -24,6 +26,7 @@ void process (void) { process_dd(); process_si(); process_uart(); + process_rtc(); } } @@ -182,6 +185,10 @@ void process_uart (void) { } } +void process_rtc (void) { + +} + void cfg_update_config (uint32_t *args) { switch (args[0]) { case 0: { @@ -263,5 +270,25 @@ void cfg_set_save_type (uint8_t type) { } } + save_pointer = &SDRAM + CFG->SAVE_OFFSET; save_type = type; } + +// void print (const char *text) { +// while (*text != '\0') { +// while (!(UART->SCR & UART_SCR_TXE)); +// UART->DR = *text++; +// } +// } + +// const char hex_char_map[16] = { +// '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' +// }; + +// void print_02hex (unsigned char number) { +// char buffer[3]; +// buffer[0] = hex_char_map[number >> 4]; +// buffer[1] = hex_char_map[number & 0x0F]; +// buffer[2] = '\0'; +// print(buffer); +// } diff --git a/fw/cpu/controller/prv32_rwx.ld b/fw/cpu/controller/prv32_rwx.ld index d922671..df0e65c 100644 --- a/fw/cpu/controller/prv32_rwx.ld +++ b/fw/cpu/controller/prv32_rwx.ld @@ -1,10 +1,12 @@ MEMORY { ram (rwx) : org = 0x00000000, len = 16k + bootloader (rx) : org = 0x10000000, len = 128 + sdram (rwx) : org = 0x80000000, len = 64M } __ram_size = LENGTH(ram); -__stack_pointer = ORIGIN(ram) + LENGTH(ram) - 16; +__stack_pointer = ORIGIN(ram) + LENGTH(ram) - 4; ENTRY(main) @@ -17,9 +19,9 @@ SECTIONS . = ALIGN(4); *(.text .text* .rodata .rodata* .srodata .srodata*); . = ALIGN(4); - *(.bss .bss.* .sbss .sbss.*); + *(.data .data.* .sdata .sdata.*); . = ALIGN(4); - *(.data .data.* .sdata .stada.*); + *(.bss .bss.* .sbss .sbss.*); . = ALIGN(4); } > ram AT > ram } diff --git a/fw/cpu/controller/sys.h b/fw/cpu/controller/sys.h index 62ace8b..94b8734 100644 --- a/fw/cpu/controller/sys.h +++ b/fw/cpu/controller/sys.h @@ -6,6 +6,10 @@ #include +#define DEFAULT_SAVE_OFFSET (0x03FE0000) +#define DEFAULT_DD_OFFSET (0x03BE0000) + + typedef volatile uint8_t io8_t; typedef volatile uint32_t io32_t; @@ -111,7 +115,7 @@ typedef volatile struct cfg_regs { #define SDRAM_BASE (0x80000000) -#define SDRAM (*((io32_t *) SDRAM_BASE) +#define SDRAM (*((io32_t *) SDRAM_BASE)) #define SDRAM_SIZE (64 * 1024 * 1024) diff --git a/fw/rtl/SummerCart64.sv b/fw/rtl/SummerCart64.sv index ac4e4a4..8d9112a 100644 --- a/fw/rtl/SummerCart64.sv +++ b/fw/rtl/SummerCart64.sv @@ -58,6 +58,8 @@ module SummerCart64 ( if_dma dma (); + if_sdram sdram (); + system system_inst ( .sys(sys) ); @@ -72,6 +74,7 @@ module SummerCart64 ( .sys(sys), .cfg(cfg), .dma(dma), + .sdram(sdram), .n64_pi_alel(i_n64_pi_alel), .n64_pi_aleh(i_n64_pi_aleh), @@ -95,6 +98,7 @@ module SummerCart64 ( .sys(sys), .cfg(cfg), .dma(dma), + .sdram(sdram), .gpio_o(gpio_o), .gpio_i(gpio_i), diff --git a/fw/rtl/cpu/cpu_sdram.sv b/fw/rtl/cpu/cpu_sdram.sv new file mode 100644 index 0000000..b1cd3d5 --- /dev/null +++ b/fw/rtl/cpu/cpu_sdram.sv @@ -0,0 +1,76 @@ +interface if_sdram (); + + logic request; + logic ack; + logic write; + logic [31:0] address; + logic [15:0] rdata; + logic [15:0] wdata; + + modport cpu ( + output request, + input ack, + output write, + output address, + input rdata, + output wdata + ); + + modport memory ( + input request, + output ack, + input write, + input address, + output rdata, + input wdata + ); + +endinterface + + +module cpu_sdram ( + if_system.sys sys, + if_cpu_bus bus, + if_sdram.cpu sdram +); + + logic request; + logic current_word; + logic [31:0] rdata; + + always_comb begin + bus.rdata = 32'd0; + if (bus.ack) begin + bus.rdata = rdata; + end + + sdram.write = current_word ? &bus.wmask[3:2] : &bus.wmask[1:0]; + sdram.address = {1'b0, bus.address[30:2], current_word, 1'b0}; + sdram.wdata = current_word ? bus.wdata[31:16] : bus.wdata[15:0]; + end + + always_ff @(posedge sys.clk) begin + bus.ack <= 1'b0; + + if (sys.reset) begin + sdram.request <= 1'b0; + end else begin + if (bus.request) begin + sdram.request <= 1'b1; + current_word <= 1'b0; + end + + if (sdram.ack) begin + if (!current_word) begin + current_word <= 1'b1; + rdata[31:16] <= sdram.rdata; + end else begin + bus.ack <= 1'b1; + sdram.request <= 1'b0; + rdata[15:0] <= sdram.rdata; + end + end + end + end + +endmodule diff --git a/fw/rtl/cpu/cpu_soc.sv b/fw/rtl/cpu/cpu_soc.sv index 8c9a84d..6acdea5 100644 --- a/fw/rtl/cpu/cpu_soc.sv +++ b/fw/rtl/cpu/cpu_soc.sv @@ -2,6 +2,7 @@ module cpu_soc ( if_system.sys sys, if_config.cpu cfg, if_dma dma, + if_sdram.cpu sdram, input [7:0] gpio_i, output [7:0] gpio_o, @@ -90,4 +91,10 @@ module cpu_soc ( .cfg(cfg) ); + cpu_sdram cpu_sdram_inst ( + .sys(sys), + .bus(bus.at[sc64::ID_CPU_SDRAM].device), + .sdram(sdram) + ); + endmodule diff --git a/fw/rtl/n64/n64_sdram.sv b/fw/rtl/n64/n64_sdram.sv index 56428ae..cc0e6fc 100644 --- a/fw/rtl/n64/n64_sdram.sv +++ b/fw/rtl/n64/n64_sdram.sv @@ -2,6 +2,7 @@ module n64_sdram ( if_system sys, if_n64_bus bus, if_dma.memory dma, + if_sdram.memory sdram, output sdram_cs, output sdram_ras, @@ -24,13 +25,14 @@ module n64_sdram ( S_WAIT } e_state; - typedef enum bit [0:0] { + typedef enum bit [1:0] { T_BUS, - T_DMA - } e_bus_or_dma; + T_DMA, + T_SDRAM + } e_source_request; e_state state; - e_bus_or_dma bus_or_dma; + e_source_request source_request; always_ff @(posedge sys.clk) begin if (sys.reset) begin @@ -39,13 +41,25 @@ module n64_sdram ( end else begin case (state) S_IDLE: begin - if (bus.request || dma.request) begin + if (bus.request || sdram.request || dma.request) begin state <= S_WAIT; mem_request <= 1'b1; - mem_write <= bus.request ? bus.write : dma.write; - mem_address <= bus.request ? bus.address : dma.address; - mem_wdata <= bus.request ? bus.wdata : dma.wdata; - bus_or_dma <= bus.request ? T_BUS : T_DMA; + if (bus.request) begin + mem_write <= bus.write; + mem_address <= bus.address; + mem_wdata <= bus.wdata; + source_request <= T_BUS; + end else if (sdram.request) begin + mem_write <= sdram.write; + mem_address <= sdram.address; + mem_wdata <= sdram.wdata; + source_request <= T_SDRAM; + end else if (dma.request) begin + mem_write <= dma.write; + mem_address <= dma.address; + mem_wdata <= dma.wdata; + source_request <= T_DMA; + end end end @@ -60,11 +74,14 @@ module n64_sdram ( end always_comb begin - bus.ack = bus_or_dma == T_BUS && mem_ack; + bus.ack = source_request == T_BUS && mem_ack; bus.rdata = bus.ack ? mem_rdata : 16'd0; - dma.ack = bus_or_dma == T_DMA && mem_ack; + dma.ack = source_request == T_DMA && mem_ack; dma.rdata = mem_rdata; + + sdram.ack = source_request == T_SDRAM && mem_ack; + sdram.rdata = mem_rdata; end memory_sdram memory_sdram_inst ( diff --git a/fw/rtl/n64/n64_soc.sv b/fw/rtl/n64/n64_soc.sv index 21aa1f6..f76d4a3 100644 --- a/fw/rtl/n64/n64_soc.sv +++ b/fw/rtl/n64/n64_soc.sv @@ -2,6 +2,7 @@ module n64_soc ( if_system sys, if_config cfg, if_dma.memory dma, + if_sdram.memory sdram, input n64_pi_alel, input n64_pi_aleh, @@ -39,6 +40,7 @@ module n64_soc ( .sys(sys), .bus(bus.at[sc64::ID_N64_SDRAM].device), .dma(dma), + .sdram(sdram), .sdram_cs(sdram_cs), .sdram_ras(sdram_ras), diff --git a/fw/rtl/system/sc64.sv b/fw/rtl/system/sc64.sv index 1f3b65f..71799f4 100644 --- a/fw/rtl/system/sc64.sv +++ b/fw/rtl/system/sc64.sv @@ -18,6 +18,7 @@ package sc64; ID_CPU_UART, ID_CPU_DMA, ID_CPU_CFG, + ID_CPU_SDRAM, __ID_CPU_END } e_cpu_id;