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https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-24 14:46:53 +01:00
sd dma fix
This commit is contained in:
parent
fb17b9c540
commit
cb17198089
@ -4,8 +4,8 @@ module sd_dma (
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input [3:0] i_dma_bank,
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input [3:0] i_dma_bank,
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input [23:0] i_dma_address,
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input [23:0] i_dma_address,
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input [14:0] i_dma_length,
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input [17:0] i_dma_length,
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output [14:0] o_dma_left,
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output [17:0] o_dma_left,
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input i_dma_load_bank_address,
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input i_dma_load_bank_address,
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input i_dma_load_length,
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input i_dma_load_length,
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input i_dma_direction,
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input i_dma_direction,
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@ -47,14 +47,14 @@ module sd_dma (
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end
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end
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end
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end
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reg [14:0] r_remaining;
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reg [17:0] r_remaining;
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assign o_dma_left = r_remaining;
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assign o_dma_left = r_remaining;
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always @(posedge i_clk) begin
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always @(posedge i_clk) begin
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if (i_dma_load_length && !o_dma_busy) begin
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if (i_dma_load_length && !o_dma_busy) begin
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r_remaining <= i_dma_length;
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r_remaining <= i_dma_length;
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end else if (w_request_successful && r_remaining > 15'd0) begin
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end else if (w_request_successful && r_remaining > 18'd0) begin
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r_remaining <= r_remaining - 1'd1;
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r_remaining <= r_remaining - 1'd1;
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end
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end
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end
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end
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@ -66,7 +66,7 @@ module sd_dma (
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if (i_dma_start && !o_dma_busy) begin
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if (i_dma_start && !o_dma_busy) begin
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o_dma_busy <= 1'b1;
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o_dma_busy <= 1'b1;
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end
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end
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if (i_dma_stop || (w_request_successful && r_remaining == 15'd0)) begin
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if (i_dma_stop || (w_request_successful && r_remaining == 18'd0)) begin
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o_dma_busy <= 1'b0;
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o_dma_busy <= 1'b0;
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end
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end
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end
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end
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@ -187,8 +187,8 @@ module sd_interface (
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wire [3:0] w_dma_bank;
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wire [3:0] w_dma_bank;
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wire [23:0] w_dma_address;
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wire [23:0] w_dma_address;
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wire [14:0] w_dma_length;
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wire [17:0] w_dma_length;
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wire [14:0] w_dma_left;
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wire [17:0] w_dma_left;
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wire w_dma_load_bank_address;
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wire w_dma_load_bank_address;
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wire w_dma_load_length;
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wire w_dma_load_length;
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wire w_dma_direction;
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wire w_dma_direction;
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@ -38,10 +38,10 @@ module sd_regs (
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output reg [3:0] o_dma_bank,
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output reg [3:0] o_dma_bank,
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output reg [23:0] o_dma_address,
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output reg [23:0] o_dma_address,
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output reg [14:0] o_dma_length,
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output reg [17:0] o_dma_length,
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input [3:0] i_dma_bank,
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input [3:0] i_dma_bank,
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input [23:0] i_dma_address,
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input [23:0] i_dma_address,
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input [14:0] i_dma_left,
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input [17:0] i_dma_left,
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output reg o_dma_load_bank_address,
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output reg o_dma_load_bank_address,
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output reg o_dma_load_length,
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output reg o_dma_load_length,
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output reg o_dma_direction,
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output reg o_dma_direction,
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@ -73,7 +73,7 @@ module sd_regs (
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always @(*) begin
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always @(*) begin
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o_dma_bank = i_data[31:28];
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o_dma_bank = i_data[31:28];
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o_dma_address = i_data[25:2];
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o_dma_address = i_data[25:2];
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o_dma_length = i_data[14:0];
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o_dma_length = i_data[17:0];
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o_dma_load_bank_address = w_write_request && !i_address[3] && (i_address[2:0] == SD_REG_DMA_ADDR);
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o_dma_load_bank_address = w_write_request && !i_address[3] && (i_address[2:0] == SD_REG_DMA_ADDR);
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o_dma_load_length = w_write_request && !i_address[3] && (i_address[2:0] == SD_REG_DMA_LEN);
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o_dma_load_length = w_write_request && !i_address[3] && (i_address[2:0] == SD_REG_DMA_LEN);
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o_busy = 1'b0;
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o_busy = 1'b0;
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@ -210,7 +210,7 @@ module sd_regs (
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end
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end
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SD_REG_DMA_LEN: begin
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SD_REG_DMA_LEN: begin
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o_data <= {17'd0, i_dma_left};
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o_data <= {14'd0, i_dma_left};
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end
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end
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endcase
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endcase
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end else begin
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end else begin
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@ -165,8 +165,8 @@ typedef struct sc64_sd_registers_s {
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#define SC64_SD_DMA_BANK_GET(addr) (((addr) >> 28) & 0xF)
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#define SC64_SD_DMA_BANK_GET(addr) (((addr) >> 28) & 0xF)
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#define SC64_SD_DMA_BANK_ADDR(b, a) ((((b) & 0xF) << 28) | ((a) & 0x3FFFFFC))
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#define SC64_SD_DMA_BANK_ADDR(b, a) ((((b) & 0xF) << 28) | ((a) & 0x3FFFFFC))
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#define SC64_SD_DMA_LEN_GET(len) (((len) & 0x7FFF) * 4)
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#define SC64_SD_DMA_LEN_GET(len) (((len) & 0x3FFFF) * 4)
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#define SC64_SD_DMA_LEN(l) ((((l) / 4) - 1) & 0x7FFF)
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#define SC64_SD_DMA_LEN(l) ((((l) / 4) - 1) & 0x3FFFF)
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#endif
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#endif
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@ -379,7 +379,6 @@ sc64_sd_err_t sc64_sd_read_sectors(uint32_t starting_sector, size_t count, void
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}
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}
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sc64_sd_err_t sc64_sd_read_sectors_dma(uint32_t starting_sector, size_t count, uint8_t bank, uint32_t address) {
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sc64_sd_err_t sc64_sd_read_sectors_dma(uint32_t starting_sector, size_t count, uint8_t bank, uint32_t address) {
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size_t num_transfers;
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size_t sectors_left;
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size_t sectors_left;
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uint32_t current_sector;
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uint32_t current_sector;
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uint32_t current_address;
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uint32_t current_address;
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@ -397,7 +396,6 @@ sc64_sd_err_t sc64_sd_read_sectors_dma(uint32_t starting_sector, size_t count, u
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return E_PAR_ERROR;
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return E_PAR_ERROR;
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}
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}
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num_transfers = (count / 2048) + 1;
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sectors_left = count;
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sectors_left = count;
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current_sector = starting_sector;
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current_sector = starting_sector;
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if (!sd_card_type_block) {
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if (!sd_card_type_block) {
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@ -405,7 +403,7 @@ sc64_sd_err_t sc64_sd_read_sectors_dma(uint32_t starting_sector, size_t count, u
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}
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}
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current_address = address;
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current_address = address;
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for (size_t i = 0; i < num_transfers; i++) {
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do {
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num_blocks = (sectors_left > 2048) ? 2048 : sectors_left;
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num_blocks = (sectors_left > 2048) ? 2048 : sectors_left;
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platform_pi_io_write(&SC64_SD->DMA_ADDR, SC64_SD_DMA_BANK_ADDR(bank, current_address));
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platform_pi_io_write(&SC64_SD->DMA_ADDR, SC64_SD_DMA_BANK_ADDR(bank, current_address));
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@ -450,9 +448,10 @@ sc64_sd_err_t sc64_sd_read_sectors_dma(uint32_t starting_sector, size_t count, u
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while (platform_pi_io_read(&SC64_SD->DMA_SCR) & SC64_SD_DMA_SCR_BUSY);
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while (platform_pi_io_read(&SC64_SD->DMA_SCR) & SC64_SD_DMA_SCR_BUSY);
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current_sector += sd_card_type_block ? 1 : SD_BLOCK_SIZE;
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sectors_left -= num_blocks;
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current_sector += num_blocks * (sd_card_type_block ? 1 : SD_BLOCK_SIZE);
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current_address += num_blocks * SD_BLOCK_SIZE;
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current_address += num_blocks * SD_BLOCK_SIZE;
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}
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} while (sectors_left > 0);
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return E_OK;
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return E_OK;
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}
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}
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