mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-25 15:16:53 +01:00
[SC64][SW] Minor formatting and spelling fixes
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parent
f6b94aec97
commit
cff730cafc
16
sw/cic/cic.c
16
sw/cic/cic.c
@ -60,7 +60,7 @@ typedef struct {
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#define CIC_TIMEOUT_SOFT_RESET CIC_TIMER_MS_TO_TICKS(500)
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#define CIC_TIMEOUT_SOFT_RESET CIC_TIMER_MS_TO_TICKS(500)
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typedef enum {
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typedef enum {
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CIC_STEP_UNINITIALIZED = 0,
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CIC_STEP_UNAVAILABLE = 0,
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CIC_STEP_POWER_OFF = 1,
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CIC_STEP_POWER_OFF = 1,
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CIC_STEP_INIT = 2,
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CIC_STEP_INIT = 2,
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CIC_STEP_ID = 3,
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CIC_STEP_ID = 3,
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@ -94,11 +94,9 @@ static uint8_t cic_ram[32];
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static uint8_t cic_x105_ram[30];
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static uint8_t cic_x105_ram[30];
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static const uint8_t cic_ram_init[2][16] = {{
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static const uint8_t cic_ram_init[2][16] = {{
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0xE0, 0x9A, 0x18, 0x5A, 0x13, 0xE1, 0x0D, 0xEC,
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0xE0, 0x9A, 0x18, 0x5A, 0x13, 0xE1, 0x0D, 0xEC, 0x0B, 0x14, 0xF8, 0xB5, 0x7C, 0xD6, 0x1E, 0x98
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0x0B, 0x14, 0xF8, 0xB5, 0x7C, 0xD6, 0x1E, 0x98
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}, {
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}, {
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0xE0, 0x4F, 0x51, 0x21, 0x71, 0x98, 0x57, 0x5A,
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0xE0, 0x4F, 0x51, 0x21, 0x71, 0x98, 0x57, 0x5A, 0x0B, 0x12, 0x3F, 0x82, 0x71, 0x98, 0x11, 0x5C
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0x0B, 0x12, 0x3F, 0x82, 0x71, 0x98, 0x11, 0x5C
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}};
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}};
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@ -246,10 +244,10 @@ static void cic_write_checksum (void) {
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}
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}
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static void cic_init_ram (void) {
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static void cic_init_ram (void) {
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for (int i = 0; i < 32; i += 2) {
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for (int i = 0; i < 16; i++) {
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uint8_t value = cic_ram_init[config.cic_region ? 1 : 0][i / 2];
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uint8_t value = cic_ram_init[config.cic_region ? 1 : 0][i];
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cic_ram[i] = ((value >> 4) & 0x0F);
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cic_ram[(i * 2)] = ((value >> 4) & 0x0F);
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cic_ram[i + 1] = (value & 0x0F);
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cic_ram[(i * 2) + 1] = (value & 0x0F);
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}
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}
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cic_ram[0x01] = cic_read_nibble();
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cic_ram[0x01] = cic_read_nibble();
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cic_ram[0x11] = cic_read_nibble();
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cic_ram[0x11] = cic_read_nibble();
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@ -60,7 +60,7 @@ static void hw_timeout_start (void) {
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TIM1->CR1 |= TIM_CR1_CEN;
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TIM1->CR1 |= TIM_CR1_CEN;
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}
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}
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static bool hw_timeout_occured (uint32_t timeout_us) {
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static bool hw_timeout_elapsed (uint32_t timeout_us) {
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uint16_t count = TIM1->CNT;
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uint16_t count = TIM1->CNT;
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uint32_t adjusted_timeout = ((timeout_us + (TIMEOUT_US_PER_TICK - 1)) / TIMEOUT_US_PER_TICK);
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uint32_t adjusted_timeout = ((timeout_us + (TIMEOUT_US_PER_TICK - 1)) / TIMEOUT_US_PER_TICK);
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@ -343,7 +343,7 @@ i2c_err_t hw_i2c_trx (uint8_t address, uint8_t *tx_data, uint8_t tx_length, uint
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hw_timeout_start();
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hw_timeout_start();
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while (I2C1->ISR & I2C_ISR_BUSY) {
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while (I2C1->ISR & I2C_ISR_BUSY) {
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if (hw_timeout_occured(I2C_TIMEOUT_US_BUSY)) {
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if (hw_timeout_elapsed(I2C_TIMEOUT_US_BUSY)) {
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return I2C_ERR_BUSY;
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return I2C_ERR_BUSY;
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}
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}
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}
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}
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@ -375,7 +375,7 @@ i2c_err_t hw_i2c_trx (uint8_t address, uint8_t *tx_data, uint8_t tx_length, uint
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return I2C_ERR_NACK;
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return I2C_ERR_NACK;
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}
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}
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if (hw_timeout_occured(tx_timeout)) {
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if (hw_timeout_elapsed(tx_timeout)) {
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return I2C_ERR_TIMEOUT;
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return I2C_ERR_TIMEOUT;
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}
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}
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}
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}
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@ -385,7 +385,7 @@ i2c_err_t hw_i2c_trx (uint8_t address, uint8_t *tx_data, uint8_t tx_length, uint
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}
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}
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while (!(I2C1->ISR & I2C_ISR_TC)) {
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while (!(I2C1->ISR & I2C_ISR_TC)) {
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if (hw_timeout_occured(tx_timeout)) {
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if (hw_timeout_elapsed(tx_timeout)) {
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return I2C_ERR_TIMEOUT;
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return I2C_ERR_TIMEOUT;
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}
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}
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}
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}
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@ -414,7 +414,7 @@ i2c_err_t hw_i2c_trx (uint8_t address, uint8_t *tx_data, uint8_t tx_length, uint
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left -= 1;
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left -= 1;
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}
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}
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if (hw_timeout_occured(rx_timeout)) {
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if (hw_timeout_elapsed(rx_timeout)) {
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return I2C_ERR_TIMEOUT;
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return I2C_ERR_TIMEOUT;
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}
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}
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}
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}
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@ -716,9 +716,9 @@ fn handle_info_command(connection: Connection) -> Result<(), sc64::Error> {
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let (major, minor, revision) = sc64.check_firmware_version()?;
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let (major, minor, revision) = sc64.check_firmware_version()?;
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let state = sc64.get_device_state()?;
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let state = sc64.get_device_state()?;
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let datetime = state.datetime.format("%Y-%m-%d %H:%M:%S %Z");
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let datetime = state.datetime.format("%Y-%m-%d %H:%M:%S");
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println!("{}", "SC64 information and current state:".bold());
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println!("{}", "SummerCart64 state information:".bold());
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println!(" Firmware version: v{}.{}.{}", major, minor, revision);
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println!(" Firmware version: v{}.{}.{}", major, minor, revision);
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println!(" RTC datetime: {}", datetime);
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println!(" RTC datetime: {}", datetime);
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println!(" Boot mode: {}", state.boot_mode);
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println!(" Boot mode: {}", state.boot_mode);
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@ -737,7 +737,10 @@ fn handle_info_command(connection: Connection) -> Result<(), sc64::Error> {
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println!(" Button state: {}", state.button_state);
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println!(" Button state: {}", state.button_state);
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println!(" LED blink: {}", state.led_enable);
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println!(" LED blink: {}", state.led_enable);
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println!(" IS-Viewer 64 offset: 0x{:08X}", state.isv_address);
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println!(" IS-Viewer 64 offset: 0x{:08X}", state.isv_address);
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println!(" FPGA debug data: {}", state.fpga_debug_data);
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println!("{}", "SummerCart64 diagnostic information:".bold());
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println!(" Last PI address: 0x{:08X}", state.fpga_debug_data.last_pi_address);
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println!(" PI FIFO flags: {}", state.fpga_debug_data.pi_fifo_flags);
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println!(" Current CIC step: {}", state.fpga_debug_data.cic_step);
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println!(" Diagnostic data: {}", state.diagnostic_data);
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println!(" Diagnostic data: {}", state.diagnostic_data);
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Ok(())
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Ok(())
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@ -783,7 +783,7 @@ impl TryFrom<u32> for UpdateStatus {
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}
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}
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pub enum CicStep {
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pub enum CicStep {
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Uninitialized,
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Unavailable,
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PowerOff,
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PowerOff,
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Init,
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Init,
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Id,
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Id,
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@ -804,7 +804,7 @@ pub enum CicStep {
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impl Display for CicStep {
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impl Display for CicStep {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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f.write_str(match self {
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f.write_str(match self {
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Self::Uninitialized => "Uninitialized",
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Self::Unavailable => "Unavailable",
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Self::PowerOff => "Power off",
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Self::PowerOff => "Power off",
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Self::Init => "Initialize",
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Self::Init => "Initialize",
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Self::Id => "ID",
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Self::Id => "ID",
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@ -828,7 +828,7 @@ impl TryFrom<u8> for CicStep {
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type Error = Error;
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type Error = Error;
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fn try_from(value: u8) -> Result<Self, Self::Error> {
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fn try_from(value: u8) -> Result<Self, Self::Error> {
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Ok(match value {
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Ok(match value {
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0 => Self::Uninitialized,
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0 => Self::Unavailable,
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1 => Self::PowerOff,
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1 => Self::PowerOff,
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2 => Self::Init,
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2 => Self::Init,
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3 => Self::Id,
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3 => Self::Id,
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@ -843,17 +843,51 @@ impl TryFrom<u8> for CicStep {
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12 => Self::Die64DD,
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12 => Self::Die64DD,
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13 => Self::DieInvalidRegion,
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13 => Self::DieInvalidRegion,
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14 => Self::DieCommand,
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14 => Self::DieCommand,
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_ => Self::Unknown
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_ => Self::Unknown,
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})
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}
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}
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pub struct PiFifoFlags {
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pub read_fifo_wait: bool,
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pub read_fifo_failure: bool,
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pub write_fifo_wait: bool,
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pub write_fifo_failure: bool,
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}
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impl Display for PiFifoFlags {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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let mapping = vec![
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(self.read_fifo_wait, "Read wait"),
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(self.read_fifo_failure, "Read failure"),
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(self.write_fifo_wait, "Write wait"),
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(self.write_fifo_failure, "Write failure"),
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];
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let filtered: Vec<&str> = mapping.into_iter().filter(|x| x.0).map(|x| x.1).collect();
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if filtered.len() > 0 {
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f.write_str(filtered.join(", ").as_str())?;
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} else {
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f.write_str("None")?;
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}
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Ok(())
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}
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}
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impl TryFrom<u8> for PiFifoFlags {
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type Error = Error;
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fn try_from(value: u8) -> Result<Self, Self::Error> {
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Ok(PiFifoFlags {
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read_fifo_wait: (value & (1 << 0)) != 0,
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read_fifo_failure: (value & (1 << 1)) != 0,
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write_fifo_wait: (value & (1 << 2)) != 0,
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write_fifo_failure: (value & (1 << 3)) != 0,
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})
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})
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}
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}
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}
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}
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pub struct FpgaDebugData {
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pub struct FpgaDebugData {
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pub last_pi_address: u32,
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pub last_pi_address: u32,
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pub read_fifo_wait: bool,
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pub pi_fifo_flags: PiFifoFlags,
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pub read_fifo_failure: bool,
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pub write_fifo_wait: bool,
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pub write_fifo_failure: bool,
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pub cic_step: CicStep,
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pub cic_step: CicStep,
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}
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}
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@ -865,39 +899,12 @@ impl TryFrom<Vec<u8>> for FpgaDebugData {
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}
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}
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Ok(FpgaDebugData {
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Ok(FpgaDebugData {
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last_pi_address: u32::from_be_bytes(value[0..4].try_into().unwrap()),
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last_pi_address: u32::from_be_bytes(value[0..4].try_into().unwrap()),
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read_fifo_wait: (value[7] & (1 << 0)) != 0,
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pi_fifo_flags: (value[7] & 0x0F).try_into().unwrap(),
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read_fifo_failure: (value[7] & (1 << 1)) != 0,
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cic_step: ((value[7] >> 4) & 0x0F).try_into().unwrap(),
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write_fifo_wait: (value[7] & (1 << 2)) != 0,
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write_fifo_failure: (value[7] & (1 << 3)) != 0,
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cic_step: ((value[7] >> 4) & 0xF).try_into().unwrap(),
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})
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})
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}
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}
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}
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}
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impl Display for FpgaDebugData {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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f.write_fmt(format_args!(
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"Last PI address: 0x{:08X}",
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self.last_pi_address
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))?;
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if self.read_fifo_wait {
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f.write_str(" RW")?;
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}
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if self.read_fifo_failure {
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f.write_str(" RF")?;
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}
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if self.write_fifo_wait {
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f.write_str(" WW")?;
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}
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if self.write_fifo_failure {
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f.write_str(" WF")?;
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}
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f.write_str(" / ")?;
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f.write_fmt(format_args!("CIC step: {}", self.cic_step))?;
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Ok(())
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}
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}
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pub struct DiagnosticDataV0 {
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pub struct DiagnosticDataV0 {
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pub cic: u32,
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pub cic: u32,
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pub rtc: u32,
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pub rtc: u32,
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