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[SC64][SW] Minor formatting and spelling fixes

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This commit is contained in:
Mateusz Faderewski 2024-04-10 21:32:17 +02:00
parent f6b94aec97
commit cff730cafc
4 changed files with 62 additions and 54 deletions
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16
sw/cic/cic.c
View File

@ -60,7 +60,7 @@ typedef struct {
#define CIC_TIMEOUT_SOFT_RESET CIC_TIMER_MS_TO_TICKS(500)
typedef enum {
CIC_STEP_UNINITIALIZED = 0,
CIC_STEP_UNAVAILABLE = 0,
CIC_STEP_POWER_OFF = 1,
CIC_STEP_INIT = 2,
CIC_STEP_ID = 3,
@ -94,11 +94,9 @@ static uint8_t cic_ram[32];
static uint8_t cic_x105_ram[30];
static const uint8_t cic_ram_init[2][16] = {{
0xE0, 0x9A, 0x18, 0x5A, 0x13, 0xE1, 0x0D, 0xEC,
0x0B, 0x14, 0xF8, 0xB5, 0x7C, 0xD6, 0x1E, 0x98
0xE0, 0x9A, 0x18, 0x5A, 0x13, 0xE1, 0x0D, 0xEC, 0x0B, 0x14, 0xF8, 0xB5, 0x7C, 0xD6, 0x1E, 0x98
}, {
0xE0, 0x4F, 0x51, 0x21, 0x71, 0x98, 0x57, 0x5A,
0x0B, 0x12, 0x3F, 0x82, 0x71, 0x98, 0x11, 0x5C
0xE0, 0x4F, 0x51, 0x21, 0x71, 0x98, 0x57, 0x5A, 0x0B, 0x12, 0x3F, 0x82, 0x71, 0x98, 0x11, 0x5C
}};
@ -246,10 +244,10 @@ static void cic_write_checksum (void) {
}
static void cic_init_ram (void) {
for (int i = 0; i < 32; i += 2) {
uint8_t value = cic_ram_init[config.cic_region ? 1 : 0][i / 2];
cic_ram[i] = ((value >> 4) & 0x0F);
cic_ram[i + 1] = (value & 0x0F);
for (int i = 0; i < 16; i++) {
uint8_t value = cic_ram_init[config.cic_region ? 1 : 0][i];
cic_ram[(i * 2)] = ((value >> 4) & 0x0F);
cic_ram[(i * 2) + 1] = (value & 0x0F);
}
cic_ram[0x01] = cic_read_nibble();
cic_ram[0x11] = cic_read_nibble();

10
sw/controller/src/hw.c
View File

@ -60,7 +60,7 @@ static void hw_timeout_start (void) {
TIM1->CR1 |= TIM_CR1_CEN;
}
static bool hw_timeout_occured (uint32_t timeout_us) {
static bool hw_timeout_elapsed (uint32_t timeout_us) {
uint16_t count = TIM1->CNT;
uint32_t adjusted_timeout = ((timeout_us + (TIMEOUT_US_PER_TICK - 1)) / TIMEOUT_US_PER_TICK);
@ -343,7 +343,7 @@ i2c_err_t hw_i2c_trx (uint8_t address, uint8_t *tx_data, uint8_t tx_length, uint
hw_timeout_start();
while (I2C1->ISR & I2C_ISR_BUSY) {
if (hw_timeout_occured(I2C_TIMEOUT_US_BUSY)) {
if (hw_timeout_elapsed(I2C_TIMEOUT_US_BUSY)) {
return I2C_ERR_BUSY;
}
}
@ -375,7 +375,7 @@ i2c_err_t hw_i2c_trx (uint8_t address, uint8_t *tx_data, uint8_t tx_length, uint
return I2C_ERR_NACK;
}
if (hw_timeout_occured(tx_timeout)) {
if (hw_timeout_elapsed(tx_timeout)) {
return I2C_ERR_TIMEOUT;
}
}
@ -385,7 +385,7 @@ i2c_err_t hw_i2c_trx (uint8_t address, uint8_t *tx_data, uint8_t tx_length, uint
}
while (!(I2C1->ISR & I2C_ISR_TC)) {
if (hw_timeout_occured(tx_timeout)) {
if (hw_timeout_elapsed(tx_timeout)) {
return I2C_ERR_TIMEOUT;
}
}
@ -414,7 +414,7 @@ i2c_err_t hw_i2c_trx (uint8_t address, uint8_t *tx_data, uint8_t tx_length, uint
left -= 1;
}
if (hw_timeout_occured(rx_timeout)) {
if (hw_timeout_elapsed(rx_timeout)) {
return I2C_ERR_TIMEOUT;
}
}

9
sw/deployer/src/main.rs
View File

@ -716,9 +716,9 @@ fn handle_info_command(connection: Connection) -> Result<(), sc64::Error> {
let (major, minor, revision) = sc64.check_firmware_version()?;
let state = sc64.get_device_state()?;
let datetime = state.datetime.format("%Y-%m-%d %H:%M:%S %Z");
let datetime = state.datetime.format("%Y-%m-%d %H:%M:%S");
println!("{}", "SC64 information and current state:".bold());
println!("{}", "SummerCart64 state information:".bold());
println!(" Firmware version: v{}.{}.{}", major, minor, revision);
println!(" RTC datetime: {}", datetime);
println!(" Boot mode: {}", state.boot_mode);
@ -737,7 +737,10 @@ fn handle_info_command(connection: Connection) -> Result<(), sc64::Error> {
println!(" Button state: {}", state.button_state);
println!(" LED blink: {}", state.led_enable);
println!(" IS-Viewer 64 offset: 0x{:08X}", state.isv_address);
println!(" FPGA debug data: {}", state.fpga_debug_data);
println!("{}", "SummerCart64 diagnostic information:".bold());
println!(" Last PI address: 0x{:08X}", state.fpga_debug_data.last_pi_address);
println!(" PI FIFO flags: {}", state.fpga_debug_data.pi_fifo_flags);
println!(" Current CIC step: {}", state.fpga_debug_data.cic_step);
println!(" Diagnostic data: {}", state.diagnostic_data);
Ok(())

81
sw/deployer/src/sc64/types.rs
View File

@ -783,7 +783,7 @@ impl TryFrom<u32> for UpdateStatus {
}
pub enum CicStep {
Uninitialized,
Unavailable,
PowerOff,
Init,
Id,
@ -804,7 +804,7 @@ pub enum CicStep {
impl Display for CicStep {
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
f.write_str(match self {
Self::Uninitialized => "Uninitialized",
Self::Unavailable => "Unavailable",
Self::PowerOff => "Power off",
Self::Init => "Initialize",
Self::Id => "ID",
@ -828,7 +828,7 @@ impl TryFrom<u8> for CicStep {
type Error = Error;
fn try_from(value: u8) -> Result<Self, Self::Error> {
Ok(match value {
0 => Self::Uninitialized,
0 => Self::Unavailable,
1 => Self::PowerOff,
2 => Self::Init,
3 => Self::Id,
@ -843,17 +843,51 @@ impl TryFrom<u8> for CicStep {
12 => Self::Die64DD,
13 => Self::DieInvalidRegion,
14 => Self::DieCommand,
_ => Self::Unknown
_ => Self::Unknown,
})
}
}
pub struct PiFifoFlags {
pub read_fifo_wait: bool,
pub read_fifo_failure: bool,
pub write_fifo_wait: bool,
pub write_fifo_failure: bool,
}
impl Display for PiFifoFlags {
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
let mapping = vec![
(self.read_fifo_wait, "Read wait"),
(self.read_fifo_failure, "Read failure"),
(self.write_fifo_wait, "Write wait"),
(self.write_fifo_failure, "Write failure"),
];
let filtered: Vec<&str> = mapping.into_iter().filter(|x| x.0).map(|x| x.1).collect();
if filtered.len() > 0 {
f.write_str(filtered.join(", ").as_str())?;
} else {
f.write_str("None")?;
}
Ok(())
}
}
impl TryFrom<u8> for PiFifoFlags {
type Error = Error;
fn try_from(value: u8) -> Result<Self, Self::Error> {
Ok(PiFifoFlags {
read_fifo_wait: (value & (1 << 0)) != 0,
read_fifo_failure: (value & (1 << 1)) != 0,
write_fifo_wait: (value & (1 << 2)) != 0,
write_fifo_failure: (value & (1 << 3)) != 0,
})
}
}
pub struct FpgaDebugData {
pub last_pi_address: u32,
pub read_fifo_wait: bool,
pub read_fifo_failure: bool,
pub write_fifo_wait: bool,
pub write_fifo_failure: bool,
pub pi_fifo_flags: PiFifoFlags,
pub cic_step: CicStep,
}
@ -865,39 +899,12 @@ impl TryFrom<Vec<u8>> for FpgaDebugData {
}
Ok(FpgaDebugData {
last_pi_address: u32::from_be_bytes(value[0..4].try_into().unwrap()),
read_fifo_wait: (value[7] & (1 << 0)) != 0,
read_fifo_failure: (value[7] & (1 << 1)) != 0,
write_fifo_wait: (value[7] & (1 << 2)) != 0,
write_fifo_failure: (value[7] & (1 << 3)) != 0,
cic_step: ((value[7] >> 4) & 0xF).try_into().unwrap(),
pi_fifo_flags: (value[7] & 0x0F).try_into().unwrap(),
cic_step: ((value[7] >> 4) & 0x0F).try_into().unwrap(),
})
}
}
impl Display for FpgaDebugData {
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
f.write_fmt(format_args!(
"Last PI address: 0x{:08X}",
self.last_pi_address
))?;
if self.read_fifo_wait {
f.write_str(" RW")?;
}
if self.read_fifo_failure {
f.write_str(" RF")?;
}
if self.write_fifo_wait {
f.write_str(" WW")?;
}
if self.write_fifo_failure {
f.write_str(" WF")?;
}
f.write_str(" / ")?;
f.write_fmt(format_args!("CIC step: {}", self.cic_step))?;
Ok(())
}
}
pub struct DiagnosticDataV0 {
pub cic: u32,
pub rtc: u32,