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https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-25 15:16:53 +01:00
make room for saves
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parent
4b888d0f71
commit
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@ -829,9 +829,9 @@ if __name__ == "__main__":
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print(f"Setting 64DD disk state to [Changed]")
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sc64.set_dd_disk_state("changed" if disk_file else "ejected")
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if (is_viewer_enabled):
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print(f"Setting IS-Viewer64 emulation to [Enabled]")
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print(f"Setting IS-Viewer 64 emulation to [Enabled]")
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sc64.debug_init(sd_file, disk_file, is_viewer_enabled)
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sc64.debug_loop(is_viewer_enabled)
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sc64.debug_loop()
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except SC64Exception as e:
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print(f"Error: {e}")
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@ -12,10 +12,12 @@
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#define SAVE_SIZE_FLASHRAM (128 * 1024)
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#define SAVE_SIZE_SRAM_BANKED (3 * 32 * 1024)
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#define ISV_SIZE (64 * 1024)
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#define SAVE_OFFSET_PKST2 (0x01608000UL)
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#define DEFAULT_SAVE_OFFSET (0x03FE0000UL)
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#define DEFAULT_DDIPL_OFFSET (0x03BE0000UL)
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#define DEFAULT_SAVE_OFFSET (0x03FD0000UL)
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#define DEFAULT_DDIPL_OFFSET (0x03BD0000UL)
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enum cfg_id {
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@ -85,23 +87,23 @@ static void set_save_type (enum save_type save_type) {
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case SAVE_TYPE_NONE:
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break;
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case SAVE_TYPE_EEPROM_4K:
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save_offset = SDRAM_SIZE - SAVE_SIZE_EEPROM_4K;
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save_offset = SDRAM_SIZE - SAVE_SIZE_EEPROM_4K - ISV_SIZE;
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joybus_set_eeprom(EEPROM_4K);
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break;
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case SAVE_TYPE_EEPROM_16K:
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save_offset = SDRAM_SIZE - SAVE_SIZE_EEPROM_16K;
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save_offset = SDRAM_SIZE - SAVE_SIZE_EEPROM_16K - ISV_SIZE;
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joybus_set_eeprom(EEPROM_16K);
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break;
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case SAVE_TYPE_SRAM:
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save_offset = SDRAM_SIZE - SAVE_SIZE_SRAM;
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save_offset = SDRAM_SIZE - SAVE_SIZE_SRAM - ISV_SIZE;
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change_scr_bits(CFG_SCR_SRAM_EN, true);
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break;
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case SAVE_TYPE_FLASHRAM:
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save_offset = SDRAM_SIZE - SAVE_SIZE_FLASHRAM;
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save_offset = SDRAM_SIZE - SAVE_SIZE_FLASHRAM - ISV_SIZE;
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change_scr_bits(CFG_SCR_FLASHRAM_EN, true);
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break;
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case SAVE_TYPE_SRAM_BANKED:
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save_offset = SDRAM_SIZE - SAVE_SIZE_SRAM_BANKED;
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save_offset = SDRAM_SIZE - SAVE_SIZE_SRAM_BANKED - ISV_SIZE;
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change_scr_bits(CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_EN, true);
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break;
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case SAVE_TYPE_FLASHRAM_PKST2:
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@ -5,7 +5,7 @@
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#define DD_USER_SECTORS_PER_BLOCK (85)
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#define DD_BUFFERS_OFFSET (SDRAM_BASE + 0x03BD0000UL)
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#define DD_BUFFERS_OFFSET (SDRAM_BASE + 0x03BC0000UL)
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#define DD_THB_TABLE_OFFSET (DD_BUFFERS_OFFSET + 0x0000)
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#define DD_USB_BUFFER_OFFSET (DD_BUFFERS_OFFSET + 0x5000)
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#define DD_BLOCK_BUFFER_OFFSET (DD_USB_BUFFER_OFFSET + 0x10)
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