From e1ecb0cac305025f602dc9e79dcd999712fd9e5e Mon Sep 17 00:00:00 2001 From: Mateusz Faderewski Date: Wed, 17 Jan 2024 05:16:00 +0100 Subject: [PATCH] flashram cleanup --- fw/rtl/mcu/mcu_top.sv | 2 +- fw/rtl/n64/n64_flashram.sv | 11 +++--- fw/rtl/n64/n64_scb.sv | 6 +-- sw/controller/src/flashram.c | 74 +++++++++++++++++++----------------- sw/tools/primer.py | 2 +- 5 files changed, 50 insertions(+), 45 deletions(-) diff --git a/fw/rtl/mcu/mcu_top.sv b/fw/rtl/mcu/mcu_top.sv index 9996b23..683b252 100644 --- a/fw/rtl/mcu/mcu_top.sv +++ b/fw/rtl/mcu/mcu_top.sv @@ -474,7 +474,7 @@ module mcu_top ( 18'd0, n64_scb.flashram_write_or_erase, n64_scb.flashram_sector_or_all, - n64_scb.flashram_sector, + n64_scb.flashram_page, n64_scb.flashram_pending, 1'b0 }; diff --git a/fw/rtl/n64/n64_flashram.sv b/fw/rtl/n64/n64_flashram.sv index bbc9464..d23f566 100644 --- a/fw/rtl/n64/n64_flashram.sv +++ b/fw/rtl/n64/n64_flashram.sv @@ -8,7 +8,7 @@ module n64_flashram ( ); localparam [31:0] FLASH_TYPE_ID = 32'h1111_8001; - localparam [31:0] FLASH_MODEL_ID = 32'h00C2_001D; + localparam [31:0] FLASH_MODEL_ID = 32'h0032_00F1; typedef enum bit [7:0] { CMD_STATUS_MODE = 8'hD2, @@ -97,14 +97,14 @@ module n64_flashram ( CMD_ERASE_SECTOR: begin state <= STATE_STATUS; erase_enabled <= 1'b1; - n64_scb.flashram_sector <= reg_bus.wdata[9:0]; + n64_scb.flashram_page <= reg_bus.wdata[9:0]; n64_scb.flashram_sector_or_all <= 1'b0; end CMD_ERASE_CHIP: begin state <= STATE_STATUS; erase_enabled <= 1'b1; - n64_scb.flashram_sector <= 10'd0; + n64_scb.flashram_page <= 10'd0; n64_scb.flashram_sector_or_all <= 1'b1; end @@ -126,7 +126,7 @@ module n64_flashram ( state <= STATE_STATUS; status[WRITE_BUSY] <= 1'b1; status[WRITE_DONE] <= 1'b0; - n64_scb.flashram_sector <= reg_bus.wdata[9:0]; + n64_scb.flashram_page <= reg_bus.wdata[9:0]; n64_scb.flashram_pending <= 1'b1; n64_scb.flashram_write_or_erase <= 1'b0; n64_scb.flashram_sector_or_all <= 1'b0; @@ -135,8 +135,7 @@ module n64_flashram ( end end else begin if (reg_bus.address[1] && state != STATE_BUFFER) begin - status[ERASE_BUSY] <= reg_bus.wdata[ERASE_BUSY]; - status[WRITE_BUSY] <= reg_bus.wdata[WRITE_BUSY]; + status <= reg_bus.wdata[3:0]; end end end diff --git a/fw/rtl/n64/n64_scb.sv b/fw/rtl/n64/n64_scb.sv index b2ba869..f1afa4a 100644 --- a/fw/rtl/n64/n64_scb.sv +++ b/fw/rtl/n64/n64_scb.sv @@ -22,7 +22,7 @@ interface n64_scb (); logic flashram_pending; logic flashram_done; - logic [9:0] flashram_sector; + logic [9:0] flashram_page; logic flashram_sector_or_all; logic flashram_write_or_erase; logic flashram_read_mode; @@ -84,7 +84,7 @@ interface n64_scb (); input flashram_pending, output flashram_done, - input flashram_sector, + input flashram_page, input flashram_sector_or_all, input flashram_write_or_erase, @@ -143,7 +143,7 @@ interface n64_scb (); modport flashram ( output flashram_pending, input flashram_done, - output flashram_sector, + output flashram_page, output flashram_sector_or_all, output flashram_write_or_erase, diff --git a/sw/controller/src/flashram.c b/sw/controller/src/flashram.c index 50acd79..60bcb91 100644 --- a/sw/controller/src/flashram.c +++ b/sw/controller/src/flashram.c @@ -9,15 +9,15 @@ #define FLASHRAM_BUFFER_ADDRESS (0x05002900UL) -enum operation { +typedef enum { OP_NONE, OP_ERASE_ALL, OP_ERASE_SECTOR, OP_WRITE_PAGE -}; +} flashram_op_t; -static enum operation flashram_operation_type (uint32_t scr) { +static flashram_op_t flashram_operation_type (uint32_t scr) { if (!(scr & FLASHRAM_SCR_PENDING)) { return OP_NONE; } @@ -43,38 +43,44 @@ void flashram_init (void) { void flashram_process (void) { uint32_t scr = fpga_reg_get(REG_FLASHRAM_SCR); - enum operation op = flashram_operation_type(scr); - uint8_t page_buffer[FLASHRAM_PAGE_SIZE]; - uint8_t write_buffer[FLASHRAM_PAGE_SIZE]; - uint32_t address = FLASHRAM_ADDRESS; - uint32_t erase_size = (op == OP_ERASE_SECTOR) ? FLASHRAM_SECTOR_SIZE : FLASHRAM_SIZE; - uint32_t page = (op != OP_ERASE_ALL) ? ((scr & FLASHRAM_SCR_PAGE_MASK) >> FLASHRAM_SCR_PAGE_BIT) : 0; - address += page * FLASHRAM_PAGE_SIZE; - switch (op) { - case OP_ERASE_ALL: - case OP_ERASE_SECTOR: - for (int i = 0; i < FLASHRAM_PAGE_SIZE; i++) { - write_buffer[i] = 0xFF; - } - for (int i = 0; i < erase_size; i += FLASHRAM_PAGE_SIZE) { - fpga_mem_write(address + i, FLASHRAM_PAGE_SIZE, write_buffer); - } - fpga_reg_set(REG_FLASHRAM_SCR, FLASHRAM_SCR_DONE); - break; + flashram_op_t op = flashram_operation_type(scr); - case OP_WRITE_PAGE: - fpga_mem_read(FLASHRAM_BUFFER_ADDRESS, FLASHRAM_PAGE_SIZE, page_buffer); - fpga_mem_read(address, FLASHRAM_PAGE_SIZE, write_buffer); - for (int i = 0; i < FLASHRAM_PAGE_SIZE; i++) { - write_buffer[i] &= page_buffer[i]; - } - fpga_mem_write(address, FLASHRAM_PAGE_SIZE, write_buffer); - fpga_reg_set(REG_FLASHRAM_SCR, FLASHRAM_SCR_DONE); - break; - - case OP_NONE: - default: - break; + if (op == OP_NONE) { + return; } + + uint8_t write_buffer[FLASHRAM_PAGE_SIZE]; + + uint32_t page = ((scr & FLASHRAM_SCR_PAGE_MASK) >> FLASHRAM_SCR_PAGE_BIT); + + if (op == OP_WRITE_PAGE) { + uint8_t page_buffer[FLASHRAM_PAGE_SIZE]; + + uint32_t address = (FLASHRAM_ADDRESS + (page * FLASHRAM_PAGE_SIZE)); + + fpga_mem_read(FLASHRAM_BUFFER_ADDRESS, FLASHRAM_PAGE_SIZE, page_buffer); + fpga_mem_read(address, FLASHRAM_PAGE_SIZE, write_buffer); + + for (int i = 0; i < FLASHRAM_PAGE_SIZE; i++) { + write_buffer[i] &= page_buffer[i]; + } + + fpga_mem_write(address, FLASHRAM_PAGE_SIZE, write_buffer); + } else if ((op == OP_ERASE_SECTOR) || (op == OP_ERASE_ALL)) { + for (int i = 0; i < FLASHRAM_PAGE_SIZE; i++) { + write_buffer[i] = 0xFF; + } + + page &= ~((FLASHRAM_SECTOR_SIZE / FLASHRAM_PAGE_SIZE) - 1); + + uint32_t erase_size = (op == OP_ERASE_ALL) ? FLASHRAM_SIZE : FLASHRAM_SECTOR_SIZE; + uint32_t address = (FLASHRAM_ADDRESS + (page * FLASHRAM_PAGE_SIZE)); + + for (uint32_t offset = 0; offset < erase_size; offset += FLASHRAM_PAGE_SIZE) { + fpga_mem_write(address + offset, FLASHRAM_PAGE_SIZE, write_buffer); + } + } + + fpga_reg_set(REG_FLASHRAM_SCR, FLASHRAM_SCR_DONE); } diff --git a/sw/tools/primer.py b/sw/tools/primer.py index 6bcb7e3..4f24016 100644 --- a/sw/tools/primer.py +++ b/sw/tools/primer.py @@ -679,7 +679,7 @@ if __name__ == '__main__': sc64_bring_up = SC64BringUp(progress=utils.progress) Utils.log() - Utils.info('[ Welcome to SummerCart64 flashcart board bring-up! ]') + Utils.info('[ Welcome to the SummerCart64 flashcart board bring-up! ]') Utils.log() Utils.log(f'Serial port: {port}')