From e89529275a4277dbf7adc9c17a5f502bc71a3569 Mon Sep 17 00:00:00 2001
From: Mateusz Faderewski <sc@mateuszfaderewski.pl>
Date: Sun, 7 Jul 2024 14:42:39 +0200
Subject: [PATCH] small cleanup

---
 fw/rtl/memory/memory_sdram.sv       |  2 +-
 fw/tests/mocks/fifo_bus_mock.sv     |  1 +
 fw/tests/mocks/memory_sdram_mock.sv | 32 ++++++++++++++---------------
 3 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/fw/rtl/memory/memory_sdram.sv b/fw/rtl/memory/memory_sdram.sv
index cbd0ffd..f112241 100644
--- a/fw/rtl/memory/memory_sdram.sv
+++ b/fw/rtl/memory/memory_sdram.sv
@@ -95,7 +95,7 @@ module memory_sdram (
             CMD_MRS: begin
                 {sdram_ba, sdram_a} <= {
                     2'b00,          // [BA1:BA0] Reserved = 0
-                    3'b00,          // [A12:A10] Reserved = 0
+                    3'b000,         // [A12:A10] Reserved = 0
                     1'b0,           // [A9] Write Burst Mode = Programmed Burst Length
                     2'b00,          // [A8:A7] Operating Mode = Standard Operation
                     CAS_LATENCY,    // [A6:A4] Latency Mode = 2
diff --git a/fw/tests/mocks/fifo_bus_mock.sv b/fw/tests/mocks/fifo_bus_mock.sv
index 17828de..bfa2a1c 100644
--- a/fw/tests/mocks/fifo_bus_mock.sv
+++ b/fw/tests/mocks/fifo_bus_mock.sv
@@ -16,6 +16,7 @@ module fifo_bus_mock #(
 
     localparam int PTR_BITS = $clog2(DEPTH);
 
+
     // RX FIFO mock
 
     logic [7:0] rx_fifo_mem [0:(DEPTH - 1)];
diff --git a/fw/tests/mocks/memory_sdram_mock.sv b/fw/tests/mocks/memory_sdram_mock.sv
index f24a61d..9f5d34a 100644
--- a/fw/tests/mocks/memory_sdram_mock.sv
+++ b/fw/tests/mocks/memory_sdram_mock.sv
@@ -37,26 +37,26 @@ module memory_sdram_mock (
 
     assign sdram_dq = sdram_dq_driven;
 
-    initial begin
-        cas_delay = 2'b00;
-        data_from_sdram = 16'h0102;
-        data_to_sdram = 16'hFFFF;
-    end
-
     always_ff @(posedge clk) begin
-        cas_delay <= {cas_delay[0], 1'b0};
+        if (reset) begin
+            cas_delay <= 2'b00;
+            data_from_sdram <= 16'h0102;
+            data_to_sdram <= 16'hFFFF;
+        end else begin
+            cas_delay <= {cas_delay[0], 1'b0};
 
-        if ({sdram_cs, sdram_ras, sdram_cas, sdram_we} == 4'b0101) begin
-            cas_delay[0] <= 1'b1;
-        end
+            if ({sdram_cs, sdram_ras, sdram_cas, sdram_we} == 4'b0101) begin
+                cas_delay[0] <= 1'b1;
+            end
 
-        if (cas_delay[1]) begin
-            data_from_sdram <= data_from_sdram + 16'h0202;
-        end
+            if (cas_delay[1]) begin
+                data_from_sdram <= data_from_sdram + 16'h0202;
+            end
 
-        if ({sdram_cs, sdram_ras, sdram_cas, sdram_we} == 4'b0100) begin
-            if (!sdram_dqm[0]) data_to_sdram[7:0] <= sdram_dq[7:0];
-            if (!sdram_dqm[1]) data_to_sdram[15:8] <= sdram_dq[15:8];
+            if ({sdram_cs, sdram_ras, sdram_cas, sdram_we} == 4'b0100) begin
+                if (!sdram_dqm[0]) data_to_sdram[7:0] <= sdram_dq[7:0];
+                if (!sdram_dqm[1]) data_to_sdram[15:8] <= sdram_dq[15:8];
+            end
         end
     end