diff --git a/fw/rtl/memory/memory_dma.sv b/fw/rtl/memory/memory_dma.sv
index 7bd529f..cf96555 100644
--- a/fw/rtl/memory/memory_dma.sv
+++ b/fw/rtl/memory/memory_dma.sv
@@ -178,9 +178,8 @@ module memory_dma (
 
     // RX FIFO controller
 
-    typedef enum bit [2:0] {
+    typedef enum bit [1:0] {
         RX_FIFO_BUS_STATE_IDLE,
-        RX_FIFO_BUS_STATE_WAIT,
         RX_FIFO_BUS_STATE_TRANSFER_1,
         RX_FIFO_BUS_STATE_TRANSFER_2,
         RX_FIFO_BUS_STATE_ACK
@@ -191,7 +190,6 @@ module memory_dma (
 
     logic rx_fifo_shift;
     logic rx_fifo_shift_delayed;
-    logic [1:0] rx_fifo_valid;
 
     always_ff @(posedge clk) begin
         if (reset || dma_stop) begin
@@ -211,29 +209,24 @@ module memory_dma (
         case (rx_fifo_bus_state)
             RX_FIFO_BUS_STATE_IDLE: begin
                 if (dma_start && dma_scb.direction) begin
-                    next_rx_fifo_bus_state = RX_FIFO_BUS_STATE_WAIT;
-                end
-            end
-
-            RX_FIFO_BUS_STATE_WAIT: begin
-                if (mem_bus_wdata_end) begin
-                    next_rx_fifo_bus_state = RX_FIFO_BUS_STATE_IDLE;
-                end else if (mem_bus_wdata_empty) begin
                     next_rx_fifo_bus_state = RX_FIFO_BUS_STATE_TRANSFER_1;
                 end
             end
 
             RX_FIFO_BUS_STATE_TRANSFER_1: begin
-                fifo_bus.rx_read = (!fifo_bus.rx_empty && rx_fifo_valid[1]);
-                if (!fifo_bus.rx_empty || !rx_fifo_valid[1]) begin
+                fifo_bus.rx_read = (!fifo_bus.rx_empty && mem_bus_wdata_empty && mem_bus_wdata_valid[1] && !mem_bus_wdata_end);
+                if ((!fifo_bus.rx_empty && mem_bus_wdata_empty) || !mem_bus_wdata_valid[1]) begin
                     next_rx_fifo_bus_state = RX_FIFO_BUS_STATE_TRANSFER_2;
                     rx_fifo_shift = 1'b1;
                 end
+                if (mem_bus_wdata_end) begin
+                    next_rx_fifo_bus_state = RX_FIFO_BUS_STATE_IDLE;
+                end
             end
 
             RX_FIFO_BUS_STATE_TRANSFER_2: begin
-                fifo_bus.rx_read = (!fifo_bus.rx_empty && rx_fifo_valid[1]);
-                if (!fifo_bus.rx_empty || !rx_fifo_valid[1]) begin
+                fifo_bus.rx_read = (!fifo_bus.rx_empty && mem_bus_wdata_valid[0]);
+                if (!fifo_bus.rx_empty || !mem_bus_wdata_valid[0]) begin
                     next_rx_fifo_bus_state = RX_FIFO_BUS_STATE_ACK;
                     rx_fifo_shift = 1'b1;
                 end
@@ -241,7 +234,7 @@ module memory_dma (
 
             RX_FIFO_BUS_STATE_ACK: begin
                 if (mem_bus_wdata_ready) begin
-                    next_rx_fifo_bus_state = RX_FIFO_BUS_STATE_WAIT;
+                    next_rx_fifo_bus_state = RX_FIFO_BUS_STATE_TRANSFER_1;
                 end
             end
 
@@ -255,26 +248,12 @@ module memory_dma (
         mem_bus_wdata_ready <= 1'b0;
         rx_fifo_shift_delayed <= rx_fifo_shift;
 
-        if (rx_fifo_shift) begin
-            rx_fifo_valid <= {rx_fifo_valid[0], 1'bX};
-        end
-
         if (rx_fifo_shift_delayed) begin
             if (rx_fifo_bus_state == RX_FIFO_BUS_STATE_ACK) begin
                 mem_bus_wdata_ready <= 1'b1;
             end
             mem_bus_wdata_buffer <= {mem_bus_wdata_buffer[7:0], fifo_bus.rx_rdata};
         end
-
-        case (rx_fifo_bus_state)
-            RX_FIFO_BUS_STATE_WAIT: begin
-                if (mem_bus_wdata_empty) begin
-                    rx_fifo_valid <= mem_bus_wdata_valid;
-                end
-            end
-
-            default: begin end
-        endcase
     end
 
 
diff --git a/sw/deployer/src/main.rs b/sw/deployer/src/main.rs
index dd4aa9a..49e0152 100644
--- a/sw/deployer/src/main.rs
+++ b/sw/deployer/src/main.rs
@@ -892,12 +892,19 @@ fn handle_test_command(connection: Connection) -> Result<(), sc64::Error> {
 
     println!("{}: USB", "[SC64 Tests]".bold());
 
-    print!(" Performing USB speed test... ");
+    print!(" Performing USB write speed test... ");
     stdout().flush().unwrap();
+    println!(
+        "{}",
+        format!("{:.2} MiB/s", sc64.test_usb_speed(true)?).bright_green()
+    );
 
-    let (read_speed, write_speed) = sc64.test_usb_speed()?;
-
-    println!("Read speed: {read_speed:.2} MiB/s, Write speed: {write_speed:.2} MiB/s");
+    print!(" Performing USB read speed test... ");
+    stdout().flush().unwrap();
+    println!(
+        "{}",
+        format!("{:.2} MiB/s", sc64.test_usb_speed(false)?).bright_green()
+    );
 
     println!("{}: SDRAM (pattern)", "[SC64 Tests]".bold());
 
diff --git a/sw/deployer/src/sc64/mod.rs b/sw/deployer/src/sc64/mod.rs
index 2b1a721..db6b4a4 100644
--- a/sw/deployer/src/sc64/mod.rs
+++ b/sw/deployer/src/sc64/mod.rs
@@ -752,20 +752,22 @@ impl SC64 {
         }
     }
 
-    pub fn test_usb_speed(&mut self) -> Result<(f64, f64), Error> {
+    pub fn test_usb_speed(&mut self, write: bool) -> Result<f64, Error> {
         const TEST_ADDRESS: u32 = SDRAM_ADDRESS;
-        const TEST_LENGTH: usize = SDRAM_LENGTH;
+        const TEST_LENGTH: usize = 8 * 1024 * 1024;
         const MIB_DIVIDER: f64 = 1024.0 * 1024.0;
 
-        let read_time = std::time::Instant::now();
-        let data = self.command_memory_read(TEST_ADDRESS, TEST_LENGTH)?;
-        let read_speed = (TEST_LENGTH as f64 / MIB_DIVIDER) / read_time.elapsed().as_secs_f64();
+        let data = vec![0x00; TEST_LENGTH];
 
-        let write_time = std::time::Instant::now();
-        self.command_memory_write(TEST_ADDRESS, &data)?;
-        let write_speed = (TEST_LENGTH as f64 / MIB_DIVIDER) / write_time.elapsed().as_secs_f64();
+        let time = std::time::Instant::now();
 
-        Ok((read_speed, write_speed))
+        if write {
+            self.command_memory_write(TEST_ADDRESS, &data)?;
+        } else {
+            self.command_memory_read(TEST_ADDRESS, TEST_LENGTH)?;
+        }
+
+        Ok((TEST_LENGTH as f64 / MIB_DIVIDER) / time.elapsed().as_secs_f64())
     }
 
     pub fn test_sdram_pattern(