From ea42b286af3594da6c15cd006b4bb0ff0bbfad07 Mon Sep 17 00:00:00 2001 From: Polprzewodnikowy Date: Mon, 13 Sep 2021 22:16:19 +0200 Subject: [PATCH] skip bootloader --- fw/rtl/cpu/cpu_cfg.sv | 11 ++++++++--- sw/n64/src/sc64.h | 1 + sw/riscv/src/cfg.c | 41 ++++++++++++++++++++++++----------------- sw/riscv/src/sys.h | 1 + 4 files changed, 34 insertions(+), 20 deletions(-) diff --git a/fw/rtl/cpu/cpu_cfg.sv b/fw/rtl/cpu/cpu_cfg.sv index 55d3485..426b1b9 100644 --- a/fw/rtl/cpu/cpu_cfg.sv +++ b/fw/rtl/cpu/cpu_cfg.sv @@ -4,6 +4,8 @@ module cpu_cfg ( if_config.cpu cfg ); + logic skip_bootloader; + typedef enum bit [2:0] { R_SCR, R_DD_OFFSET, @@ -30,7 +32,8 @@ module cpu_cfg ( cfg.cpu_busy, cfg.usb_waiting, cfg.cmd_error, - 22'd0, + 21'd0, + skip_bootloader, cfg.flashram_enabled, cfg.sram_banked, cfg.sram_enabled, @@ -72,9 +75,10 @@ module cpu_cfg ( cfg.flashram_enabled <= 1'b0; cfg.dd_offset <= 26'h3BE_0000; cfg.save_offset <= 26'h3FE_0000; + skip_bootloader <= 1'b0; end else begin if (sys.n64_soft_reset) begin - cfg.sdram_switch <= 1'b0; + cfg.sdram_switch <= skip_bootloader; cfg.sdram_writable <= 1'b0; end if (cfg.cmd_request) begin @@ -93,13 +97,14 @@ module cpu_cfg ( end if (bus.wmask[0]) begin { + skip_bootloader, cfg.flashram_enabled, cfg.sram_banked, cfg.sram_enabled, cfg.dd_enabled, cfg.sdram_writable, cfg.sdram_switch - } <= bus.wdata[5:0]; + } <= bus.wdata[6:0]; end end diff --git a/sw/n64/src/sc64.h b/sw/n64/src/sc64.h index a478b5f..6c98447 100644 --- a/sw/n64/src/sc64.h +++ b/sw/n64/src/sc64.h @@ -21,6 +21,7 @@ enum cfg_id { CFG_ID_TV_TYPE, CFG_ID_SAVE_OFFEST, CFG_ID_DD_OFFEST, + CFG_ID_SKIP_BOOTLOADER, }; diff --git a/sw/riscv/src/cfg.c b/sw/riscv/src/cfg.c index 75052a8..e452237 100644 --- a/sw/riscv/src/cfg.c +++ b/sw/riscv/src/cfg.c @@ -24,6 +24,7 @@ enum cfg_id { CFG_ID_TV_TYPE, CFG_ID_SAVE_OFFEST, CFG_ID_DD_OFFEST, + CFG_ID_SKIP_BOOTLOADER, }; enum save_type { @@ -46,18 +47,18 @@ struct process { static struct process p; -static void scr_set_bit (uint32_t mask) { - CFG->SCR |= mask; -} - -static void scr_clr_bit (uint32_t mask) { - CFG->SCR &= ~(mask); +static void change_scr_bits (uint32_t mask, bool value) { + if (value) { + CFG->SCR |= mask; + } else { + CFG->SCR &= ~(mask); + } } static void set_save_type (enum save_type save_type) { uint32_t save_offset = DEFAULT_SAVE_OFFSET; - scr_clr_bit(CFG_SCR_FLASHRAM_EN | CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_EN); + change_scr_bits(CFG_SCR_FLASHRAM_EN | CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_EN, false); joybus_set_eeprom(EEPROM_NONE); switch (save_type) { @@ -73,19 +74,19 @@ static void set_save_type (enum save_type save_type) { break; case SAVE_TYPE_SRAM: save_offset = SDRAM_SIZE - SAVE_SIZE_SRAM; - CFG->SCR |= CFG_SCR_SRAM_EN; + change_scr_bits(CFG_SCR_SRAM_EN, true); break; case SAVE_TYPE_FLASHRAM: save_offset = SDRAM_SIZE - SAVE_SIZE_FLASHRAM; - CFG->SCR |= CFG_SCR_FLASHRAM_EN; + change_scr_bits(CFG_SCR_FLASHRAM_EN, true); break; case SAVE_TYPE_SRAM_BANKED: save_offset = SDRAM_SIZE - SAVE_SIZE_SRAM_BANKED; - CFG->SCR |= CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_EN; + change_scr_bits(CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_EN, true); break; case SAVE_TYPE_FLASHRAM_PKST2: save_offset = SAVE_OFFSET_PKST2; - CFG->SCR |= CFG_SCR_FLASHRAM_EN; + change_scr_bits(CFG_SCR_FLASHRAM_EN, true); break; default: break; @@ -103,13 +104,13 @@ void cfg_update (uint32_t *args) { CFG->SCR = args[1]; break; case CFG_ID_SDRAM_SWITCH: - (args[1] ? scr_set_bit : scr_clr_bit)(CFG_SCR_SDRAM_SWITCH); + change_scr_bits(CFG_SCR_SDRAM_SWITCH, args[1]); break; case CFG_ID_SDRAM_WRITABLE: - (args[1] ? scr_set_bit : scr_clr_bit)(CFG_SCR_SDRAM_WRITABLE); + change_scr_bits(CFG_SCR_SDRAM_WRITABLE, args[1]); break; case CFG_ID_DD_ENABLE: - (args[1] ? scr_set_bit : scr_clr_bit)(CFG_SCR_DD_EN); + change_scr_bits(CFG_SCR_DD_EN, args[1]); break; case CFG_ID_SAVE_TYPE: set_save_type((enum save_type)(args[1])); @@ -126,6 +127,9 @@ void cfg_update (uint32_t *args) { case CFG_ID_DD_OFFEST: CFG->DD_OFFSET = args[1]; break; + case CFG_ID_SKIP_BOOTLOADER: + change_scr_bits(CFG_SCR_SKIP_BOOTLOADER, args[1]); + break; } } @@ -158,6 +162,9 @@ void cfg_query (uint32_t *args) { case CFG_ID_DD_OFFEST: args[1] = CFG->DD_OFFSET; break; + case CFG_ID_SKIP_BOOTLOADER: + args[1] = CFG->SCR & CFG_SCR_SKIP_BOOTLOADER; + break; } } @@ -175,7 +182,7 @@ void process_cfg (void) { uint32_t args[2]; if (CFG->SCR & CFG_SCR_CPU_BUSY) { - scr_clr_bit(CFG_SCR_CMD_ERROR); + change_scr_bits(CFG_SCR_CMD_ERROR, false); args[0] = CFG->DATA[0]; args[1] = CFG->DATA[1]; @@ -190,13 +197,13 @@ void process_cfg (void) { break; default: - scr_set_bit(CFG_SCR_CMD_ERROR); + change_scr_bits(CFG_SCR_CMD_ERROR, true); break; } CFG->DATA[0] = args[0]; CFG->DATA[1] = args[1]; - scr_clr_bit(CFG_SCR_CPU_BUSY); + change_scr_bits(CFG_SCR_CPU_BUSY, false); } } diff --git a/sw/riscv/src/sys.h b/sw/riscv/src/sys.h index 9f7c14d..124edca 100644 --- a/sw/riscv/src/sys.h +++ b/sw/riscv/src/sys.h @@ -109,6 +109,7 @@ typedef volatile struct cfg_regs { #define CFG_SCR_SRAM_EN (1 << 3) #define CFG_SCR_SRAM_BANKED (1 << 4) #define CFG_SCR_FLASHRAM_EN (1 << 5) +#define CFG_SCR_SKIP_BOOTLOADER (1 << 6) #define CFG_SCR_CMD_ERROR (1 << 28) #define CFG_SCR_USB_WAITING (1 << 29) #define CFG_SCR_CPU_BUSY (1 << 30)