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https://github.com/Polprzewodnikowy/SummerCart64.git
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USB unplugged cable handling
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commit
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@ -387,7 +387,9 @@ module mcu_top (
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REG_USB_SCR: begin
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reg_rdata <= {
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4'd0,
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2'd0,
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usb_scb.pwrsav,
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usb_scb.reset_state,
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usb_scb.tx_count,
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usb_scb.rx_count,
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2'b00,
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@ -6,6 +6,8 @@ interface usb_scb ();
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logic write_buffer_flush;
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logic [10:0] rx_count;
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logic [10:0] tx_count;
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logic pwrsav;
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logic reset_state;
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modport controller (
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output fifo_flush,
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@ -13,7 +15,9 @@ interface usb_scb ();
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output reset_ack,
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output write_buffer_flush,
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input rx_count,
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input tx_count
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input tx_count,
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input pwrsav,
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input reset_state
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);
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modport usb (
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@ -22,7 +26,9 @@ interface usb_scb ();
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input reset_ack,
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input write_buffer_flush,
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output rx_count,
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output tx_count
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output tx_count,
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output pwrsav,
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output reset_state
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);
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endinterface
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@ -145,6 +151,9 @@ module usb_ft1248 (
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state <= next_state;
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cmd <= next_cmd;
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usb_scb.pwrsav <= !ft_pwrsav;
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usb_scb.reset_state <= last_reset_status;
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phase <= {phase[2:0], phase[3]};
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if (state == STATE_IDLE) begin
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phase <= 4'b0100;
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@ -83,6 +83,8 @@ typedef enum {
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#define USB_SCR_RX_COUNT_MASK (0x7FF << USB_SCR_RX_COUNT_BIT)
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#define USB_SCR_TX_COUNT_BIT (17)
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#define USB_SCR_TX_COUNT_MASK (0x7FF << USB_SCR_TX_COUNT_BIT)
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#define USB_SCR_RESET_STATE (1 << 28)
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#define USB_SCR_PWRSAV (1 << 29)
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#define DMA_SCR_START (1 << 0)
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#define DMA_SCR_STOP (1 << 1)
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@ -408,6 +408,7 @@ bool usb_prepare_read (uint32_t *args) {
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}
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void usb_get_read_info (uint32_t *args) {
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uint32_t scr = fpga_reg_get(REG_USB_SCR);
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args[0] = 0;
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args[1] = 0;
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if (p.rx_state == RX_STATE_DATA && p.rx_cmd == 'U') {
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@ -415,6 +416,8 @@ void usb_get_read_info (uint32_t *args) {
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args[1] = p.rx_args[1];
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}
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args[0] |= (p.read_length > 0) ? (1 << 31) : 0;
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args[0] |= (scr & USB_SCR_RESET_STATE) ? (1 << 30) : 0;
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args[0] |= (scr & USB_SCR_PWRSAV) ? (1 << 29) : 0;
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}
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void usb_init (void) {
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@ -438,12 +441,19 @@ void usb_init (void) {
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}
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void usb_process (void) {
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if (fpga_reg_get(REG_USB_SCR) & USB_SCR_RESET_PENDING) {
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if (p.tx_state != TX_STATE_IDLE && p.tx_info.done_callback) {
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p.tx_info.done_callback();
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uint32_t scr = fpga_reg_get(REG_USB_SCR);
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if (scr & (USB_SCR_PWRSAV | USB_SCR_RESET_STATE | USB_SCR_RESET_PENDING)) {
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if (p.packet_pending && p.packet_info.done_callback) {
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p.packet_pending = false;
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p.packet_info.done_callback();
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}
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if (scr & USB_SCR_RESET_PENDING) {
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if (p.tx_state != TX_STATE_IDLE && p.tx_info.done_callback) {
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p.tx_info.done_callback();
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}
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usb_init();
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fpga_reg_set(REG_USB_SCR, USB_SCR_RESET_ACK);
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}
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usb_init();
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fpga_reg_set(REG_USB_SCR, USB_SCR_RESET_ACK);
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} else {
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usb_rx_process();
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usb_tx_process();
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