From f5652a01082f6c78905c318aa46e86562a9c9b98 Mon Sep 17 00:00:00 2001 From: Mateusz Faderewski Date: Sat, 5 Nov 2022 22:54:52 +0100 Subject: [PATCH] PI address debug --- fw/rtl/mcu/mcu_top.sv | 11 ++++++++--- fw/rtl/n64/n64_pi.sv | 28 ++++++++++++++++++++-------- fw/rtl/n64/n64_scb.sv | 2 +- sw/controller/src/cfg.c | 3 ++- sw/controller/src/fpga.h | 3 ++- sw/controller/src/usb.c | 5 +++-- 6 files changed, 36 insertions(+), 16 deletions(-) diff --git a/fw/rtl/mcu/mcu_top.sv b/fw/rtl/mcu/mcu_top.sv index 9e025df..76e9996 100644 --- a/fw/rtl/mcu/mcu_top.sv +++ b/fw/rtl/mcu/mcu_top.sv @@ -356,7 +356,8 @@ module mcu_top ( REG_DD_DRIVE_ID, REG_VENDOR_SCR, REG_VENDOR_DATA, - REG_DEBUG + REG_DEBUG_0, + REG_DEBUG_1 } reg_address_e; logic bootloader_skip; @@ -631,10 +632,14 @@ module mcu_top ( reg_rdata <= vendor_scb.data_rdata; end - REG_DEBUG: begin + REG_DEBUG_0: begin + reg_rdata <= n64_scb.pi_debug[31:0]; + end + + REG_DEBUG_1: begin reg_rdata <= { 28'd0, - n64_scb.pi_debug + n64_scb.pi_debug[35:32] }; end endcase diff --git a/fw/rtl/n64/n64_pi.sv b/fw/rtl/n64/n64_pi.sv index e268c41..e15da47 100644 --- a/fw/rtl/n64/n64_pi.sv +++ b/fw/rtl/n64/n64_pi.sv @@ -122,6 +122,18 @@ module n64_pi ( end + // Debug: last accessed PI address + + always_ff @(posedge clk) begin + if (aleh_op) begin + n64_scb.pi_debug[31:16] <= n64_pi_dq_in; + end + if (alel_op) begin + n64_scb.pi_debug[15:0] <= n64_pi_dq_in; + end + end + + // Address decoding const bit [31:0] DDIPL_OFFSET = 32'h03BC_0000; @@ -289,8 +301,8 @@ module n64_pi ( always_ff @(posedge clk) begin read_fifo_read <= 1'b0; - if (reset) begin - n64_scb.pi_debug[1:0] <= 2'b00; + if (!pi_reset) begin + n64_scb.pi_debug[33:32] <= 2'b00; end if (reset || !pi_reset || alel_op) begin @@ -301,9 +313,9 @@ module n64_pi ( if (read_op) begin if (read_fifo_empty) begin read_fifo_wait <= 1'b1; - n64_scb.pi_debug[0] <= 1'b1; + n64_scb.pi_debug[32] <= 1'b1; if (read_fifo_wait) begin - n64_scb.pi_debug[1] <= 1'b1; + n64_scb.pi_debug[33] <= 1'b1; end end else begin read_fifo_read <= 1'b1; @@ -356,8 +368,8 @@ module n64_pi ( always_ff @(posedge clk) begin write_fifo_write <= 1'b0; - if (reset) begin - n64_scb.pi_debug[3:2] <= 2'b00; + if (!pi_reset) begin + n64_scb.pi_debug[35:34] <= 2'b00; end if (reset) begin @@ -368,9 +380,9 @@ module n64_pi ( if (write_op) begin if (write_fifo_full) begin write_fifo_wait <= 1'b1; - n64_scb.pi_debug[2] <= 1'b1; + n64_scb.pi_debug[34] <= 1'b1; if (write_fifo_wait) begin - n64_scb.pi_debug[3] <= 1'b1; + n64_scb.pi_debug[35] <= 1'b1; end end else begin write_fifo_write <= 1'b1; diff --git a/fw/rtl/n64/n64_scb.sv b/fw/rtl/n64/n64_scb.sv index 7c22732..c61f103 100644 --- a/fw/rtl/n64/n64_scb.sv +++ b/fw/rtl/n64/n64_scb.sv @@ -53,7 +53,7 @@ interface n64_scb (); logic pi_sdram_active; logic pi_flash_active; - logic [3:0] pi_debug; + logic [35:0] pi_debug; modport controller ( input n64_reset, diff --git a/sw/controller/src/cfg.c b/sw/controller/src/cfg.c index 9dc608c..8481e84 100644 --- a/sw/controller/src/cfg.c +++ b/sw/controller/src/cfg.c @@ -569,7 +569,8 @@ void cfg_process (void) { break; case '?': - args[0] = fpga_reg_get(REG_DEBUG); + args[0] = fpga_reg_get(REG_DEBUG_0); + args[1] = fpga_reg_get(REG_DEBUG_1); break; default: diff --git a/sw/controller/src/fpga.h b/sw/controller/src/fpga.h index a6cec0d..28a4979 100644 --- a/sw/controller/src/fpga.h +++ b/sw/controller/src/fpga.h @@ -52,7 +52,8 @@ typedef enum { REG_DD_DRIVE_ID, REG_VENDOR_SCR, REG_VENDOR_DATA, - REG_DEBUG + REG_DEBUG_0, + REG_DEBUG_1, } fpga_reg_t; diff --git a/sw/controller/src/usb.c b/sw/controller/src/usb.c index ea8fa27..ca73e75 100644 --- a/sw/controller/src/usb.c +++ b/sw/controller/src/usb.c @@ -288,8 +288,9 @@ static void usb_rx_process (void) { case '?': p.rx_state = RX_STATE_IDLE; p.response_pending = true; - p.response_info.data_length = 4; - p.response_info.data[0] = fpga_reg_get(REG_DEBUG); + p.response_info.data_length = 8; + p.response_info.data[0] = fpga_reg_get(REG_DEBUG_0); + p.response_info.data[1] = fpga_reg_get(REG_DEBUG_1); break; default: