diff --git a/.github/FUNDING.yml b/.github/FUNDING.yml deleted file mode 100644 index d259fc9..0000000 --- a/.github/FUNDING.yml +++ /dev/null @@ -1 +0,0 @@ -ko_fi: polprzewodnikowy diff --git a/.github/sc64_clean_pcb.jpg b/.github/sc64_clean_pcb.jpg deleted file mode 100644 index bcd4ff9..0000000 Binary files a/.github/sc64_clean_pcb.jpg and /dev/null differ diff --git a/.github/sc64_in_n64.jpg b/.github/sc64_in_n64.jpg deleted file mode 100644 index 60f234e..0000000 Binary files a/.github/sc64_in_n64.jpg and /dev/null differ diff --git a/.github/sc64_on_table.jpg b/.github/sc64_on_table.jpg deleted file mode 100644 index 80b8538..0000000 Binary files a/.github/sc64_on_table.jpg and /dev/null differ diff --git a/.github/sc64_v2_block_diagram.svg b/.github/sc64_v2_block_diagram.svg new file mode 100644 index 0000000..35515f2 --- /dev/null +++ b/.github/sc64_v2_block_diagram.svg @@ -0,0 +1,4 @@ + + + +
SPI Interface
SPI Interface
USB FIFO R/W
USB FIFO R/W
Memory interface
Memory interface
Control Register File
Control Register File
FT1248 Interface
FT1248 Interface
TX FIFO 1kB
TX FIFO 1kB
RX FIFO 1kB
RX FIFO 1kB
FIFO Junction
FIFO Junction
USB DMA Controller
USB DMA Controller
SDIO Interface
SDIO Interface
TX FIFO 1kB
TX FIFO 1kB
RX FIFO 1kB
RX FIFO 1kB
SD DMA Controller
SD DMA Controller
USB
FT232H
USB...
USB
Type-C
USB...
SD Card Slot
SD Card Sl...
μC
STM32G030
μC...
RTC
MCP7940N
RTC...
UART Header
UART Header
 USB
 USB
 Flashcart Controller
 Flashcart Controller
 SD Card
 SD Card
Button
Button
LED
LED
FLASH Interface
FLASH Interface
SDRAM Interface
SDRAM Interface
Block RAM ~10kB
Block RAM ~10kB
SDRAM
64 MB
SDRAM...
QSPI FLASH
16 MB
QSPI FLASH...
 Memory
 Memory
Memory Arbiter
Memory Arbiter
FPGA Vendor Interface
FPGA Vendor Int...
N64
CIC
N64...
N64
Reset
N64...
N64
IRQ
N64...
N64
Joybus
N64...
N64
AD16 Bus
N64...
PI Interface
PI Interface
Joybus Interface
Joybus Interface
EEPROM Controller
EEPROM Controller
RTC Controller
RTC Controller
64DD Controller
64DD Controller
FlashRAM Controller
FlashRAM Controller
Flashcart Interface
Flashcart Interface
 N64 Joybus devices
 N64 Joybus devices
 N64 PI devices
 N64 PI devices
IRQ Controller
IRQ Controller
FPGA 
LCMXO2-7000 
FPGA...
12 MHz
Clock
12 MHz...
50 MHz
Clock
50 MHz...
PLL
PLL
SYS CLK
SYS CLK
SYS CLK
100 MHz
SYS CLK...
SDRAM CLK
100 MHz 90°
SDRAM CLK...
 Clock & Reset
 Clock & Reset
RESET
RESET
Power-ON
Reset Generator
Power-ON...
Debug
Header
Debug...Text is not SVG - cannot display \ No newline at end of file diff --git a/.github/sc64_v2_example.jpg b/.github/sc64_v2_example.jpg new file mode 100644 index 0000000..5a5ae41 Binary files /dev/null and b/.github/sc64_v2_example.jpg differ diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 4da4db4..708ec6a 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -20,15 +20,25 @@ jobs: - uses: actions/checkout@v2 with: submodules: true + + - name: Prepare Lattice Diamond license + env: + ENCODED_LICENSE: ${{ secrets.LATTICE_DIAMOND_LICENSE }} + run: | + mkdir -p ./flexlm + echo "$ENCODED_LICENSE" > ./flexlm/encoded_license + base64 -d ./flexlm/encoded_license > ./flexlm/license.dat - name: Build script + env: + MAC_ADDRESS: ${{ secrets.LATTICE_DIAMOND_MAC }} run: ./docker_build.sh release --force-clean - name: Upload artifact uses: actions/upload-artifact@v2 with: - name: SummerCart64 - path: SummerCart64.zip + name: SC64 + path: SC64.zip - name: Get release if: github.event_name == 'release' && github.event.action == 'created' @@ -44,6 +54,6 @@ jobs: GITHUB_TOKEN: ${{ github.token }} with: upload_url: ${{ steps.get_release.outputs.upload_url }} - asset_path: SummerCart64.zip - asset_name: SummerCart64.zip + asset_path: SC64.zip + asset_name: SC64.zip asset_content_type: application/zip diff --git a/.gitignore b/.gitignore index 2e1177e..44266f1 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,7 @@ **/.DS_Store -**/.vscode +**/.vscode/ **/*.bak **/*.zip +/flexlm + +!**/.vscode/tasks.json diff --git a/.gitmodules b/.gitmodules deleted file mode 100644 index e1371e8..0000000 --- a/.gitmodules +++ /dev/null @@ -1,8 +0,0 @@ -[submodule "fw/picorv32"] - path = fw/picorv32 - url = https://github.com/cliffordwolf/picorv32.git - ignore = dirty -[submodule "sw/cic"] - path = sw/cic - url = https://github.com/ManCloud/UltraCIC-III.git - ignore = dirty diff --git a/.vscode/tasks.json b/.vscode/tasks.json new file mode 100644 index 0000000..6a40325 --- /dev/null +++ b/.vscode/tasks.json @@ -0,0 +1,73 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "build_bootloader", + "type": "shell", + "command": "./docker_build.sh bootloader", + "presentation": { + "showReuseMessage": false, + "clear": true + }, + "windows": { + "command": "wsl -- ./docker_build.sh bootloader" + }, + "group": "build" + }, + { + "label": "build_controller", + "type": "shell", + "command": "./docker_build.sh controller", + "presentation": { + "showReuseMessage": false, + "clear": true + }, + "windows": { + "command": "wsl -- ./docker_build.sh controller" + }, + "group": "build" + }, + { + "label": "build_fpga", + "type": "shell", + "command": "./docker_build.sh fpga", + "presentation": { + "showReuseMessage": false, + "clear": true + }, + "windows": { + "command": "wsl -- ./docker_build.sh fpga" + }, + "group": "build" + }, + { + "label": "build_update", + "type": "shell", + "command": "./docker_build.sh update", + "presentation": { + "showReuseMessage": false, + "clear": true + }, + "windows": { + "command": "wsl -- ./docker_build.sh update" + }, + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "build_release", + "type": "shell", + "command": "./docker_build.sh release --force-clean", + "presentation": { + "showReuseMessage": false, + "clear": true + }, + "windows":{ + "command": "wsl -- ./docker_build.sh release --force-clean" + }, + "group": "build" + }, + ] +} \ No newline at end of file diff --git a/README.md b/README.md index 8b70715..9a834fb 100644 --- a/README.md +++ b/README.md @@ -1,78 +1,29 @@ -# SummerCollection - -A collection of hardware, firmware and software designs of SummerCart64 - Nintendo 64 FlashCart/DevKit. +# SC64 - an open source Nintendo 64 flashcart -## Project parts - -### Firmware - -Folder **`fw`** contains firmware written in Verilog for Intel MAX10 FPGA. - -### Hardware - -Folder **`hw`** contains PCB design made in Autodesk Eagle. - -### Software - -Folder **`sw`** contains several helper programs that makes flash cart work all together, including bootloader and CIC emulation. +## Features + - 64 MB SDRAM memory for game and save data + - 16 MB FLASH memory for bootloader and extended game data + - 8 kB on-chip buffer for general use + - 25 MB/s peak transfer rate USB interface for data upload/download and debug functionality + - 25 MB/s peak transfer rate SD card interface + - EEPROM, SRAM and FlashRAM save types ~~with automatic writeback to SD card~~ (_not implemented yet_) + - Battery backed real time clock (RTC) + - Status LED and button for general use + - 64DD add-on emulation + - IS-Viewer 64 debug interface + - Software and firmware update via USB interface + - N64 bootloader with support for IPL2 registers spoofing and loading menu from SD card + - Enhanced [UltraCIC_C](https://github.com/jago85/UltraCIC_C) emulation with automatic region switching and programmable seed/checksum values + - PC app for communicating with flashcart (game/save data upload/download, feature enable control and debug console) + - [UNFLoader](https://github.com/buu342/N64-UNFLoader) support -## What works +## High-level flashcart block diagram -### **OLD STATUS, WILL BE UPDATED SOON** - -~~Currently hardware implements basic functionality for playing games - ROM emulation, 4/16K EEPROM, bootloader and PC communication. You can send any ROM to the SDRAM from PC and if game doesn't check for save hardware other than EEPROM then it most likely will work. Bootloader does all the work necessary to setup the console registers for specific CIC chip that game requires.~~ +[](.github/sc64_v2_block_diagram.svg) -## How to build +## Finished sample -### **OLD INSTRUCTIONS, WILL BE UPDATED SOON** - -~~Instructions below are mostly written for Windows users and point to Windows specific executables.~~ - -1. ~~Download latest zip files from [releases tab](https://github.com/Polprzewodnikowy/SummerCollection/releases).~~ -2. ~~Order PCBs in your farovite company, all gerbers, bill of materials and schematics are in **`SummerCart64_PCB-[version].zip`** file.~~ -3. ~~Order all necessary components, eg. in [Mouser](https://mouser.com/).~~ -4. ~~Solder all components onto the PCB.~~ -5. ~~Connect flashcart to PC.~~ -6. ~~Download [FT_PROG](https://www.ftdichip.com/Support/Utilities.htm#FT_PROG) from FTDI website.~~ -7. ~~Open FT_PROG and scan for devices.~~ -8. ~~Load `ftdi-template.xml` from **`SummerCart64-[version].zip`** located in `hw` folder.~~ -9. ~~Program FTDI chip, then right click on the device and select "Cycle port"~~ -10. ~~Download and install [Arrow USB Blaster drivers](https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Software/Drivers/Arrow_USB_Programmer/Arrow_USB_Programmer_2.4) from Trenz Electronic website.~~ -11. ~~Download and install [QuartusProgrammer](https://download.altera.com/akdlm/software/acdsinst/20.1std/711/ib_installers/QuartusProgrammerSetup-20.1.0.711-windows.exe) from Intel website.~~ -12. ~~Click on "Hardware Setup..." button and select "Arrow-USB-Blaster [AR*xxxxxx*]" in "Currently selected hardware", then close window.~~ -13. ~~Click on "Auto Detect" button and select "10M08SC" option.~~ -14. ~~Click on the newly shown row, then click on "Change File..." button and select `SummerCart64.pof` file from **`SummerCart64-[version].zip`** located in `fw/output_files` folder.~~ -15. ~~Select "Program/Configure" and "Verify" checkboxes.~~ -16. ~~Click on "Start" button and wait for operation to finish.~~ -17. ~~Download and install avrdude.~~ -18. ~~Program ATtiny45 with `UltraCIC-III.hex` file from **`SummerCart64-[version].zip`** located in `sw/cic` folder, more information is available [here](https://github.com/ManCloud/UltraCIC-III).~~ -19. ~~Download latest release of [N64-UNFLoader](https://github.com/buu342/N64-UNFLoader).~~ -20. ~~Insert flashcart in the Nintendo 64.~~ -21. ~~Upload ROM by executing `UNFLoader -r your_rom_file.n64`~~ -22. ~~Turn on console and enjoy playing homebrew games on real hardware.~~ - - -## Issues - -### **OLD STATUS, WILL BE UPDATED SOON** - -~~There are several issues with the project at the moment in order of importance. Keep in mind that core flashcart functionality is fully working:~~ - -- ~~No save write-back to SD card without console reset implementation.~~ - - -## What's next - -Current goal is to rewrite README.md - - -## Finished sample (obsolete v1 version, to be replaced with v2) - -![SummerCart64 clean PCB](.github/sc64_clean_pcb.jpg) - -![SummerCart64 on table](.github/sc64_on_table.jpg) - -![SummerCart64 in partialy disassembled Nintendo 64](.github/sc64_in_n64.jpg) +[SC64 HW ver: 2.0](.github/sc64_v2_example.jpg) diff --git a/assets/sc64_logo.blend b/assets/sc64_logo.blend new file mode 100644 index 0000000..ecde59d Binary files /dev/null and b/assets/sc64_logo.blend differ diff --git a/build.sh b/build.sh index a240f1f..10e5af8 100755 --- a/build.sh +++ b/build.sh @@ -2,80 +2,66 @@ set -e -PACKAGE_FILE_NAME="SummerCart64" +PACKAGE_FILE_NAME="SC64" FILES=( - "./fw/output_files/SC64_firmware.pof" - "./fw/output_files/SC64_update.bin" - "./hw/ftdi-template.xml" - "./sw/cic/UltraCIC-III.hex" + "./fw/ftdi/ft232h_config.xml" + "./fw/project/lcmxo2/impl1/sc64_impl1.mrp" + "./fw/project/lcmxo2/impl1/sc64_impl1.twr" + "./sw/pc/dd64.py" + "./sw/pc/sc64.py" + "./sw/update/sc64.upd" "./LICENSE" + "./README.md" ) -BUILT_CIC=false -BUILT_N64=false -BUILT_RISCV=false +BUILT_BOOTLOADER=false +BUILT_CONTROLLER=false BUILT_FPGA=false BUILT_UPDATE=false BUILT_RELEASE=false FORCE_CLEAN=false -SKIP_FPGA_REBUILD=false -DEBUG_ENABLED=false -USER_FLAGS+=" -D__SC64_VERSION=\"$__SC64_VERSION\"" -build_cic () { - if [ "$BUILT_CIC" = true ]; then return; fi +build_bootloader () { + if [ "$BUILT_BOOTLOADER" = true ]; then return; fi - pushd sw/cic > /dev/null - avra UltraCIC-III.asm -D attiny45 - popd > /dev/null - - BUILT_CIC=true -} - -build_n64 () { - if [ "$BUILT_N64" = true ]; then return; fi - - pushd sw/n64 > /dev/null + pushd sw/bootloader > /dev/null if [ "$FORCE_CLEAN" = true ]; then make clean fi - make all -j USER_FLAGS="$USER_FLAGS" + FLAGS="$USER_FLAGS" + if [ ! -z "${GIT_BRANCH+x}" ]; then FLAGS+=" -DGIT_BRANCH='\"$GIT_BRANCH\"'"; fi + if [ ! -z "${GIT_TAG+x}" ]; then FLAGS+=" -DGIT_TAG='\"$GIT_TAG\"'"; fi + if [ ! -z "${GIT_SHA+x}" ]; then FLAGS+=" -DGIT_SHA='\"$GIT_SHA\"'"; fi + if [ ! -z "${GIT_MESSAGE+x}" ]; then FLAGS+=" -DGIT_MESSAGE='\"$GIT_MESSAGE\"'"; fi + make all -j USER_FLAGS="$FLAGS" popd > /dev/null - BUILT_N64=true + BUILT_BOOTLOADER=true } -build_riscv () { - if [ "$BUILT_RISCV" = true ]; then return; fi +build_controller () { + if [ "$BUILT_CONTROLLER" = true ]; then return; fi - pushd sw/riscv > /dev/null + pushd sw/controller > /dev/null if [ "$FORCE_CLEAN" = true ]; then - make clean + ./build.sh clean fi - make all -j USER_FLAGS="$USER_FLAGS" + USER_FLAGS="$USER_FLAGS" ./build.sh all popd > /dev/null - BUILT_RISCV=true + BUILT_CONTROLLER=true } build_fpga () { if [ "$BUILT_FPGA" = true ]; then return; fi - build_n64 - build_riscv - - pushd fw > /dev/null - if [ "$SKIP_FPGA_REBUILD" = true ] && [ -f output_files/SummerCart64.sof ]; then - quartus_cpf -c SummerCart64.cof - else - if [ "$DEBUG_ENABLED" = true ]; then - quartus_sh --set VERILOG_MACRO="DEBUG" ./SummerCart64.qpf - fi - quartus_sh --flow compile ./SummerCart64.qpf - quartus_sh --set -remove VERILOG_MACRO="DEBUG" ./SummerCart64.qpf + pushd fw/project/lcmxo2 > /dev/null + if [ "$FORCE_CLEAN" = true ]; then + rm -rf ./impl1/ fi + ./build.sh popd > /dev/null BUILT_FPGA=true @@ -84,12 +70,26 @@ build_fpga () { build_update () { if [ "$BUILT_UPDATE" = true ]; then return; fi + build_bootloader + build_controller build_fpga - pushd fw/output_files > /dev/null - cat sc64_firmware_ufm_auto.rpd sc64_firmware_cfm0_auto.rpd > SC64_update_tmp.bin - objcopy -I binary -O binary --reverse-bytes=4 SC64_update_tmp.bin SC64_update.bin - rm SC64_update_tmp.bin + pushd sw/update > /dev/null + if [ "$FORCE_CLEAN" = true ]; then + rm -f ./sc64.upd + fi + GIT_INFO="" + if [ ! -z "${GIT_BRANCH}" ]; then GIT_INFO+="branch: [$GIT_BRANCH] "; fi + if [ ! -z "${GIT_TAG}" ]; then GIT_INFO+="tag: [$GIT_TAG] "; fi + if [ ! -z "${GIT_SHA}" ]; then GIT_INFO+="sha: [$GIT_SHA] "; fi + if [ ! -z "${GIT_MESSAGE}" ]; then GIT_INFO+="message: [$GIT_MESSAGE] "; fi + GIT_INFO=$(echo "$GIT_INFO" | xargs) + python3 update.py \ + --git "$GIT_INFO" \ + --mcu ../controller/build/app/app.bin \ + --fpga ../../fw/project/lcmxo2/impl1/sc64_impl1.jed \ + --boot ../bootloader/build/bootloader.bin \ + sc64.upd popd > /dev/null BUILT_UPDATE=true @@ -98,7 +98,6 @@ build_update () { build_release () { if [ "$BUILT_RELEASE" = true ]; then return; fi - build_cic build_update if [ -e "./${PACKAGE_FILE_NAME}.zip" ]; then @@ -110,22 +109,17 @@ build_release () { } print_usage () { - echo "builder script for SummerCart64" - echo "usage: ./build.sh [cic] [n64] [riscv] [fpga] [update] [release] [-c] [-s] [-d] [--help]" + echo "builder script for SC64" + echo "usage: ./build.sh [bootloader] [controller] [fpga] [update] [release] [-c] [--help]" echo "parameters:" - echo " cic - assemble UltraCIC-III software" - echo " n64 - compile N64 bootloader software" - echo " riscv - compile cart governor software" - echo " fpga - compile FPGA design (triggers 'n64' and 'riscv' build)" - echo " update - convert programming .pof file to raw binary for self-upgrade (triggers 'fpga' build)" - echo " release - collect and zip files for release (triggers 'cic' and 'update' build)" + echo " bootloader - compile N64 bootloader software" + echo " controller - compile ARM controller software" + echo " fpga - compile FPGA design" + echo " update - compile all software and designs" + echo " release - collect and zip files for release (triggers 'update' build)" echo " -c | --force-clean" - echo " - clean software compilation result directories before build" - echo " -s | --skip-fpga-rebuild" - echo " - do not recompile whole FPGA design if it's already done, just update software binaries" - echo " -d | --debug" - echo " - enable debug features" - echo " --help - print this guide" + echo " - clean compilation result directories before build" + echo " --help - print this guide" } if test $# -eq 0; then @@ -135,23 +129,19 @@ if test $# -eq 0; then exit 1 fi -TRIGGER_CIC=false -TRIGGER_N64=false -TRIGGER_RISCV=false +TRIGGER_BOOTLOADER=false +TRIGGER_CONTROLLER=false TRIGGER_FPGA=false TRIGGER_UPDATE=false TRIGGER_RELEASE=false while test $# -gt 0; do case "$1" in - cic) - TRIGGER_CIC=true + bootloader) + TRIGGER_BOOTLOADER=true ;; - n64) - TRIGGER_N64=true - ;; - riscv) - TRIGGER_RISCV=true + controller) + TRIGGER_CONTROLLER=true ;; fpga) TRIGGER_FPGA=true @@ -165,12 +155,6 @@ while test $# -gt 0; do -c|--force-clean) FORCE_CLEAN=true ;; - -s|--skip-fpga-rebuild) - SKIP_FPGA_REBUILD=true - ;; - -d|--debug) - DEBUG_ENABLED=true - ;; --help) print_usage exit 0 @@ -185,10 +169,8 @@ while test $# -gt 0; do shift done -if [ "$DEBUG_ENABLED" = true ]; then USER_FLAGS+=" -DDEBUG"; fi -if [ "$TRIGGER_CIC" = true ]; then build_cic; fi -if [ "$TRIGGER_N64" = true ]; then build_n64; fi -if [ "$TRIGGER_RISCV" = true ]; then build_riscv; fi +if [ "$TRIGGER_BOOTLOADER" = true ]; then build_bootloader; fi +if [ "$TRIGGER_CONTROLLER" = true ]; then build_controller; fi if [ "$TRIGGER_FPGA" = true ]; then build_fpga; fi if [ "$TRIGGER_UPDATE" = true ]; then build_update; fi if [ "$TRIGGER_RELEASE" = true ]; then build_release; fi diff --git a/docker_build.sh b/docker_build.sh index 169cea1..0129053 100755 --- a/docker_build.sh +++ b/docker_build.sh @@ -1,18 +1,37 @@ #!/bin/bash -GIT_SHA=$(git rev-parse --short HEAD) -GIT_TAG=$(git describe --tags --exact-match 2> /dev/null) +BUILDER_IMAGE="ghcr.io/polprzewodnikowy/sc64env:v1.5" -if [ ! -z $GIT_TAG ]; then - __SC64_VERSION=$(printf "%.7q\ %.7q" $GIT_SHA $GIT_TAG) -else - __SC64_VERSION=$(printf "%.7q\ develop" $GIT_SHA) +pushd $(dirname $0) > /dev/null + +GIT_BRANCH=$(git rev-parse --abbrev-ref HEAD) +GIT_TAG=$(git describe --tags 2> /dev/null) +GIT_SHA=$(git rev-parse HEAD) +GIT_MESSAGE=$(git log --oneline --format=%B -n 1 HEAD | head -n 1) + +if [ -t 1 ]; then + DOCKER_OPTIONS="-it" fi docker run \ + $DOCKER_OPTIONS \ --rm \ --user $(id -u):$(id -g) \ + --mac-address ${MAC_ADDRESS:-F8:12:34:56:78:90} \ + --mount type=bind,src="$(pwd)/flexlm",target="/flexlm" \ --mount type=bind,src="$(pwd)",target="/workdir" \ - -e __SC64_VERSION="$__SC64_VERSION" \ - ghcr.io/polprzewodnikowy/sc64env:v1.2 \ + -h=`hostname` \ + -e GIT_BRANCH="$GIT_BRANCH" \ + -e GIT_TAG="$GIT_TAG" \ + -e GIT_SHA="$GIT_SHA" \ + -e GIT_MESSAGE="$GIT_MESSAGE" \ + $BUILDER_IMAGE \ ./build.sh $@ + +BUILD_ERROR=$? + +popd > /dev/null + +if [ $BUILD_ERROR -ne 0 ]; then + exit -1 +fi diff --git a/fw/.gitignore b/fw/.gitignore deleted file mode 100644 index e8bfb66..0000000 --- a/fw/.gitignore +++ /dev/null @@ -1,13 +0,0 @@ -/db -/greybox_tmp -/incremental_db -/output_files -**/.qsys_edit -**/*.bin -**/*.dat -**/*.elf -*.qws -*.rpt -*.sopcinfo -*.srf -*.txt diff --git a/fw/SummerCart64.cof b/fw/SummerCart64.cof deleted file mode 100644 index ebd1b9d..0000000 --- a/fw/SummerCart64.cof +++ /dev/null @@ -1,42 +0,0 @@ - - - output_files/SC64_firmware.pof - 1 - 1 - 14 - - Page_0 - 1 - - output_files/SummerCart64.sof1 - - - 10 - 0 - 0 - 1 - 0 - - 1 - - - 0 - 1 - 0 - 0 - 0 - 0 - 2 - ../sw/n64/build/n64boot.hex - ../sw/riscv/build/governor.hex - 305152 - - - 1 - 2 - 0 - -1 - -1 - 1 - - \ No newline at end of file diff --git a/fw/SummerCart64.qpf b/fw/SummerCart64.qpf deleted file mode 100644 index b58ed21..0000000 --- a/fw/SummerCart64.qpf +++ /dev/null @@ -1,31 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2020 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and any partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details, at -# https://fpgasoftware.intel.com/eula. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition -# Date created = 10:53:32 August 01, 2021 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "20.1" -DATE = "10:53:32 August 01, 2021" - -# Revisions - -PROJECT_REVISION = "SummerCart64" diff --git a/fw/SummerCart64.qsf b/fw/SummerCart64.qsf deleted file mode 100644 index d24b06c..0000000 --- a/fw/SummerCart64.qsf +++ /dev/null @@ -1,292 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2021 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and any partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details, at -# https://fpgasoftware.intel.com/eula. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition -# Date created = 13:29:40 November 11, 2021 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# SummerCart64_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Intel recommends that you do not modify this file. This -# file is updated automatically by the Quartus Prime software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:53:32 AUGUST 01, 2021" -set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON -set_global_assignment -name QSYS_FILE rtl/intel/flash/intel_flash.qsys -set_global_assignment -name QIP_FILE rtl/intel/fifo/intel_fifo_8.qip -set_global_assignment -name QIP_FILE rtl/intel/gpio/intel_gpio_ddro.qip -set_global_assignment -name QIP_FILE rtl/intel/pll/intel_pll.qip -set_global_assignment -name SDC_FILE SummerCart64.sdc -set_global_assignment -name SYSTEMVERILOG_FILE picorv32/picorv32.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_bus.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_cfg.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_dd.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_dma.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_flash.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_flashram.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_gpio.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_i2c.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_ram.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_sdram.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_si.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_soc.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_uart.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_usb.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_wrapper.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/memory/memory_sdram.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_bootloader.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_bus.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_cfg.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_dd.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_flashram.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_pi.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_pi_fifo.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_sdram.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_si.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_soc.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/SummerCart64.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/config.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/sc64.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/system.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/usb/usb_ft1248.sv -set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:scripts/post_module.tcl" - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_6 -to o_usb_clk -set_location_assignment PIN_7 -to io_usb_miosi[2] -set_location_assignment PIN_8 -to io_usb_miosi[3] -set_location_assignment PIN_10 -to io_usb_miosi[0] -set_location_assignment PIN_11 -to io_usb_miosi[1] -set_location_assignment PIN_12 -to i_uart_rxd -set_location_assignment PIN_13 -to o_uart_txd -set_location_assignment PIN_17 -to o_led -set_location_assignment PIN_21 -to o_rtc_scl -set_location_assignment PIN_22 -to io_rtc_sda -set_location_assignment PIN_24 -to io_n64_si_dq -set_location_assignment PIN_25 -to i_n64_nmi -set_location_assignment PIN_26 -to i_clk -set_location_assignment PIN_27 -to i_n64_reset -set_location_assignment PIN_28 -to i_n64_si_clk -set_location_assignment PIN_32 -to io_n64_pi_ad[7] -set_location_assignment PIN_33 -to io_n64_pi_ad[8] -set_location_assignment PIN_38 -to io_n64_pi_ad[6] -set_location_assignment PIN_39 -to io_n64_pi_ad[9] -set_location_assignment PIN_41 -to io_n64_pi_ad[5] -set_location_assignment PIN_43 -to io_n64_pi_ad[10] -set_location_assignment PIN_44 -to io_n64_pi_ad[4] -set_location_assignment PIN_45 -to io_n64_pi_ad[11] -set_location_assignment PIN_46 -to i_n64_pi_aleh -set_location_assignment PIN_47 -to i_n64_pi_read -set_location_assignment PIN_48 -to i_n64_pi_write -set_location_assignment PIN_50 -to i_n64_pi_alel -set_location_assignment PIN_52 -to io_n64_pi_ad[12] -set_location_assignment PIN_54 -to io_n64_pi_ad[3] -set_location_assignment PIN_55 -to io_n64_pi_ad[13] -set_location_assignment PIN_56 -to io_n64_pi_ad[2] -set_location_assignment PIN_57 -to io_n64_pi_ad[14] -set_location_assignment PIN_58 -to io_n64_pi_ad[1] -set_location_assignment PIN_59 -to io_n64_pi_ad[15] -set_location_assignment PIN_60 -to io_n64_pi_ad[0] -set_location_assignment PIN_61 -to o_sdram_a[4] -set_location_assignment PIN_62 -to o_sdram_a[5] -set_location_assignment PIN_64 -to o_sdram_a[6] -set_location_assignment PIN_65 -to o_sdram_a[7] -set_location_assignment PIN_66 -to o_sdram_a[8] -set_location_assignment PIN_69 -to o_sdram_a[9] -set_location_assignment PIN_70 -to o_sdram_a[11] -set_location_assignment PIN_74 -to o_sdram_a[12] -set_location_assignment PIN_75 -to o_sdram_clk -set_location_assignment PIN_76 -to o_sdram_a[3] -set_location_assignment PIN_77 -to o_sdram_a[2] -set_location_assignment PIN_78 -to o_sdram_a[1] -set_location_assignment PIN_79 -to o_sdram_a[0] -set_location_assignment PIN_80 -to o_sdram_a[10] -set_location_assignment PIN_81 -to o_sdram_ba[1] -set_location_assignment PIN_84 -to o_sdram_ba[0] -set_location_assignment PIN_85 -to o_sdram_cs -set_location_assignment PIN_86 -to o_sdram_ras -set_location_assignment PIN_87 -to o_sdram_cas -set_location_assignment PIN_88 -to o_sdram_we -set_location_assignment PIN_89 -to io_sdram_dq[7] -set_location_assignment PIN_90 -to io_sdram_dq[6] -set_location_assignment PIN_91 -to io_sdram_dq[5] -set_location_assignment PIN_92 -to io_sdram_dq[4] -set_location_assignment PIN_93 -to io_sdram_dq[3] -set_location_assignment PIN_96 -to io_sdram_dq[2] -set_location_assignment PIN_97 -to io_sdram_dq[1] -set_location_assignment PIN_98 -to io_sdram_dq[0] -set_location_assignment PIN_99 -to io_sdram_dq[8] -set_location_assignment PIN_100 -to io_sdram_dq[9] -set_location_assignment PIN_101 -to io_sdram_dq[10] -set_location_assignment PIN_102 -to io_sdram_dq[11] -set_location_assignment PIN_105 -to io_sdram_dq[12] -set_location_assignment PIN_106 -to io_sdram_dq[13] -set_location_assignment PIN_110 -to io_sdram_dq[14] -set_location_assignment PIN_111 -to io_sdram_dq[15] -set_location_assignment PIN_112 -to io_sd_dat[1] -set_location_assignment PIN_113 -to io_sd_dat[0] -set_location_assignment PIN_114 -to o_sd_clk -set_location_assignment PIN_118 -to io_sd_cmd -set_location_assignment PIN_119 -to io_sd_dat[3] -set_location_assignment PIN_120 -to io_sd_dat[2] -set_location_assignment PIN_123 -to o_n64_irq -set_location_assignment PIN_138 -to i_usb_pwren -set_location_assignment PIN_140 -to o_usb_cs -set_location_assignment PIN_141 -to i_usb_miso - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON - -# Compiler Assignments -# ==================== -set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "MAX 10" -set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name PROJECT_IP_REGENERATION_POLICY ALWAYS_REGENERATE_IP -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 -set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name TOP_LEVEL_ENTITY SummerCart64 - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE 10M08SCE144C8G -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" - -# Assembler Assignments -# ===================== -set_global_assignment -name ENABLE_OCT_DONE OFF -set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# -------------------------- -# start ENTITY(SummerCart64) - - # Pin & Location Assignments - # ========================== - set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_usb_miosi[*] - set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_uart_rxd - set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_rtc_sda - set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_n64_si_dq - set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_nmi - set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_reset - set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_si_clk - set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_n64_pi_ad[*] - set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_pi_aleh - set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_pi_read - set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_pi_write - set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_pi_alel - set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_sdram_dq[*] - set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_sd_* - set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_usb_pwren - set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_usb_miso - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_usb_clk - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_usb_miosi[*] - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_uart_txd - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_rtc_scl - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_rtc_sda - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_n64_pi_ad[*] - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_sdram_* - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_sdram_dq[*] - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_sd_clk - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_sd_* - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_usb_cs - set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to io_usb_miosi[*] - set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to io_n64_pi_ad[*] - set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to io_sdram_dq[*] - set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to io_sd_* - set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to io_rtc_sda - - # Fitter Assignments - # ================== - set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_usb_miosi[*] - set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_nmi - set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_uart_rxd - set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_n64_si_dq - set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_reset - set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_si_clk - set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_aleh - set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_read - set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_write - set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_alel - set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to o_n64_irq - set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_usb_pwren - set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_usb_miso - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(SummerCart64) -# ------------------------ \ No newline at end of file diff --git a/fw/SummerCart64.sdc b/fw/SummerCart64.sdc deleted file mode 100644 index 530e475..0000000 --- a/fw/SummerCart64.sdc +++ /dev/null @@ -1,81 +0,0 @@ -# Clocks - -derive_pll_clocks -create_base_clocks - -set sys_clk {system_inst|intel_pll_inst|altpll_component|auto_generated|pll1|clk[0]} -set sdram_pll_clk {system_inst|intel_pll_inst|altpll_component|auto_generated|pll1|clk[1]} -# set sd_reg_clk {sd_interface_inst|sd_clk_inst|o_sd_clk|q} - -create_generated_clock -name sdram_clk -source [get_pins $sdram_pll_clk] [get_ports {o_sdram_clk}] -# create_generated_clock -name sd_reg_clk -source [get_pins {sd_interface_inst|sd_clk_inst|o_sd_clk|clk}] -divide_by 2 [get_pins $sd_reg_clk] -# create_generated_clock -name sd_clk -source [get_pins $sd_reg_clk] [get_ports {o_sd_clk}] - -create_generated_clock -name flash_se_neg_reg \ - -source [get_pins -compatibility_mode {*altera_onchip_flash:*onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|clk}] \ - -divide_by 2 \ - [get_pins -compatibility_mode {*altera_onchip_flash:*onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|q}] - -derive_clock_uncertainty - - -# SDRAM timings - -set sdram_outputs {o_sdram_cs o_sdram_ras o_sdram_cas o_sdram_we o_sdram_a[*] o_sdram_ba[*] io_sdram_dq[*]} -set sdram_inputs {io_sdram_dq[*]} - -set_output_delay -clock [get_clocks {sdram_clk}] -max 1.5 [get_ports $sdram_outputs] -set_output_delay -clock [get_clocks {sdram_clk}] -min -0.8 [get_ports $sdram_outputs] - -set_input_delay -clock [get_clocks {sdram_clk}] -max 5.4 [get_ports $sdram_inputs] -set_input_delay -clock [get_clocks {sdram_clk}] -min 2.5 [get_ports $sdram_inputs] - -set_multicycle_path -setup -end 2 -from [get_clocks {sdram_clk}] -to [get_clocks $sys_clk] - - -# SD card timings - -# set_output_delay -clock [get_clocks {sd_clk}] -max 6.0 [get_ports {io_sd_cmd io_sd_dat[*]}] -# set_output_delay -clock [get_clocks {sd_clk}] -min -2.0 [get_ports {io_sd_cmd io_sd_dat[*]}] - -# set_input_delay -clock [get_clocks {sd_clk}] -max 15.0 [get_ports {io_sd_cmd io_sd_dat[*]}] -# set_input_delay -clock [get_clocks {sd_clk}] -min 6.5 [get_ports {io_sd_cmd io_sd_dat[*]}] - -# set_multicycle_path -hold -start 1 -from [get_clocks $sys_clk] -to [get_clocks {sd_clk}] - -# set_multicycle_path -setup -end 3 -from [get_clocks {sd_clk}] -to [get_clocks $sys_clk] -# set_multicycle_path -hold -end 1 -from [get_clocks {sd_clk}] -to [get_clocks $sys_clk] - - -# FT1248 timings - -set_false_path -to [get_ports {o_usb_clk io_usb_miosi[*] o_usb_cs}] -set_false_path -from [get_ports {io_usb_miosi[*] i_usb_miso i_usb_pwren}] - - -# N64, PI and SI timings - -set_false_path -to [get_ports {o_n64_irq}] -set_false_path -from [get_ports {i_n64_reset i_n64_nmi}] - -set_false_path -to [get_ports {io_n64_pi_ad[*]}] -set_false_path -from [get_ports {i_n64_pi_* io_n64_pi_ad[*]}] - -set_false_path -to [get_ports {io_n64_si_dq}] -set_false_path -from [get_ports {i_n64_si_clk io_n64_si_dq}] - - -# LED timings - -set_false_path -to [get_ports {o_led}] - - -# UART timings - -set_false_path -to [get_ports {o_uart_txd}] -set_false_path -from [get_ports {i_uart_rxd}] - - -# I2C timings - -set_false_path -to [get_ports {o_rtc_scl io_rtc_sda}] -set_false_path -from [get_ports {io_rtc_sda}] diff --git a/hw/ftdi-template.xml b/fw/ftdi/ft232h_config.xml similarity index 55% rename from hw/ftdi-template.xml rename to fw/ftdi/ft232h_config.xml index 50922cc..30ed587 100644 Binary files a/hw/ftdi-template.xml and b/fw/ftdi/ft232h_config.xml differ diff --git a/fw/picorv32 b/fw/picorv32 deleted file mode 160000 index f9b1beb..0000000 --- a/fw/picorv32 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit f9b1beb4cfd6b382157b54bc8f38c61d5ae7d785 diff --git a/fw/project/lcmxo2/.gitignore b/fw/project/lcmxo2/.gitignore new file mode 100644 index 0000000..aa4d819 --- /dev/null +++ b/fw/project/lcmxo2/.gitignore @@ -0,0 +1,17 @@ +.recovery +*.dir/ +*.ccl +*.dmp +*.html +*.ini +*.rva +*.rvl +*.rvs +*.svf +*.tcl +*.tpf +*.trc +*.xml +impl*/ + +!build.tcl diff --git a/fw/project/lcmxo2/build.sh b/fw/project/lcmxo2/build.sh new file mode 100755 index 0000000..35a8b44 --- /dev/null +++ b/fw/project/lcmxo2/build.sh @@ -0,0 +1,5 @@ +#!/bin/bash + +source $bindir/diamond_env + +diamondc build.tcl diff --git a/fw/project/lcmxo2/build.tcl b/fw/project/lcmxo2/build.tcl new file mode 100644 index 0000000..3dba79f --- /dev/null +++ b/fw/project/lcmxo2/build.tcl @@ -0,0 +1,2 @@ +prj_project open sc64.ldf +prj_run Export -impl impl1 -task Jedecgen diff --git a/fw/project/lcmxo2/debug.sty b/fw/project/lcmxo2/debug.sty new file mode 100644 index 0000000..e2e20d6 --- /dev/null +++ b/fw/project/lcmxo2/debug.sty @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fw/project/lcmxo2/release.sty b/fw/project/lcmxo2/release.sty new file mode 100644 index 0000000..3408612 --- /dev/null +++ b/fw/project/lcmxo2/release.sty @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fw/project/lcmxo2/sc64.ldf b/fw/project/lcmxo2/sc64.ldf new file mode 100644 index 0000000..d9473c2 --- /dev/null +++ b/fw/project/lcmxo2/sc64.ldf @@ -0,0 +1,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fw/project/lcmxo2/sc64.lpf b/fw/project/lcmxo2/sc64.lpf new file mode 100644 index 0000000..dfc6bdd --- /dev/null +++ b/fw/project/lcmxo2/sc64.lpf @@ -0,0 +1,209 @@ +RVL_ALIAS "clk" "clk"; +BANK 0 VCCIO 3.3 V; +BANK 1 VCCIO 3.3 V; +BANK 2 VCCIO 3.3 V; +BANK 3 VCCIO 3.3 V; +BANK 4 VCCIO 3.3 V; +BANK 5 VCCIO 3.3 V; +BLOCK ASYNCPATHS ; +BLOCK JTAGPATHS ; +BLOCK PATH FROM PORT "button" ; +BLOCK RESETPATHS ; +IOBUF ALLPORTS IO_TYPE=LVCMOS33 ; +IOBUF PORT "button" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "flash_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "flash_cs" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "flash_dq[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "flash_dq[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "flash_dq[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "flash_dq[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "inclk" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "mcu_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "mcu_cs" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "mcu_int" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "mcu_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "mcu_mosi" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "n64_irq" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_nmi" PULLMODE=DOWN IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_ad[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_ad[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_ad[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_ad[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_ad[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_ad[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_ad[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_ad[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_ad[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_ad[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_ad[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_ad[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_ad[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_ad[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_ad[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_ad[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_aleh" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_alel" PULLMODE=DOWN IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_read" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_pi_write" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_reset" PULLMODE=DOWN IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_si_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 ; +IOBUF PORT "n64_si_dq" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "sd_dat[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "sd_dat[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "sd_dat[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "sd_dat[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "sd_det" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_cas" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_cs" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_dq[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_dq[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_dq[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_dq[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_dq[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_dq[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_dq[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_dq[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_dq[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_dq[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_dq[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_dq[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_dq[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_dq[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_dq[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_dq[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_ras" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "sdram_we" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "usb_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "usb_cs" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "usb_miosi[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "usb_miosi[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "usb_miosi[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "usb_miosi[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "usb_miosi[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "usb_miosi[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "usb_miosi[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "usb_miosi[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "usb_miso" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +IOBUF PORT "usb_pwrsav" PULLMODE=NONE IO_TYPE=LVCMOS33 ; +LOCATE COMP "button" SITE "1" ; +LOCATE COMP "flash_clk" SITE "142" ; +LOCATE COMP "flash_cs" SITE "138" ; +LOCATE COMP "flash_dq[0]" SITE "141" ; +LOCATE COMP "flash_dq[1]" SITE "139" ; +LOCATE COMP "flash_dq[2]" SITE "140" ; +LOCATE COMP "flash_dq[3]" SITE "143" ; +LOCATE COMP "inclk" SITE "3" ; +LOCATE COMP "mcu_clk" SITE "121" ; +LOCATE COMP "mcu_cs" SITE "122" ; +LOCATE COMP "mcu_int" SITE "117" ; +LOCATE COMP "mcu_miso" SITE "119" ; +LOCATE COMP "mcu_mosi" SITE "120" ; +LOCATE COMP "n64_irq" SITE "32" ; +LOCATE COMP "n64_nmi" SITE "28" ; +LOCATE COMP "n64_pi_ad[0]" SITE "60" ; +LOCATE COMP "n64_pi_ad[1]" SITE "58" ; +LOCATE COMP "n64_pi_ad[10]" SITE "42" ; +LOCATE COMP "n64_pi_ad[11]" SITE "44" ; +LOCATE COMP "n64_pi_ad[12]" SITE "52" ; +LOCATE COMP "n64_pi_ad[13]" SITE "55" ; +LOCATE COMP "n64_pi_ad[14]" SITE "57" ; +LOCATE COMP "n64_pi_ad[15]" SITE "59" ; +LOCATE COMP "n64_pi_ad[2]" SITE "56" ; +LOCATE COMP "n64_pi_ad[3]" SITE "54" ; +LOCATE COMP "n64_pi_ad[4]" SITE "45" ; +LOCATE COMP "n64_pi_ad[5]" SITE "43" ; +LOCATE COMP "n64_pi_ad[6]" SITE "40" ; +LOCATE COMP "n64_pi_ad[7]" SITE "38" ; +LOCATE COMP "n64_pi_ad[8]" SITE "39" ; +LOCATE COMP "n64_pi_ad[9]" SITE "41" ; +LOCATE COMP "n64_pi_aleh" SITE "48" ; +LOCATE COMP "n64_pi_alel" SITE "50" ; +LOCATE COMP "n64_pi_read" SITE "47" ; +LOCATE COMP "n64_pi_write" SITE "49" ; +LOCATE COMP "n64_reset" SITE "31" ; +LOCATE COMP "n64_si_clk" SITE "33" ; +LOCATE COMP "n64_si_dq" SITE "27" ; +LOCATE COMP "sd_clk" SITE "111" ; +LOCATE COMP "sd_cmd" SITE "112" ; +LOCATE COMP "sd_dat[0]" SITE "110" ; +LOCATE COMP "sd_dat[1]" SITE "109" ; +LOCATE COMP "sd_dat[2]" SITE "114" ; +LOCATE COMP "sd_dat[3]" SITE "113" ; +LOCATE COMP "sd_det" SITE "115" ; +LOCATE COMP "sdram_a[0]" SITE "85" ; +LOCATE COMP "sdram_a[1]" SITE "86" ; +LOCATE COMP "sdram_a[10]" SITE "84" ; +LOCATE COMP "sdram_a[11]" SITE "63" ; +LOCATE COMP "sdram_a[12]" SITE "62" ; +LOCATE COMP "sdram_a[2]" SITE "87" ; +LOCATE COMP "sdram_a[3]" SITE "89" ; +LOCATE COMP "sdram_a[4]" SITE "71" ; +LOCATE COMP "sdram_a[5]" SITE "70" ; +LOCATE COMP "sdram_a[6]" SITE "69" ; +LOCATE COMP "sdram_a[7]" SITE "68" ; +LOCATE COMP "sdram_a[8]" SITE "67" ; +LOCATE COMP "sdram_a[9]" SITE "65" ; +LOCATE COMP "sdram_ba[0]" SITE "92" ; +LOCATE COMP "sdram_ba[1]" SITE "91" ; +LOCATE COMP "sdram_cas" SITE "95" ; +LOCATE COMP "sdram_clk" SITE "61" ; +LOCATE COMP "sdram_cs" SITE "93" ; +LOCATE COMP "sdram_dq[0]" SITE "107" ; +LOCATE COMP "sdram_dq[1]" SITE "106" ; +LOCATE COMP "sdram_dq[10]" SITE "76" ; +LOCATE COMP "sdram_dq[11]" SITE "77" ; +LOCATE COMP "sdram_dq[12]" SITE "78" ; +LOCATE COMP "sdram_dq[13]" SITE "81" ; +LOCATE COMP "sdram_dq[14]" SITE "82" ; +LOCATE COMP "sdram_dq[15]" SITE "83" ; +LOCATE COMP "sdram_dq[2]" SITE "105" ; +LOCATE COMP "sdram_dq[3]" SITE "104" ; +LOCATE COMP "sdram_dq[4]" SITE "103" ; +LOCATE COMP "sdram_dq[5]" SITE "100" ; +LOCATE COMP "sdram_dq[6]" SITE "99" ; +LOCATE COMP "sdram_dq[7]" SITE "98" ; +LOCATE COMP "sdram_dq[8]" SITE "74" ; +LOCATE COMP "sdram_dq[9]" SITE "75" ; +LOCATE COMP "sdram_dqm[0]" SITE "97" ; +LOCATE COMP "sdram_dqm[1]" SITE "73" ; +LOCATE COMP "sdram_ras" SITE "94" ; +LOCATE COMP "sdram_we" SITE "96" ; +LOCATE COMP "usb_clk" SITE "12" ; +LOCATE COMP "usb_cs" SITE "11" ; +LOCATE COMP "usb_miosi[0]" SITE "22" ; +LOCATE COMP "usb_miosi[1]" SITE "21" ; +LOCATE COMP "usb_miosi[2]" SITE "20" ; +LOCATE COMP "usb_miosi[3]" SITE "19" ; +LOCATE COMP "usb_miosi[4]" SITE "17" ; +LOCATE COMP "usb_miosi[5]" SITE "15" ; +LOCATE COMP "usb_miosi[6]" SITE "14" ; +LOCATE COMP "usb_miosi[7]" SITE "13" ; +LOCATE COMP "usb_miso" SITE "10" ; +LOCATE COMP "usb_pwrsav" SITE "2" ; +SYSCONFIG SDM_PORT=DISABLE ; +VOLTAGE 3.300 V; +FREQUENCY NET "clk" 100.000000 MHz PAR_ADJ 10.000000 ; +BLOCK PATH TO PORT "mcu_int" ; +BLOCK PATH TO PORT "n64_irq" ; +BLOCK PATH FROM PORT "usb_pwrsav" ; +BLOCK PATH FROM PORT "sd_det" ; diff --git a/fw/rtl/SummerCart64.sv b/fw/rtl/SummerCart64.sv deleted file mode 100644 index cb164c7..0000000 --- a/fw/rtl/SummerCart64.sv +++ /dev/null @@ -1,154 +0,0 @@ -module SummerCart64 ( - input i_clk, - - input i_n64_reset, - input i_n64_nmi, - output o_n64_irq, - - input i_n64_pi_alel, - input i_n64_pi_aleh, - input i_n64_pi_read, - input i_n64_pi_write, - inout [15:0] io_n64_pi_ad, - - input i_n64_si_clk, - inout io_n64_si_dq, - - output o_sdram_clk, - output o_sdram_cs, - output o_sdram_ras, - output o_sdram_cas, - output o_sdram_we, - output [1:0] o_sdram_ba, - output [12:0] o_sdram_a, - inout [15:0] io_sdram_dq, - - output o_rtc_scl, - inout io_rtc_sda, - - output o_usb_clk, - output o_usb_cs, - input i_usb_miso, - inout [3:0] io_usb_miosi, - input i_usb_pwren, - - input i_uart_rxd, - output o_uart_txd, - - output o_sd_clk, - inout io_sd_cmd, - inout [3:0] io_sd_dat, - - output o_led -); - - logic [7:0] gpio_o; - logic [7:0] gpio_i; - logic [7:0] gpio_oe; - - logic dd_interrupt; - - if_system sys ( - .in_clk(i_clk), - .n64_reset(i_n64_reset), - .n64_nmi(i_n64_nmi) - ); - - if_config cfg (); - - if_dma dma (); - - if_sdram sdram (); - - if_flashram flashram (); - - if_si si (); - - if_flash flash (); - - if_dd dd ( - .dd_interrupt(dd_interrupt) - ); - - system system_inst ( - .sys(sys) - ); - - intel_gpio_ddro sdram_clk_ddro ( - .outclock(sys.sdram.sdram_clk), - .din({1'b0, 1'b1}), - .pad_out(o_sdram_clk) - ); - - n64_soc n64_soc_inst ( - .sys(sys), - .cfg(cfg), - .dma(dma), - .sdram(sdram), - .flashram(flashram), - .si(si), - .flash(flash), - .dd(dd), - - .n64_pi_alel(i_n64_pi_alel), - .n64_pi_aleh(i_n64_pi_aleh), - .n64_pi_read(i_n64_pi_read), - .n64_pi_write(i_n64_pi_write), - .n64_pi_ad(io_n64_pi_ad), - - .n64_si_clk(i_n64_si_clk), - .n64_si_dq(io_n64_si_dq), - - .sdram_cs(o_sdram_cs), - .sdram_ras(o_sdram_ras), - .sdram_cas(o_sdram_cas), - .sdram_we(o_sdram_we), - .sdram_ba(o_sdram_ba), - .sdram_a(o_sdram_a), - .sdram_dq(io_sdram_dq) - ); - - cpu_soc cpu_soc_inst ( - .sys(sys), - .cfg(cfg), - .dma(dma), - .sdram(sdram), - .flashram(flashram), - .si(si), - .flash(flash), - .dd(dd), - - .gpio_o(gpio_o), - .gpio_i(gpio_i), - .gpio_oe(gpio_oe), - - .i2c_scl(o_rtc_scl), - .i2c_sda(io_rtc_sda), - - .usb_clk(o_usb_clk), - .usb_cs(o_usb_cs), - .usb_miso(i_usb_miso), - .usb_miosi(io_usb_miosi), - .usb_pwren(i_usb_pwren), - - .uart_rxd(i_uart_rxd), - .uart_txd(o_uart_txd), - - .sd_clk(o_sd_clk), - .sd_cmd(io_sd_cmd), - .sd_dat(io_sd_dat) - ); - - always_comb begin - o_n64_irq = dd_interrupt ? 1'b0 : 1'bZ; - end - - always_comb begin - o_led = gpio_oe[0] ? gpio_o[0] : 1'bZ; - end - - always_ff @(posedge sys.clk) begin - gpio_i <= {4'b0000, i_n64_nmi, i_n64_reset, gpio_o[1:0]}; - end - -endmodule diff --git a/fw/rtl/cpu/cpu_bus.sv b/fw/rtl/cpu/cpu_bus.sv deleted file mode 100644 index 13579af..0000000 --- a/fw/rtl/cpu/cpu_bus.sv +++ /dev/null @@ -1,54 +0,0 @@ -interface if_cpu_bus (); - - localparam [3:0] NUM_DEVICES = sc64::__ID_CPU_END; - - logic request; - logic ack; - logic [3:0] wmask; - logic [31:0] address; - logic [31:0] wdata; - logic [31:0] rdata; - - logic device_ack [(NUM_DEVICES - 1):0]; - logic [31:0] device_rdata [(NUM_DEVICES - 1):0]; - - always_comb begin - ack = 1'b0; - rdata = 32'd0; - - for (integer i = 0; i < NUM_DEVICES; i++) begin - ack = ack | device_ack[i]; - rdata = rdata | device_rdata[i]; - end - end - - modport cpu ( - output request, - input ack, - output wmask, - output address, - output wdata, - input rdata - ); - - genvar n; - generate - for (n = 0; n < NUM_DEVICES; n++) begin : at - logic device_request; - - always_comb begin - device_request = request && address[31:28] == n[3:0]; - end - - modport device ( - input .request(device_request), - output .ack(device_ack[n]), - input .wmask(wmask), - input .address(address), - input .wdata(wdata), - output .rdata(device_rdata[n]) - ); - end - endgenerate - -endinterface diff --git a/fw/rtl/cpu/cpu_cfg.sv b/fw/rtl/cpu/cpu_cfg.sv deleted file mode 100644 index cf45e77..0000000 --- a/fw/rtl/cpu/cpu_cfg.sv +++ /dev/null @@ -1,164 +0,0 @@ -module cpu_cfg ( - if_system.sys sys, - if_cpu_bus bus, - if_config.cpu cfg -); - - logic skip_bootloader; - logic trigger_reconfiguration; - - typedef enum bit [2:0] { - R_SCR, - R_DDIPL_OFFSET, - R_SAVE_OFFSET, - R_COMMAND, - R_DATA_0, - R_DATA_1, - R_VERSION, - R_RECONFIGURE - } e_reg_id; - - const logic [31:0] RECONFIGURE_MAGIC = 32'h52535446; - - always_ff @(posedge sys.clk) begin - bus.ack <= 1'b0; - if (bus.request) begin - bus.ack <= 1'b1; - end - end - - always_comb begin - bus.rdata = 32'd0; - if (bus.ack) begin - case (bus.address[4:2]) - R_SCR: bus.rdata = { - cfg.cpu_ready, - cfg.cpu_busy, - 1'b0, - cfg.cmd_error, - 21'd0, - skip_bootloader, - cfg.flashram_enabled, - cfg.sram_banked, - cfg.sram_enabled, - cfg.dd_enabled, - cfg.sdram_writable, - cfg.sdram_switch - }; - R_DDIPL_OFFSET: bus.rdata = {6'd0, cfg.ddipl_offset}; - R_SAVE_OFFSET: bus.rdata = {6'd0, cfg.save_offset}; - R_COMMAND: bus.rdata = {24'd0, cfg.cmd}; - R_DATA_0: bus.rdata = cfg.data[0]; - R_DATA_1: bus.rdata = cfg.data[1]; - R_VERSION: bus.rdata = sc64::SC64_VER; - R_RECONFIGURE: bus.rdata = RECONFIGURE_MAGIC; - default: bus.rdata = 32'd0; - endcase - end - end - - always_comb begin - cfg.wdata = bus.wdata; - cfg.data_write = 2'b00; - if (bus.request && (&bus.wmask)) begin - cfg.data_write[0] = bus.address[4:2] == R_DATA_0; - cfg.data_write[1] = bus.address[4:2] == R_DATA_1; - end - end - - always_ff @(posedge sys.clk) begin - if (sys.reset) begin - cfg.cpu_ready <= 1'b0; - cfg.cpu_busy <= 1'b0; - cfg.cmd_error <= 1'b0; - cfg.sdram_switch <= 1'b0; - cfg.sdram_writable <= 1'b0; - cfg.dd_enabled <= 1'b0; - cfg.sram_enabled <= 1'b0; - cfg.sram_banked <= 1'b0; - cfg.flashram_enabled <= 1'b0; - cfg.ddipl_offset <= 26'h3BE_0000; - cfg.save_offset <= 26'h3FE_0000; - skip_bootloader <= 1'b0; - trigger_reconfiguration <= 1'b0; - end else begin - if (sys.n64_soft_reset) begin - cfg.sdram_switch <= skip_bootloader; - cfg.sdram_writable <= 1'b0; - end - if (cfg.cmd_request) begin - cfg.cpu_busy <= 1'b1; - end - if (bus.request) begin - case (bus.address[4:2]) - R_SCR: begin - if (bus.wmask[3]) begin - { - cfg.cpu_ready, - cfg.cpu_busy, - cfg.cmd_error - } <= {bus.wdata[31:30], bus.wdata[28]}; - end - if (bus.wmask[0]) begin - { - skip_bootloader, - cfg.flashram_enabled, - cfg.sram_banked, - cfg.sram_enabled, - cfg.dd_enabled, - cfg.sdram_writable, - cfg.sdram_switch - } <= bus.wdata[6:0]; - end - end - - R_DDIPL_OFFSET: begin - if (&bus.wmask) begin - cfg.ddipl_offset <= bus.wdata[25:0]; - end - end - - R_SAVE_OFFSET: begin - if (&bus.wmask) begin - cfg.save_offset <= bus.wdata[25:0]; - end - end - - R_RECONFIGURE: begin - if (&bus.wmask && bus.wdata == RECONFIGURE_MAGIC) begin - trigger_reconfiguration <= 1'b1; - end - end - endcase - end - end - end - - logic [1:0] ru_clk; - logic ru_rconfig; - logic ru_regout; - - always_ff @(posedge sys.clk) begin - if (sys.reset) begin - ru_clk <= 2'd0; - ru_rconfig <= 1'b0; - end else begin - ru_clk <= ru_clk + 1'd1; - - if (ru_clk == 2'd1) begin - ru_rconfig <= trigger_reconfiguration; - end - end - end - - fiftyfivenm_rublock fiftyfivenm_rublock_inst ( - .clk(ru_clk[1]), - .shiftnld(1'b0), - .captnupdt(1'b0), - .regin(1'b0), - .rsttimer(1'b0), - .rconfig(ru_rconfig), - .regout(ru_regout) - ); - -endmodule diff --git a/fw/rtl/cpu/cpu_dd.sv b/fw/rtl/cpu/cpu_dd.sv deleted file mode 100644 index f4227d2..0000000 --- a/fw/rtl/cpu/cpu_dd.sv +++ /dev/null @@ -1,141 +0,0 @@ -module cpu_dd ( - if_system.sys sys, - if_cpu_bus bus, - if_dd.cpu dd -); - - const bit [8:0] M_SECTOR_BUFFER = 9'h100; - - logic bm_ack; - logic [31:0] seek_timer; - - typedef enum bit [2:0] { - R_SCR, - R_CMD_DATA, - R_HEAD_TRACK, - R_SECTOR_INFO, - R_DRIVE_ID, - R_SEEK_TIMER - } e_reg_id; - - always_ff @(posedge sys.clk) begin - bus.ack <= 1'b0; - if (bus.request) begin - bus.ack <= 1'b1; - end - end - - always_comb begin - bus.rdata = 32'd0; - if (bus.ack) begin - if (bus.address[8] == M_SECTOR_BUFFER[8]) begin - bus.rdata = { - dd.sector_rdata[7:0], - dd.sector_rdata[15:8], - dd.sector_rdata[23:16], - dd.sector_rdata[31:24] - }; - end else begin - case (bus.address[5:2]) - R_SCR: bus.rdata = { - 14'd0, - bm_ack, - dd.bm_micro_error, - dd.bm_transfer_c2, - dd.bm_transfer_data, - dd.bm_transfer_blocks, - dd.bm_transfer_mode, - 1'b0, - dd.bm_stop_pending, - 1'b0, - dd.bm_start_pending, - dd.disk_changed, - dd.disk_inserted, - 1'b0, - dd.bm_pending, - 1'b0, - dd.cmd_pending, - 1'b0, - dd.hard_reset - }; - R_CMD_DATA: bus.rdata = {8'd0, dd.cmd, dd.data}; - R_HEAD_TRACK: bus.rdata = {18'd0, dd.index_lock, dd.head_track}; - R_SECTOR_INFO: bus.rdata = { - dd.sectors_in_block, - dd.sector_size_full, - dd.sector_size, - dd.sector_num - }; - R_DRIVE_ID: bus.rdata = {dd.drive_id}; - R_SEEK_TIMER: bus.rdata = seek_timer; - default: bus.rdata = 32'd0; - endcase - end - end - end - - always_comb begin - dd.sector_address = bus.address[7:2]; - dd.sector_address_valid = bus.request && bus.address[8] == M_SECTOR_BUFFER[8]; - dd.sector_write = (&bus.wmask) && dd.sector_address_valid; - dd.sector_wdata = {bus.wdata[7:0], bus.wdata[15:8], bus.wdata[23:16], bus.wdata[31:24]}; - end - - always_ff @(posedge sys.clk) begin - dd.hard_reset_clear <= 1'b0; - dd.cmd_ready <= 1'b0; - dd.bm_start_clear <= 1'b0; - dd.bm_stop_clear <= 1'b0; - dd.bm_clear <= 1'b0; - dd.bm_ready <= 1'b0; - - if (dd.bm_interrupt_ack) begin - bm_ack <= 1'b1; - end - - if (!(&seek_timer)) begin - seek_timer <= seek_timer + 1'd1; - end - - if (sys.reset) begin - bm_ack <= 1'b0; - end else begin - if (bus.request && (!bus.address[8])) begin - case (bus.address[4:2]) - R_SCR: if (&bus.wmask) begin - if (bus.wdata[20]) begin - seek_timer <= 32'd0; - end - dd.bm_clear <= bus.wdata[19]; - if (bus.wdata[18]) begin - bm_ack <= 1'b0; - end - dd.bm_micro_error <= bus.wdata[16]; - dd.bm_transfer_c2 <= bus.wdata[15]; - dd.bm_transfer_data <= bus.wdata[14]; - dd.bm_stop_clear <= bus.wdata[11]; - dd.bm_start_clear <= bus.wdata[9]; - dd.disk_changed <= bus.wdata[7]; - dd.disk_inserted <= bus.wdata[6]; - dd.bm_ready <= bus.wdata[5]; - dd.cmd_ready <= bus.wdata[3]; - dd.hard_reset_clear <= bus.wdata[1]; - end - - R_CMD_DATA: if (&bus.wmask[1:0]) begin - dd.cmd_data <= bus.wdata[15:0]; - end - - R_HEAD_TRACK: if (&bus.wmask[1:0]) begin - {dd.index_lock, dd.head_track} <= bus.wdata[13:0]; - end - - R_DRIVE_ID: if (&bus.wmask[1:0]) begin - dd.drive_id <= bus.wdata[15:0]; - end - endcase - end - end - end - -endmodule diff --git a/fw/rtl/cpu/cpu_dma.sv b/fw/rtl/cpu/cpu_dma.sv deleted file mode 100644 index 45b2989..0000000 --- a/fw/rtl/cpu/cpu_dma.sv +++ /dev/null @@ -1,222 +0,0 @@ -interface if_dma (); - - localparam [1:0] NUM_DEVICES = sc64::__ID_DMA_END; - - sc64::e_dma_id id; - - logic rx_empty; - logic rx_read; - logic [7:0] rx_rdata; - logic tx_full; - logic tx_write; - logic [7:0] tx_wdata; - - logic request; - logic ack; - logic write; - logic [31:0] address; - logic [15:0] rdata; - logic [15:0] wdata; - - modport controller ( - output id, - - input rx_empty, - output rx_read, - input rx_rdata, - input tx_full, - output tx_write, - output tx_wdata, - - output request, - input ack, - output write, - output address, - input rdata, - output wdata - ); - - modport memory ( - input request, - output ack, - input write, - input address, - output rdata, - input wdata - ); - - logic [7:0] device_rx_rdata [(NUM_DEVICES - 1):0]; - logic device_rx_empty [(NUM_DEVICES - 1):0]; - logic device_tx_full [(NUM_DEVICES - 1):0]; - - always_comb begin - rx_rdata = 8'd0; - rx_empty = 1'b0; - tx_full = 1'b0; - - for (integer i = 0; i < NUM_DEVICES; i++) begin - rx_rdata = rx_rdata | (id == i[1:0] ? device_rx_rdata[i] : 8'd0); - rx_empty = rx_empty | (device_rx_empty[i] && id == i[1:0]); - tx_full = tx_full | (device_tx_full[i] && id == i[1:0]); - end - end - - genvar n; - generate - for (n = 0; n < NUM_DEVICES; n++) begin : at - logic device_selected; - logic device_rx_read; - logic device_tx_write; - - always_comb begin - device_selected = id == n[1:0]; - device_rx_read = device_selected && rx_read; - device_tx_write = device_selected && tx_write; - end - - modport device ( - output .rx_empty(device_rx_empty[n]), - input .rx_read(device_rx_read), - output .rx_rdata(device_rx_rdata[n]), - output .tx_full(device_tx_full[n]), - input .tx_write(device_tx_write), - input .tx_wdata(tx_wdata) - ); - end - endgenerate - -endinterface - - -module cpu_dma ( - if_system.sys sys, - if_cpu_bus bus, - if_dma.controller dma -); - - typedef enum bit [2:0] { - S_IDLE, - S_FETCH, - S_TRANSFER - } e_state; - - e_state state; - logic pending_stop; - logic direction; - logic [27:0] length; - logic [15:0] rdata_buffer; - logic byte_counter; - - always_comb begin - bus.rdata = 32'd0; - if (bus.ack) begin - case (bus.address[3:2]) - 0: bus.rdata = {28'd0, state != S_IDLE, direction, 2'b00}; - 1: bus.rdata = dma.address; - 2: bus.rdata = {2'b00, dma.id, length}; - default: bus.rdata = 32'd0; - endcase - end - end - - always_ff @(posedge sys.clk) begin - bus.ack <= 1'b0; - if (bus.request) begin - bus.ack <= 1'b1; - end - - dma.rx_read <= 1'b0; - dma.tx_write <= 1'b0; - - if (sys.reset) begin - state <= S_IDLE; - pending_stop <= 1'b0; - dma.request <= 1'b0; - end else begin - if (bus.request && bus.address[3:2] == 0 && bus.wmask[0]) begin - pending_stop <= bus.wdata[1]; - end - - case (state) - S_IDLE: begin - pending_stop <= 1'b0; - - if (bus.request) begin - case (bus.address[3:2]) - 0: if (bus.wmask[0]) begin - direction <= bus.wdata[2]; - if (bus.wdata[0]) begin - state <= S_FETCH; - byte_counter <= 1'b0; - end - end - - 1: if (&bus.wmask) begin - dma.address <= bus.wdata; - end - - 2: if (&bus.wmask) begin - {dma.id, length} <= {bus.wdata[29:1], 1'b0}; - end - endcase - end - end - - S_FETCH: begin - if (length != 28'd0 && !pending_stop) begin - if (direction) begin - if (!dma.rx_empty && !dma.rx_read) begin - dma.rx_read <= 1'b1; - dma.wdata <= {dma.wdata[7:0], dma.rx_rdata}; - byte_counter <= ~byte_counter; - if (byte_counter) begin - state <= S_TRANSFER; - dma.request <= 1'b1; - dma.write <= 1'b1; - end - end - end else begin - dma.request <= 1'b1; - dma.write <= 1'b0; - if (dma.ack) begin - state <= S_TRANSFER; - dma.request <= 1'b0; - rdata_buffer <= dma.rdata; - end - end - end else begin - state <= S_IDLE; - end - end - - S_TRANSFER: begin - if (direction) begin - if (dma.ack) begin - state <= S_FETCH; - dma.request <= 1'b0; - dma.address <= dma.address + 2'd2; - length <= length - 2'd2; - end - end else begin - if (!dma.tx_full && !dma.tx_write) begin - dma.tx_write <= 1'b1; - dma.tx_wdata <= byte_counter ? rdata_buffer[7:0] : rdata_buffer[15:8]; - byte_counter <= ~byte_counter; - if (byte_counter) begin - state <= S_FETCH; - dma.address <= dma.address + 2'd2; - length <= length - 2'd2; - end - end - end - end - - default: begin - state <= S_IDLE; - dma.request <= 1'b0; - end - endcase - end - end - -endmodule diff --git a/fw/rtl/cpu/cpu_flash.sv b/fw/rtl/cpu/cpu_flash.sv deleted file mode 100644 index a7c3b6f..0000000 --- a/fw/rtl/cpu/cpu_flash.sv +++ /dev/null @@ -1,61 +0,0 @@ -interface if_flash (); - - logic request; - logic ack; - logic write; - logic [31:0] address; - logic [31:0] rdata; - logic [31:0] wdata; - - modport cpu ( - output request, - input ack, - output write, - output address, - input rdata, - output wdata - ); - - modport memory ( - input request, - output ack, - input write, - input address, - output rdata, - input wdata - ); - -endinterface - - -module cpu_flash ( - if_system.sys sys, - if_cpu_bus bus, - if_flash.cpu flash -); - - logic request; - - always_comb begin - bus.ack = flash.ack; - bus.rdata = flash.rdata; - flash.request = bus.request || request; - flash.write = &bus.wmask; - flash.address = bus.address; - flash.wdata = bus.wdata; - end - - always_ff @(posedge sys.clk) begin - if (sys.reset) begin - request <= 1'b0; - end else begin - if (bus.request) begin - request <= 1'b1; - end - if (flash.ack) begin - request <= 1'b0; - end - end - end - -endmodule diff --git a/fw/rtl/cpu/cpu_flashram.sv b/fw/rtl/cpu/cpu_flashram.sv deleted file mode 100644 index 7519811..0000000 --- a/fw/rtl/cpu/cpu_flashram.sv +++ /dev/null @@ -1,77 +0,0 @@ -interface if_flashram (); - - logic [4:0] address; - logic [31:0] rdata; - logic [9:0] sector; - logic operation_pending; - logic write_or_erase; - logic sector_or_all; - logic operation_done; - - modport cpu ( - output address, - input rdata, - input sector, - input operation_pending, - input write_or_erase, - input sector_or_all, - output operation_done - ); - - modport flashram ( - input address, - output rdata, - output sector, - output operation_pending, - output write_or_erase, - output sector_or_all, - input operation_done - ); - -endinterface - - -module cpu_flashram ( - if_system.sys sys, - if_cpu_bus bus, - if_flashram.cpu flashram -); - - always_ff @(posedge sys.clk) begin - bus.ack <= 1'b0; - if (bus.request) begin - bus.ack <= 1'b1; - end - end - - always_comb begin - bus.rdata = 32'd0; - if (bus.ack) begin - bus.rdata = { - 14'd0, - flashram.sector, - 4'd0, - flashram.sector_or_all, - flashram.write_or_erase, - 1'b0, - flashram.operation_pending - }; - if (bus.address[7]) begin - bus.rdata = {flashram.rdata[7:0], flashram.rdata[15:8], flashram.rdata[23:16], flashram.rdata[31:24]}; - end - end - - flashram.address = bus.address[6:2]; - end - - always_ff @(posedge sys.clk) begin - flashram.operation_done <= 1'b0; - - if (bus.request) begin - if (!bus.address[7] && bus.wmask[0]) begin - flashram.operation_done <= bus.wdata[1]; - end - end - end - -endmodule diff --git a/fw/rtl/cpu/cpu_gpio.sv b/fw/rtl/cpu/cpu_gpio.sv deleted file mode 100644 index 4877713..0000000 --- a/fw/rtl/cpu/cpu_gpio.sv +++ /dev/null @@ -1,42 +0,0 @@ -module cpu_gpio ( - if_system.sys sys, - if_cpu_bus bus, - - input [7:0] gpio_i, - output [7:0] gpio_o, - output [7:0] gpio_oe -); - - logic [1:0][7:0] gpio_i_ff; - logic [7:0] gpio_o_value; - logic [7:0] gpio_oe_value; - - always_ff @(posedge sys.clk) begin - bus.ack <= 1'b0; - if (bus.request) begin - bus.ack <= 1'b1; - end - end - - always_comb begin - bus.rdata = 32'd0; - if (bus.ack) begin - bus.rdata = {8'd0, gpio_oe_value, gpio_i_ff[1], gpio_o_value}; - end - end - - always_ff @(posedge sys.clk) begin - gpio_i_ff <= {gpio_i_ff[0], gpio_i}; - gpio_o <= gpio_o_value; - gpio_oe <= gpio_oe_value; - - if (sys.reset) begin - gpio_o_value <= 8'd0; - gpio_oe_value <= 8'd0; - end else if (bus.request) begin - if (bus.wmask[0]) gpio_o_value <= bus.wdata[7:0]; - if (bus.wmask[2]) gpio_oe_value <= bus.wdata[23:16]; - end - end - -endmodule diff --git a/fw/rtl/cpu/cpu_i2c.sv b/fw/rtl/cpu/cpu_i2c.sv deleted file mode 100644 index ab2c7e2..0000000 --- a/fw/rtl/cpu/cpu_i2c.sv +++ /dev/null @@ -1,155 +0,0 @@ -module cpu_i2c ( - if_system.sys sys, - if_cpu_bus bus, - - output i2c_scl, - inout i2c_sda -); - - reg [1:0] state; - reg mack; - reg [8:0] trx_data; - - always_comb begin - bus.rdata = 32'd0; - if (bus.ack) begin - case (bus.address[2]) - 0: bus.rdata = {27'd0, |state, ~trx_data[0], mack, 2'b00}; - 1: bus.rdata = {23'd0, trx_data[0], trx_data[8:1]}; - default: bus.rdata = 32'd0; - endcase - end - end - - always_ff @(posedge sys.clk) begin - bus.ack <= 1'b0; - if (bus.request) begin - bus.ack <= 1'b1; - end - - if (sys.reset) begin - mack <= 1'b0; - end else if (bus.request && bus.wmask[0] && !bus.address[2]) begin - mack <= bus.wdata[2]; - end - end - - reg [5:0] clock_div; - reg [3:0] clock_phase_gen; - - wire clock_tick = &clock_div; - wire [3:0] clock_phase = {4{clock_tick}} & clock_phase_gen; - - always_ff @(posedge sys.clk) begin - if (sys.reset) begin - clock_div <= 6'd0; - end else begin - clock_div <= clock_div + 1'd1; - end - - if (sys.reset || state == 2'd0) begin - clock_phase_gen <= 4'b0001; - end else if (clock_tick) begin - clock_phase_gen <= {clock_phase_gen[2:0], clock_phase_gen[3]}; - end - end - - reg [3:0] bit_counter; - - reg sda_i_ff1, sda_i_ff2; - reg scl_o; - reg sda_o; - - assign i2c_scl = scl_o ? 1'bZ : 1'b0; - assign i2c_sda = sda_o ? 1'bZ : 1'b0; - - always_ff @(posedge sys.clk) begin - {sda_i_ff2, sda_i_ff1} <= {sda_i_ff1, i2c_sda}; - - if (sys.reset) begin - state <= 2'd0; - scl_o <= 1'b1; - sda_o <= 1'b1; - end else begin - case (state) - 2'd0: begin - bit_counter <= 4'd0; - - if (bus.request && bus.wmask[0]) begin - case (bus.address[2]) - 0: begin - if (bus.wdata[1]) state <= 2'd2; - if (bus.wdata[0]) state <= 2'd1; - end - - 1: begin - state <= 2'd3; - trx_data <= {bus.wdata[7:0], ~mack}; - end - endcase - end - end - - 2'd1: begin - if (clock_phase[0]) begin - scl_o <= 1'b1; - sda_o <= 1'b1; - end - - if (clock_phase[1]) begin - sda_o <= 1'b0; - end - - if (clock_phase[3]) begin - state <= 2'd0; - scl_o <= 1'b0; - end - end - - 2'd2: begin - if (clock_phase[0]) begin - scl_o <= 1'b0; - sda_o <= 1'b0; - end - - if (clock_phase[1]) begin - scl_o <= 1'b1; - end - - if (clock_phase[3]) begin - state <= 2'd0; - sda_o <= 1'b1; - end - end - - 2'd3: begin - if (clock_phase[0]) begin - bit_counter <= bit_counter + 1'd1; - scl_o <= 1'b0; - sda_o <= trx_data[8]; - end - - if (clock_phase[1]) begin - scl_o <= 1'b1; - end - - if (clock_phase[3]) begin - trx_data <= {trx_data[7:0], sda_i_ff2}; - scl_o <= 1'b0; - end - - if (bit_counter == 4'b1010) begin - state <= 2'd0; - end - end - - default: begin - state <= 2'd0; - scl_o <= 1'b1; - sda_o <= 1'b1; - end - endcase - end - end - -endmodule diff --git a/fw/rtl/cpu/cpu_ram.sv b/fw/rtl/cpu/cpu_ram.sv deleted file mode 100644 index fae5dd9..0000000 --- a/fw/rtl/cpu/cpu_ram.sv +++ /dev/null @@ -1,33 +0,0 @@ -module cpu_ram ( - if_system.sys sys, - if_cpu_bus bus -); - - logic [3:0][7:0] ram [0:4095]; - logic [31:0] q; - - always_ff @(posedge sys.clk) begin - bus.ack <= 1'b0; - if (bus.request) begin - bus.ack <= 1'b1; - end - end - - always_comb begin - bus.rdata = 32'd0; - if (bus.ack) begin - bus.rdata = q; - end - end - - always_ff @(posedge sys.clk) begin - q <= ram[bus.address[13:2]]; - if (bus.request) begin - if (bus.wmask[0]) ram[bus.address[13:2]][0] <= bus.wdata[7:0]; - if (bus.wmask[1]) ram[bus.address[13:2]][1] <= bus.wdata[15:8]; - if (bus.wmask[2]) ram[bus.address[13:2]][2] <= bus.wdata[23:16]; - if (bus.wmask[3]) ram[bus.address[13:2]][3] <= bus.wdata[31:24]; - end - end - -endmodule diff --git a/fw/rtl/cpu/cpu_sdram.sv b/fw/rtl/cpu/cpu_sdram.sv deleted file mode 100644 index 6f01317..0000000 --- a/fw/rtl/cpu/cpu_sdram.sv +++ /dev/null @@ -1,76 +0,0 @@ -interface if_sdram (); - - logic request; - logic ack; - logic write; - logic [31:0] address; - logic [15:0] rdata; - logic [15:0] wdata; - - modport cpu ( - output request, - input ack, - output write, - output address, - input rdata, - output wdata - ); - - modport memory ( - input request, - output ack, - input write, - input address, - output rdata, - input wdata - ); - -endinterface - - -module cpu_sdram ( - if_system.sys sys, - if_cpu_bus bus, - if_sdram.cpu sdram -); - - logic request; - logic current_word; - logic [31:0] rdata; - - always_comb begin - bus.rdata = 32'd0; - if (bus.ack) begin - bus.rdata = {rdata[7:0], rdata[15:8], rdata[23:16], rdata[31:24]}; - end - - sdram.write = current_word ? &bus.wmask[1:0] : &bus.wmask[3:2]; - sdram.address = {1'b0, bus.address[30:2], current_word, 1'b0}; - sdram.wdata = current_word ? {bus.wdata[23:16], bus.wdata[31:24]} : {bus.wdata[7:0], bus.wdata[15:8]}; - end - - always_ff @(posedge sys.clk) begin - bus.ack <= 1'b0; - - if (sys.reset) begin - sdram.request <= 1'b0; - end else begin - if (bus.request) begin - sdram.request <= 1'b1; - current_word <= 1'b0; - end - - if (sdram.ack) begin - if (!current_word) begin - current_word <= 1'b1; - rdata[31:16] <= sdram.rdata; - end else begin - bus.ack <= 1'b1; - sdram.request <= 1'b0; - rdata[15:0] <= sdram.rdata; - end - end - end - end - -endmodule diff --git a/fw/rtl/cpu/cpu_si.sv b/fw/rtl/cpu/cpu_si.sv deleted file mode 100644 index 2197d68..0000000 --- a/fw/rtl/cpu/cpu_si.sv +++ /dev/null @@ -1,59 +0,0 @@ -module cpu_si ( - if_system.sys sys, - if_cpu_bus bus, - if_si.cpu si -); - always_ff @(posedge sys.clk) begin - bus.ack <= 1'b0; - if (bus.request) begin - bus.ack <= 1'b1; - end - end - - always_comb begin - bus.rdata = 32'd0; - if (bus.ack) begin - case (bus.address[3:2]) - 0: bus.rdata = { - 20'd0, - si.rx_length[6:3], - 4'd0, - si.tx_busy, - 1'b0, - si.rx_data[0], - si.rx_ready - }; - 1: bus.rdata = {si.rx_data[56:49], si.rx_data[64:57], si.rx_data[72:65], si.rx_data[80:73]}; - 2: bus.rdata = {si.rx_data[24:17], si.rx_data[32:25], si.rx_data[40:33], si.rx_data[48:41]}; - 3: bus.rdata = {16'd0, si.rx_data[8:1], si.rx_data[16:9]}; - default: bus.rdata = 32'd0; - endcase - end - end - - always_comb begin - si.tx_data = {bus.wdata[7:0], bus.wdata[15:8], bus.wdata[23:16], bus.wdata[31:24]}; - si.tx_length = bus.wdata[22:16]; - end - - always_ff @(posedge sys.clk) begin - si.tx_reset <= 1'b0; - si.rx_reset <= 1'b0; - si.tx_start <= 1'b0; - si.tx_wmask <= 3'b000; - - if (bus.request && (&bus.wmask)) begin - case (bus.address[3:2]) - 0: begin - si.tx_reset <= bus.wdata[7]; - si.rx_reset <= bus.wdata[6]; - si.tx_start <= bus.wdata[2]; - end - 1: si.tx_wmask[0] <= 1'b1; - 2: si.tx_wmask[1] <= 1'b1; - 3: si.tx_wmask[2] <= 1'b1; - endcase - end - end - -endmodule diff --git a/fw/rtl/cpu/cpu_soc.sv b/fw/rtl/cpu/cpu_soc.sv deleted file mode 100644 index 7a15039..0000000 --- a/fw/rtl/cpu/cpu_soc.sv +++ /dev/null @@ -1,127 +0,0 @@ -module cpu_soc ( - if_system.sys sys, - if_config.cpu cfg, - if_dma dma, - if_sdram.cpu sdram, - if_flashram.cpu flashram, - if_si.cpu si, - if_flash.cpu flash, - if_dd.cpu dd, - - input [7:0] gpio_i, - output [7:0] gpio_o, - output [7:0] gpio_oe, - - output i2c_scl, - inout i2c_sda, - - output usb_clk, - output usb_cs, - input usb_miso, - inout [3:0] usb_miosi, - input usb_pwren, - - input uart_rxd, - output uart_txd, - - output sd_clk, - inout sd_cmd, - inout [3:0] sd_dat -); - - if_cpu_bus bus (); - - cpu_wrapper cpu_wrapper_inst ( - .sys(sys), - .bus(bus) - ); - - cpu_ram cpu_ram_inst ( - .sys(sys), - .bus(bus.at[sc64::ID_CPU_RAM].device) - ); - - cpu_flash cpu_flash_inst ( - .sys(sys), - .bus(bus.at[sc64::ID_CPU_FLASH].device), - .flash(flash) - ); - - cpu_gpio cpu_gpio_inst ( - .sys(sys), - .bus(bus.at[sc64::ID_CPU_GPIO].device), - .gpio_i(gpio_i), - .gpio_o(gpio_o), - .gpio_oe(gpio_oe) - ); - - cpu_i2c cpu_i2c_inst ( - .sys(sys), - .bus(bus.at[sc64::ID_CPU_I2C].device), - .i2c_scl(i2c_scl), - .i2c_sda(i2c_sda) - ); - - cpu_usb cpu_usb_inst ( - .sys(sys), - .bus(bus.at[sc64::ID_CPU_USB].device), - .dma(dma.at[sc64::ID_DMA_USB].device), - .usb_clk(usb_clk), - .usb_cs(usb_cs), - .usb_miso(usb_miso), - .usb_miosi(usb_miosi), - .usb_pwren(usb_pwren) - ); - - generate - if (sc64::CPU_HAS_UART) begin - cpu_uart cpu_uart_inst ( - .sys(sys), - .bus(bus.at[sc64::ID_CPU_UART].device), - .uart_rxd(uart_rxd), - .uart_txd(uart_txd) - ); - end - endgenerate - - cpu_dma cpu_dma_inst ( - .sys(sys), - .bus(bus.at[sc64::ID_CPU_DMA].device), - .dma(dma) - ); - - cpu_cfg cpu_cfg_inst ( - .sys(sys), - .bus(bus.at[sc64::ID_CPU_CFG].device), - .cfg(cfg) - ); - - cpu_sdram cpu_sdram_inst ( - .sys(sys), - .bus(bus.at[sc64::ID_CPU_SDRAM].device), - .sdram(sdram) - ); - - cpu_flashram cpu_flashram_inst ( - .sys(sys), - .bus(bus.at[sc64::ID_CPU_FLASHRAM].device), - .flashram(flashram) - ); - - cpu_si cpu_si_inst ( - .sys(sys), - .bus(bus.at[sc64::ID_CPU_SI].device), - .si(si) - ); - - cpu_dd cpu_dd_inst ( - .sys(sys), - .bus(bus.at[sc64::ID_CPU_DD].device), - .dd(dd) - ); - - assign sd_clk = 1'bZ; - assign sd_cmd = 1'bZ; - assign sd_dat = 4'bZZZZ; - -endmodule diff --git a/fw/rtl/cpu/cpu_uart.sv b/fw/rtl/cpu/cpu_uart.sv deleted file mode 100644 index 6da1ed1..0000000 --- a/fw/rtl/cpu/cpu_uart.sv +++ /dev/null @@ -1,153 +0,0 @@ -module cpu_uart ( - if_system.sys sys, - if_cpu_bus bus, - - input uart_rxd, - output uart_txd -); - - localparam BAUD_GEN_VALUE = int'(sc64::CLOCK_FREQUENCY / sc64::UART_BAUD_RATE) - 1'd1; - - typedef enum bit [1:0] { - S_TRX_IDLE, - S_TRX_DATA, - S_TRX_SAMPLING_OFFSET - } e_trx_state; - - - // CPU bus controller - - e_trx_state tx_state; - e_trx_state rx_state; - logic [7:0] rx_data; - logic rx_available; - logic rx_overrun; - - always_ff @(posedge sys.clk) begin - bus.ack <= 1'b0; - if (bus.request) begin - bus.ack <= 1'b1; - end - end - - always_comb begin - bus.rdata = 32'd0; - if (bus.ack) begin - case (bus.address[2:2]) - 0: bus.rdata = {29'd0, rx_overrun, tx_state == S_TRX_IDLE, rx_available}; - 1: bus.rdata = {24'd0, rx_data}; - default: bus.rdata = 32'd0; - endcase - end - end - - - // TX path - - logic [6:0] tx_baud_counter; - logic [3:0] tx_bit_counter; - logic [9:0] tx_shifter; - - always_ff @(posedge sys.clk) begin - tx_baud_counter <= tx_baud_counter + 1'd1; - uart_txd <= tx_shifter[0]; - - if (sys.reset) begin - tx_state <= S_TRX_IDLE; - tx_shifter <= 10'h3FF; - end else begin - case (tx_state) - S_TRX_IDLE: begin - if (bus.request && bus.wmask[0] && bus.address[2]) begin - tx_state <= S_TRX_DATA; - tx_baud_counter <= 7'd0; - tx_bit_counter <= 4'd0; - tx_shifter <= {1'b1, bus.wdata[7:0], 1'b0}; - end - end - - S_TRX_DATA: begin - if (tx_baud_counter == BAUD_GEN_VALUE) begin - tx_baud_counter <= 7'd0; - tx_bit_counter <= tx_bit_counter + 1'd1; - tx_shifter <= {1'b1, tx_shifter[9:1]}; - if (tx_bit_counter == 4'd9) begin - tx_state <= S_TRX_IDLE; - end - end - end - - default: begin - tx_state <= S_TRX_IDLE; - tx_shifter <= 10'h3FF; - end - endcase - end - end - - - // RX path - - logic [6:0] rx_baud_counter; - logic [3:0] rx_bit_counter; - logic [7:0] rx_shifter; - logic [1:0] rxd_ff; - - always_ff @(posedge sys.clk) begin - rx_baud_counter <= rx_baud_counter + 1'd1; - rxd_ff <= {rxd_ff[0], uart_rxd}; - - if (bus.request && bus.wmask[0] && !bus.address[2]) begin - rx_overrun <= bus.wdata[2]; - end - if (bus.request && !bus.wmask[0] && bus.address[2]) begin - rx_available <= 1'b0; - end - - if (sys.reset) begin - rx_state <= S_TRX_IDLE; - rx_available <= 1'b0; - rx_overrun <= 1'b0; - end else begin - case (rx_state) - S_TRX_IDLE: begin - if (!rxd_ff[1]) begin - rx_state <= S_TRX_SAMPLING_OFFSET; - rx_baud_counter <= 7'd0; - rx_bit_counter <= 4'd0; - end - end - - S_TRX_SAMPLING_OFFSET: begin - if (rx_baud_counter == (BAUD_GEN_VALUE / 2)) begin - rx_state <= S_TRX_DATA; - rx_baud_counter <= 7'd0; - end - end - - S_TRX_DATA: begin - if (rx_baud_counter == BAUD_GEN_VALUE) begin - rx_baud_counter <= 7'd0; - rx_bit_counter <= rx_bit_counter + 1'd1; - rx_shifter <= {rxd_ff[1], rx_shifter[7:1]}; - if (rx_bit_counter == 4'd8) begin - rx_state <= S_TRX_IDLE; - if (rxd_ff[1]) begin - rx_data <= rx_shifter[7:0]; - rx_available <= 1'b1; - rx_overrun <= rx_available; - end - end - end - end - - default: begin - rx_state <= S_TRX_IDLE; - rx_available <= 1'b0; - rx_overrun <= 1'b0; - end - endcase - end - end - -endmodule diff --git a/fw/rtl/cpu/cpu_usb.sv b/fw/rtl/cpu/cpu_usb.sv deleted file mode 100644 index da439c2..0000000 --- a/fw/rtl/cpu/cpu_usb.sv +++ /dev/null @@ -1,119 +0,0 @@ -module cpu_usb ( - if_system sys, - if_cpu_bus bus, - if_dma dma, - - output usb_clk, - output usb_cs, - input usb_miso, - inout [3:0] usb_miosi, - input usb_pwren -); - - logic rx_flush; - logic rx_empty; - logic rx_read; - logic [7:0] rx_rdata; - - logic tx_flush; - logic tx_full; - logic tx_write; - logic [7:0] tx_wdata; - - logic rx_escape_valid; - logic rx_escape_ack; - logic [7:0] rx_escape; - - logic cpu_rx_read; - logic cpu_tx_write; - - logic usb_enabled; - - always_comb begin - dma.rx_empty = rx_empty; - rx_read = cpu_rx_read || dma.rx_read; - dma.rx_rdata = rx_rdata; - - dma.tx_full = tx_full; - tx_write = cpu_tx_write || dma.tx_write; - tx_wdata = dma.tx_write ? dma.tx_wdata : bus.wdata[7:0]; - end - - always_ff @(posedge sys.clk) begin - bus.ack <= 1'b0; - if (bus.request) begin - bus.ack <= 1'b1; - end - end - - always_comb begin - bus.rdata = 32'd0; - if (bus.ack) begin - case (bus.address[3:2]) - 0: bus.rdata = {25'd0, rx_escape_valid, usb_pwren, usb_enabled, 2'b00, ~tx_full, ~rx_empty}; - 1: bus.rdata = {24'd0, rx_rdata}; - 2: bus.rdata = {24'd0, rx_escape}; - default: bus.rdata = 32'd0; - endcase - end - end - - always_ff @(posedge sys.clk) begin - rx_flush <= 1'b0; - cpu_rx_read <= 1'b0; - - tx_flush <= 1'b0; - cpu_tx_write <= 1'b0; - - rx_escape_ack <= 1'b0; - - if (sys.reset) begin - usb_enabled <= 1'b0; - end else begin - if (bus.request) begin - case (bus.address[2:2]) - 2'd0: begin - if (bus.wmask[0]) begin - rx_escape_ack <= bus.wdata[7]; - {usb_enabled, tx_flush, rx_flush} <= bus.wdata[4:2]; - end - end - - 2'd1: begin - if (bus.wmask[0]) begin - cpu_tx_write <= 1'b1; - end else begin - cpu_rx_read <= 1'b1; - end - end - endcase - end - end - end - - usb_ft1248 usb_ft1248_inst ( - .sys(sys), - - .usb_enabled(usb_enabled), - - .usb_clk(usb_clk), - .usb_cs(usb_cs), - .usb_miso(usb_miso), - .usb_miosi(usb_miosi), - - .rx_flush(rx_flush), - .rx_empty(rx_empty), - .rx_read(rx_read), - .rx_rdata(rx_rdata), - - .tx_flush(tx_flush), - .tx_full(tx_full), - .tx_write(tx_write), - .tx_wdata(tx_wdata), - - .rx_escape_valid(rx_escape_valid), - .rx_escape_ack(rx_escape_ack), - .rx_escape(rx_escape) - ); - -endmodule diff --git a/fw/rtl/cpu/cpu_wrapper.sv b/fw/rtl/cpu/cpu_wrapper.sv deleted file mode 100644 index aaededc..0000000 --- a/fw/rtl/cpu/cpu_wrapper.sv +++ /dev/null @@ -1,49 +0,0 @@ -module cpu_wrapper ( - if_system.sys sys, - if_cpu_bus.cpu bus -); - - typedef enum bit [0:0] { - S_IDLE, - S_WAITING - } e_bus_state; - - e_bus_state state; - - logic mem_la_read; - logic mem_la_write; - - always_ff @(posedge sys.clk) begin - bus.request <= 1'b0; - if (sys.reset) begin - state <= S_IDLE; - end else begin - if (state == S_IDLE && (mem_la_read || mem_la_write)) begin - state <= S_WAITING; - bus.request <= 1'b1; - end - if (state == S_WAITING && bus.ack) begin - state <= S_IDLE; - end - end - end - - picorv32 #( - .ENABLE_COUNTERS(0), - .ENABLE_COUNTERS64(0), - .CATCH_MISALIGN(0), - .CATCH_ILLINSN(0), - .PROGADDR_RESET(sc64::CPU_RESET_VECTOR) - ) cpu_inst ( - .clk(sys.clk), - .resetn(~sys.reset), - .mem_addr(bus.address), - .mem_wdata(bus.wdata), - .mem_wstrb(bus.wmask), - .mem_ready(bus.ack), - .mem_rdata(bus.rdata), - .mem_la_read(mem_la_read), - .mem_la_write(mem_la_write) - ); - -endmodule diff --git a/fw/rtl/fifo/fifo_bus.sv b/fw/rtl/fifo/fifo_bus.sv new file mode 100644 index 0000000..80ca607 --- /dev/null +++ b/fw/rtl/fifo/fifo_bus.sv @@ -0,0 +1,37 @@ +interface fifo_bus (); + + logic rx_empty; + logic rx_almost_empty; + logic rx_read; + logic [7:0] rx_rdata; + + logic tx_full; + logic tx_almost_full; + logic tx_write; + logic [7:0] tx_wdata; + + modport controller ( + input rx_empty, + input rx_almost_empty, + output rx_read, + input rx_rdata, + + input tx_full, + input tx_almost_full, + output tx_write, + output tx_wdata + ); + + modport fifo ( + output rx_empty, + output rx_almost_empty, + input rx_read, + output rx_rdata, + + output tx_full, + output tx_almost_full, + input tx_write, + input tx_wdata + ); + +endinterface diff --git a/fw/rtl/fifo/fifo_junction.sv b/fw/rtl/fifo/fifo_junction.sv new file mode 100644 index 0000000..cd3ffdc --- /dev/null +++ b/fw/rtl/fifo/fifo_junction.sv @@ -0,0 +1,26 @@ +module fifo_junction ( + fifo_bus.controller dev_bus, + + fifo_bus.fifo cfg_bus, + fifo_bus.fifo dma_bus +); + + always_comb begin + dev_bus.rx_read = cfg_bus.rx_read || dma_bus.rx_read; + dev_bus.tx_write = cfg_bus.tx_write || dma_bus.tx_write; + dev_bus.tx_wdata = cfg_bus.tx_write ? cfg_bus.tx_wdata : dma_bus.tx_wdata; + + cfg_bus.rx_empty = dev_bus.rx_empty; + cfg_bus.rx_almost_empty = dev_bus.rx_almost_empty; + cfg_bus.rx_rdata = dev_bus.rx_rdata; + cfg_bus.tx_full = dev_bus.tx_full; + cfg_bus.tx_almost_full = dev_bus.tx_almost_full; + + dma_bus.rx_empty = dev_bus.rx_empty; + dma_bus.rx_almost_empty = dev_bus.rx_almost_empty; + dma_bus.rx_rdata = dev_bus.rx_rdata; + dma_bus.tx_full = dev_bus.tx_full; + dma_bus.tx_almost_full = dev_bus.tx_almost_full; + end + +endmodule diff --git a/fw/rtl/intel/fifo/intel_fifo_8.qip b/fw/rtl/intel/fifo/intel_fifo_8.qip deleted file mode 100644 index f252a4d..0000000 --- a/fw/rtl/intel/fifo/intel_fifo_8.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "FIFO" -set_global_assignment -name IP_TOOL_VERSION "21.1" -set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "intel_fifo_8.v"] diff --git a/fw/rtl/intel/fifo/intel_fifo_8.v b/fw/rtl/intel/fifo/intel_fifo_8.v deleted file mode 100644 index 88316a2..0000000 --- a/fw/rtl/intel/fifo/intel_fifo_8.v +++ /dev/null @@ -1,162 +0,0 @@ -// megafunction wizard: %FIFO% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: scfifo - -// ============================================================ -// File Name: intel_fifo_8.v -// Megafunction Name(s): -// scfifo -// -// Simulation Library Files(s): -// -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 21.1.0 Build 842 10/21/2021 SJ Lite Edition -// ************************************************************ - - -//Copyright (C) 2021 Intel Corporation. All rights reserved. -//Your use of Intel Corporation's design tools, logic functions -//and other software and tools, and any partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Intel Program License -//Subscription Agreement, the Intel Quartus Prime License Agreement, -//the Intel FPGA IP License Agreement, or other applicable license -//agreement, including, without limitation, that your use is for -//the sole purpose of programming logic devices manufactured by -//Intel and sold by Intel or its authorized distributors. Please -//refer to the applicable agreement for further details, at -//https://fpgasoftware.intel.com/eula. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module intel_fifo_8 ( - clock, - data, - rdreq, - sclr, - wrreq, - empty, - full, - q); - - input clock; - input [7:0] data; - input rdreq; - input sclr; - input wrreq; - output empty; - output full; - output [7:0] q; - - wire sub_wire0; - wire sub_wire1; - wire [7:0] sub_wire2; - wire empty = sub_wire0; - wire full = sub_wire1; - wire [7:0] q = sub_wire2[7:0]; - - scfifo scfifo_component ( - .clock (clock), - .data (data), - .rdreq (rdreq), - .sclr (sclr), - .wrreq (wrreq), - .empty (sub_wire0), - .full (sub_wire1), - .q (sub_wire2), - .aclr (), - .almost_empty (), - .almost_full (), - .eccstatus (), - .usedw ()); - defparam - scfifo_component.add_ram_output_register = "ON", - scfifo_component.intended_device_family = "MAX 10", - scfifo_component.lpm_numwords = 1024, - scfifo_component.lpm_showahead = "ON", - scfifo_component.lpm_type = "scfifo", - scfifo_component.lpm_width = 8, - scfifo_component.lpm_widthu = 10, - scfifo_component.overflow_checking = "ON", - scfifo_component.underflow_checking = "ON", - scfifo_component.use_eab = "ON"; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1" -// Retrieval info: PRIVATE: Clock NUMERIC "0" -// Retrieval info: PRIVATE: Depth NUMERIC "1024" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "1" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: UsedW NUMERIC "0" -// Retrieval info: PRIVATE: Width NUMERIC "8" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: diff_widths NUMERIC "0" -// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" -// Retrieval info: PRIVATE: output_width NUMERIC "8" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "1" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" -// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" -// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty" -// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full" -// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" -// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr" -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" -// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 -// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 -// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8_bb.v FALSE diff --git a/fw/rtl/intel/flash/intel_flash.qsys b/fw/rtl/intel/flash/intel_flash.qsys deleted file mode 100644 index 5759c65..0000000 --- a/fw/rtl/intel/flash/intel_flash.qsys +++ /dev/null @@ -1,90 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Single Compressed Image - Internal Configuration - - - - - - Read and write,Read and write,Hidden,Read and write,Read and write - $${FILENAME}_onchip_flash_0 - - - - - - - - - - diff --git a/fw/rtl/intel/gpio/intel_gpio_ddro.qip b/fw/rtl/intel/gpio/intel_gpio_ddro.qip deleted file mode 100644 index 2cd6c78..0000000 --- a/fw/rtl/intel/gpio/intel_gpio_ddro.qip +++ /dev/null @@ -1,77 +0,0 @@ -set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_TOOL_NAME "altera_gpio_lite" -set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_TOOL_VERSION "21.1" -set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_TOOL_ENV "mwpim" -set_global_assignment -library "intel_gpio_ddro" -name MISC_FILE [file join $::quartus(qip_path) "intel_gpio_ddro.cmp"] -set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_TARGETED_DEVICE_FAMILY "MAX 10" -set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" -set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_QSYS_MODE "UNKNOWN" -set_global_assignment -name SYNTHESIS_ONLY_QIP ON -set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_NAME "aW50ZWxfZ3Bpb19kZHJv" -set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA=" -set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" -set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_VERSION "MjEuMQ==" -set_global_assignment -entity "intel_gpio_ddro" -library "intel_gpio_ddro" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA=" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_NAME "YWx0ZXJhX2dwaW9fbGl0ZQ==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA=" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_VERSION "MjEuMQ==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA=" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIGZhbWlseQ==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "UElOX1RZUEU=::b3V0cHV0::RGF0YSBkaXJlY3Rpb24=" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "U0laRQ==::MQ==::RGF0YSB3aWR0aA==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX3RydWVfZGlmZl9idWY=::ZmFsc2U=::VXNlIHRydWUgZGlmZmVyZW50aWFsIGJ1ZmZlcg==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX3BzZXVkb19kaWZmX2J1Zg==::ZmFsc2U=::VXNlIHBzZXVkbyBkaWZmZXJlbnRpYWwgYnVmZmVy" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2J1c19ob2xk::ZmFsc2U=::VXNlIGJ1cy1ob2xkIGNpcmN1aXRyeQ==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX29wZW5fZHJhaW4=::ZmFsc2U=::VXNlIG9wZW4gZHJhaW4gb3V0cHV0" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9vZV9wb3J0::ZmFsc2U=::RW5hYmxlIG9lIHBvcnQ=" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2lvX3JlZ19tb2Rl::ZGRy::UmVnaXN0ZXIgbW9kZQ==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9hY2xyX3BvcnQ=::ZmFsc2U=::RW5hYmxlIGFjbHIgcG9ydA==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9hc2V0X3BvcnQ=::ZmFsc2U=::RW5hYmxlIGFzZXQgcG9ydA==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9zY2xyX3BvcnQ=::ZmFsc2U=::RW5hYmxlIHNjbHIgcG9ydA==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX3NldF9yZWdpc3RlcnNfdG9fcG93ZXJfdXBfaGlnaA==::ZmFsc2U=::U2V0IHJlZ2lzdGVycyB0byBwb3dlciB1cCBoaWdoICh3aGVuIGFjbHIsIHNjbHIgYW5kIGFzZXQgcG9ydHMgYXJlIG5vdCB1c2VkKQ==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2Nsb2NrX2VuYWJsZQ==::ZmFsc2U=::RW5hYmxlIGluY2xvY2tlbi9vdXRjbG9ja2VuIHBvcnRz" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vdXRwdXQ=::ZmFsc2U=::SW52ZXJ0IGRpbg==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9yZWdpc3Rlcl90b19kcml2ZV9vYnVmX29l::ZmFsc2U=::VXNlIGEgc2luZ2xlIHJlZ2lzdGVyIHRvIGRyaXZlIHRoZSBvdXRwdXQgZW5hYmxlIChvZSkgc2lnbmFsIGF0IHRoZSBJL08gYnVmZmVy" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9kZGlvX3JlZ190b19kcml2ZV9vZQ==::ZmFsc2U=::VXNlIERESU8gcmVnaXN0ZXJzIHRvIGRyaXZlIHRoZSBvdXRwdXQgZW5hYmxlIChvZSkgc2lnbmFsIGF0IHRoZSBJL08gYnVmZmVy" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9hZHZhbmNlZF9kZHJfZmVhdHVyZXM=::ZmFsc2U=::RW5hYmxlIGFkdmFuY2VkIEREUiBmZWF0dXJlcw==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9waGFzZV9kZXRlY3Rvcl9mb3JfY2s=::ZmFsc2U=::RW5hYmxlIFBoYXNlIERldGVjdG9yIGZyb20gQ0sgbG9vcGJhY2sgc2lnbmFs" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9vZV9oYWxmX2N5Y2xlX2RlbGF5::dHJ1ZQ==::QWRkIGhhbGYtY3ljbGUgZGVsYXkgdG8gT0Ugc2lnbmFs" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9ocl9jbG9jaw==::ZmFsc2U=::RW5hYmxlIGhhbGYtcmF0ZSBjbG9jayBwb3J0" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9pbnZlcnRfaHJfY2xvY2tfcG9ydA==::ZmFsc2U=::RW5hYmxlIGludmVydF9ocl9jbG9jayBwb3J0" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9jbGtkaXZfaW5wdXRfY2xvY2s=::ZmFsc2U=::SW52ZXJ0IGNsb2NrIGRpdmlkZXIgaW5wdXQgY2xvY2s=" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vdXRwdXRfY2xvY2s=::ZmFsc2U=::SW52ZXJ0IERESU8gb3V0Y2xvY2s=" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vZV9pbmNsb2Nr::ZmFsc2U=::SW52ZXJ0IG91dHB1dCBlbmFibGUgKG9lKSByZWdpc3RlciBpbmNsb2Nr" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJfTU9ERQ==::ZGRy::UkVHSVNURVJfTU9ERQ==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "QlVGRkVSX1RZUEU=::c2luZ2xlLWVuZGVk::QlVGRkVSX1RZUEU=" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "QVNZTkNfTU9ERQ==::bm9uZQ==::QVNZTkNfTU9ERQ==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "U1lOQ19NT0RF::bm9uZQ==::U1lOQ19NT0RF" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "QlVTX0hPTEQ=::ZmFsc2U=::QlVTX0hPTEQ=" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "T1BFTl9EUkFJTl9PVVRQVVQ=::ZmFsc2U=::T1BFTl9EUkFJTl9PVVRQVVQ=" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "RU5BQkxFX09FX1BPUlQ=::ZmFsc2U=::RU5BQkxFX09FX1BPUlQ=" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05TTEVFUF9QT1JU::ZmFsc2U=::RU5BQkxFX05TTEVFUF9QT1JU" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NMT0NLX0VOQV9QT1JU::ZmFsc2U=::RU5BQkxFX0NMT0NLX0VOQV9QT1JU" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "U0VUX1JFR0lTVEVSX09VVFBVVFNfSElHSA==::ZmFsc2U=::U0VUX1JFR0lTVEVSX09VVFBVVFNfSElHSA==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09VVFBVVA==::ZmFsc2U=::SU5WRVJUX09VVFBVVA==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "SU5WRVJUX0lOUFVUX0NMT0NL::ZmFsc2U=::SU5WRVJUX0lOUFVUX0NMT0NL" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "VVNFX09ORV9SRUdfVE9fRFJJVkVfT0U=::ZmFsc2U=::VVNFX09ORV9SRUdfVE9fRFJJVkVfT0U=" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "VVNFX0RESU9fUkVHX1RPX0RSSVZFX09F::ZmFsc2U=::VVNFX0RESU9fUkVHX1RPX0RSSVZFX09F" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFUw==::ZmFsc2U=::VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFUw==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFU19GT1JfSU5QVVRfT05MWQ==::ZmFsc2U=::VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFU19GT1JfSU5QVVRfT05MWQ==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "RU5BQkxFX09FX0hBTEZfQ1lDTEVfREVMQVk=::dHJ1ZQ==::RU5BQkxFX09FX0hBTEZfQ1lDTEVfREVMQVk=" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "SU5WRVJUX0NMS0RJVl9JTlBVVF9DTE9DSw==::ZmFsc2U=::SU5WRVJUX0NMS0RJVl9JTlBVVF9DTE9DSw==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1BIQVNFX0lOVkVSVF9DVFJMX1BPUlQ=::ZmFsc2U=::RU5BQkxFX1BIQVNFX0lOVkVSVF9DVFJMX1BPUlQ=" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0hSX0NMT0NL::ZmFsc2U=::RU5BQkxFX0hSX0NMT0NL" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09VVFBVVF9DTE9DSw==::ZmFsc2U=::SU5WRVJUX09VVFBVVF9DTE9DSw==" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09FX0lOQ0xPQ0s=::ZmFsc2U=::SU5WRVJUX09FX0lOQ0xPQ0s=" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1BIQVNFX0RFVEVDVE9SX0ZPUl9DSw==::ZmFsc2U=::RU5BQkxFX1BIQVNFX0RFVEVDVE9SX0ZPUl9DSw==" - -set_global_assignment -library "intel_gpio_ddro" -name VERILOG_FILE [file join $::quartus(qip_path) "intel_gpio_ddro.v"] -set_global_assignment -library "intel_gpio_ddro" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_gpio_ddro/altera_gpio_lite.sv"] - -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_TOOL_NAME "altera_gpio_lite" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_TOOL_VERSION "21.1" -set_global_assignment -entity "altera_gpio_lite" -library "intel_gpio_ddro" -name IP_TOOL_ENV "mwpim" diff --git a/fw/rtl/intel/gpio/intel_gpio_ddro.v b/fw/rtl/intel/gpio/intel_gpio_ddro.v deleted file mode 100644 index 66bf848..0000000 --- a/fw/rtl/intel/gpio/intel_gpio_ddro.v +++ /dev/null @@ -1,123 +0,0 @@ -// megafunction wizard: %GPIO Lite Intel FPGA IP v21.1% -// GENERATION: XML -// intel_gpio_ddro.v - -// Generated using ACDS version 21.1 842 - -`timescale 1 ps / 1 ps -module intel_gpio_ddro ( - input wire outclock, // outclock.export - input wire [1:0] din, // din.export - output wire [0:0] pad_out // pad_out.export - ); - - altera_gpio_lite #( - .PIN_TYPE ("output"), - .SIZE (1), - .REGISTER_MODE ("ddr"), - .BUFFER_TYPE ("single-ended"), - .ASYNC_MODE ("none"), - .SYNC_MODE ("none"), - .BUS_HOLD ("false"), - .OPEN_DRAIN_OUTPUT ("false"), - .ENABLE_OE_PORT ("false"), - .ENABLE_NSLEEP_PORT ("false"), - .ENABLE_CLOCK_ENA_PORT ("false"), - .SET_REGISTER_OUTPUTS_HIGH ("false"), - .INVERT_OUTPUT ("false"), - .INVERT_INPUT_CLOCK ("false"), - .USE_ONE_REG_TO_DRIVE_OE ("false"), - .USE_DDIO_REG_TO_DRIVE_OE ("false"), - .USE_ADVANCED_DDR_FEATURES ("false"), - .USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ("false"), - .ENABLE_OE_HALF_CYCLE_DELAY ("true"), - .INVERT_CLKDIV_INPUT_CLOCK ("false"), - .ENABLE_PHASE_INVERT_CTRL_PORT ("false"), - .ENABLE_HR_CLOCK ("false"), - .INVERT_OUTPUT_CLOCK ("false"), - .INVERT_OE_INCLOCK ("false"), - .ENABLE_PHASE_DETECTOR_FOR_CK ("false") - ) intel_gpio_ddro_inst ( - .outclock (outclock), // outclock.export - .din (din), // din.export - .pad_out (pad_out), // pad_out.export - .outclocken (1'b1), // (terminated) - .inclock (1'b0), // (terminated) - .inclocken (1'b0), // (terminated) - .fr_clock (), // (terminated) - .hr_clock (), // (terminated) - .invert_hr_clock (1'b0), // (terminated) - .phy_mem_clock (1'b0), // (terminated) - .mimic_clock (), // (terminated) - .dout (), // (terminated) - .pad_io (), // (terminated) - .pad_io_b (), // (terminated) - .pad_in (1'b0), // (terminated) - .pad_in_b (1'b0), // (terminated) - .pad_out_b (), // (terminated) - .aset (1'b0), // (terminated) - .aclr (1'b0), // (terminated) - .sclr (1'b0), // (terminated) - .nsleep (1'b0), // (terminated) - .oe (1'b0) // (terminated) - ); - -endmodule -// Retrieval info: -// -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// IPFS_FILES : intel_gpio_ddro.vo -// RELATED_FILES: intel_gpio_ddro.v, altera_gpio_lite.sv diff --git a/fw/rtl/intel/gpio/intel_gpio_ddro/altera_gpio_lite.sv b/fw/rtl/intel/gpio/intel_gpio_ddro/altera_gpio_lite.sv deleted file mode 100644 index 4c06935..0000000 --- a/fw/rtl/intel/gpio/intel_gpio_ddro/altera_gpio_lite.sv +++ /dev/null @@ -1,1200 +0,0 @@ -// (C) 2001-2021 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files from any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License Subscription -// Agreement, Intel FPGA IP License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -`timescale 1 ps / 1 ps - -module altgpio_one_bit( - inclock, - outclock, - phy_mem_clock, - inclocken, - outclocken, - oe, - din, - dout, - pad, - pad_b, - aset, - sclr, - hr_clock, - fr_clock, - mimic_clock, - nsleep -); - - parameter PIN_TYPE = "output"; - parameter BUFFER_TYPE = "single-ended"; - parameter REGISTER_MODE = "bypass"; - parameter ASYNC_MODE = "none"; - parameter SYNC_MODE = "none"; - parameter BUS_HOLD = "false"; - parameter SET_REGISTER_OUTPUTS_HIGH = "false"; - parameter USE_ENHANCED_DDR_HIO_REGISTER = "false"; - parameter BYPASS_THREE_QUARTER_REGISTER = "true"; - parameter INVERT_OUTPUT = "false"; - parameter INVERT_INPUT_CLOCK = "false"; - parameter INVERT_OUTPUT_CLOCK = "false"; - parameter INVERT_OE_INCLOCK = "false"; - parameter USE_ONE_REG_TO_DRIVE_OE = "false"; - parameter USE_DDIO_REG_TO_DRIVE_OE = "false"; - parameter OPEN_DRAIN_OUTPUT = "false"; - parameter ENABLE_OE_HALF_CYCLE_DELAY = "true"; - parameter USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY = "false"; - parameter ENABLE_CLOCK_ENA_PORT = "false"; - parameter ENABLE_HR_CLOCK = "false"; - parameter ENABLE_PHASE_DETECTOR_FOR_CK = "false"; - parameter ENABLE_NSLEEP_PORT = "false"; - - localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? 2:1; - localparam DDIO_REG_POWER_UP = (ASYNC_MODE == "preset" || SET_REGISTER_OUTPUTS_HIGH == "true") ? "high" : "low"; - - input inclock; - input outclock; - input inclocken; - input outclocken; - input oe; - input nsleep; - input [DATA_SIZE - 1:0] din; - output [DATA_SIZE - 1:0] dout; - inout pad; - inout pad_b; - input aset; - input sclr; - input phy_mem_clock; - input hr_clock; - (* altera_attribute = "-name GLOBAL_SIGNAL\"OFF\"" *) output fr_clock; - output mimic_clock; - - wire din_ddr; - wire buf_in; - - wire oe_out; - wire nsleep_in; - - generate - if (PIN_TYPE == "output" || PIN_TYPE == "bidir") - begin - wire [1:0] din_fr; - if (INVERT_OUTPUT == "false") - begin - assign din_fr = din; - end - else - begin - assign din_fr = ~din; - end - - wire outclock_wire; - if (REGISTER_MODE != "bypass") - begin - if (INVERT_OUTPUT_CLOCK == "false") - begin: normal_input_clock - assign outclock_wire = outclock; - end - else - begin: inverted_output_clock - assign outclock_wire = ~outclock; - end - end - - wire outclocken_wire; - assign outclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? outclocken : 1'b1; - - if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "true") - begin - if (ASYNC_MODE != "none") - begin: async_mode_out_path_enhanced_ddr - fiftyfivenm_ddio_out - #( - .async_mode(ASYNC_MODE), - .sync_mode(SYNC_MODE), - .use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER), - .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER), - .power_up(DDIO_REG_POWER_UP), - .use_new_clocking_model("true") - ) fr_out_data_ddio ( - .datainhi(din_fr[0]), - .datainlo(din_fr[1]), - .dataout(din_ddr), - .clkhi(outclock_wire), - .clklo(outclock_wire), - .muxsel(outclock_wire), - .areset(aset), - .ena(outclocken_wire), - .phymemclock(phy_mem_clock) - `ifndef ALTERA_RESERVED_QIS - , - .clk (outclock_wire), - .sreset(1'b0), - .dfflo(), - .dffhi(), - .devpor(1'b1), - .devclrn(1'b1) - `endif - ); - end - else if (SYNC_MODE != "none") - begin: sync_mode_out_path_enhanced_ddr - fiftyfivenm_ddio_out - #( - .async_mode(ASYNC_MODE), - .sync_mode(SYNC_MODE), - .use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER), - .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER), - .power_up(DDIO_REG_POWER_UP), - .use_new_clocking_model("true") - ) fr_out_data_ddio ( - .datainhi(din_fr[0]), - .datainlo(din_fr[1]), - .dataout(din_ddr), - .clkhi(outclock_wire), - .clklo(outclock_wire), - .muxsel(outclock_wire), - .sreset(sclr), - .ena(outclocken_wire), - .phymemclock(phy_mem_clock) - `ifndef ALTERA_RESERVED_QIS - , - .clk (outclock_wire), - .areset(1'b0), - .dfflo(), - .dffhi(), - .devpor(1'b1), - .devclrn(1'b1) - `endif - ); - end - else - begin: out_path_enhanced_ddr - fiftyfivenm_ddio_out - #( - .async_mode(ASYNC_MODE), - .sync_mode(SYNC_MODE), - .use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER), - .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER), - .power_up(DDIO_REG_POWER_UP), - .use_new_clocking_model("true") - ) fr_out_data_ddio ( - .datainhi(din_fr[0]), - .datainlo(din_fr[1]), - .dataout(din_ddr), - .clkhi(outclock_wire), - .clklo(outclock_wire), - .muxsel(outclock_wire), - .ena(outclocken_wire), - .phymemclock(phy_mem_clock) - `ifndef ALTERA_RESERVED_QIS - , - .areset(1'b0), - .clk(1'b0), - .sreset(1'b0), - .dfflo(), - .dffhi(), - .devpor(1'b1), - .devclrn(1'b1) - `endif - ); - end - end - else if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "false") - begin - if (ASYNC_MODE != "none") - begin: async_mode_out_path_ddr - fiftyfivenm_ddio_out - #( - .async_mode(ASYNC_MODE), - .sync_mode(SYNC_MODE), - .power_up(DDIO_REG_POWER_UP), - .use_new_clocking_model("true"), - .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER) - ) fr_out_data_ddio ( - .datainhi(din_fr[0]), - .datainlo(din_fr[1]), - .dataout(din_ddr), - .clkhi(outclock_wire), - .clklo(outclock_wire), - .muxsel(outclock_wire), - .areset(aset), - .ena(outclocken_wire) - `ifndef ALTERA_RESERVED_QIS - , - .clk(1'b0), - .phymemclock(1'b0), - .sreset(1'b0), - .dfflo(), - .dffhi(), - .devpor(1'b1), - .devclrn(1'b1) - `endif - ); - end - else if (SYNC_MODE != "none") - begin: sync_mode_out_path_ddr - fiftyfivenm_ddio_out - #( - .async_mode(ASYNC_MODE), - .sync_mode(SYNC_MODE), - .power_up(DDIO_REG_POWER_UP), - .use_new_clocking_model("true"), - .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER) - ) fr_out_data_ddio ( - .datainhi(din_fr[0]), - .datainlo(din_fr[1]), - .dataout(din_ddr), - .clkhi(outclock_wire), - .clklo(outclock_wire), - .muxsel(outclock_wire), - .sreset(sclr), - .ena(outclocken_wire) - `ifndef ALTERA_RESERVED_QIS - , - .areset(1'b0), - .clk(1'b0), - .phymemclock(1'b0), - .dfflo(), - .dffhi(), - .devpor(1'b1), - .devclrn(1'b1) - `endif - ); - end - else - begin: out_path_ddr - fiftyfivenm_ddio_out - #( - .async_mode(ASYNC_MODE), - .sync_mode(SYNC_MODE), - .power_up(DDIO_REG_POWER_UP), - .use_new_clocking_model("true"), - .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER) - ) fr_out_data_ddio ( - .datainhi(din_fr[0]), - .datainlo(din_fr[1]), - .dataout(din_ddr), - .clkhi(outclock_wire), - .clklo(outclock_wire), - .muxsel(outclock_wire), - .ena(outclocken_wire) - `ifndef ALTERA_RESERVED_QIS - , - .areset(1'b0), - .clk(1'b0), - .phymemclock(1'b0), - .sreset(1'b0), - .dfflo(), - .dffhi(), - .devpor(1'b1), - .devclrn(1'b1) - `endif - ); - end - end - else if (REGISTER_MODE == "single-register") - begin: out_path_sdr - reg reg_data_out /* synthesis altera_attribute="FAST_OUTPUT_REGISTER=on" */; - always @(posedge outclock_wire) - reg_data_out <= din_fr[0]; - - assign din_ddr = reg_data_out; - end - else - begin: out_path_reg_none - assign din_ddr = din_fr[0]; - end - end - endgenerate - - generate - - if (PIN_TYPE == "bidir" || PIN_TYPE == "output") - begin - wire oe_inclk_wire; - if (USE_ONE_REG_TO_DRIVE_OE == "true" || USE_DDIO_REG_TO_DRIVE_OE == "true") - begin - if (INVERT_OE_INCLOCK == "false") - begin: normal_oe_inclock - assign oe_inclk_wire = outclock; - end - else - begin: inverted_oe_inclock - assign oe_inclk_wire = ~outclock; - end - end - - wire oe_outclocken_wire; - assign oe_outclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? outclocken : 1'b1; - - if (USE_DDIO_REG_TO_DRIVE_OE == "true") - begin - if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "true") - begin - if (ASYNC_MODE != "none") - begin: async_mode_oe_path_enhanced_ddr - fiftyfivenm_ddio_oe - #( - .async_mode(ASYNC_MODE), - .sync_mode(SYNC_MODE), - .use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER), - .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER), - .enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY), - .power_up(DDIO_REG_POWER_UP) - ) fr_oe_data_ddio ( - .oe(~oe), - .dataout(oe_out), - .clk(oe_inclk_wire), - .areset(aset), - .ena(oe_outclocken_wire), - .phymemclock(phy_mem_clock) - `ifndef ALTERA_RESERVED_QIS - , - .sreset(1'b0), - .dfflo(), - .dffhi(), - .devpor(1'b1), - .devclrn(1'b1) - `endif - ); - end - else if (SYNC_MODE != "none") - begin: sync_mode_oe_path_enhanced_ddr - fiftyfivenm_ddio_oe - #( - .async_mode(ASYNC_MODE), - .sync_mode(SYNC_MODE), - .use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER), - .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER), - .enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY), - .power_up(DDIO_REG_POWER_UP) - ) fr_oe_data_ddio ( - .oe(~oe), - .dataout(oe_out), - .clk(oe_inclk_wire), - .sreset(sclr), - .ena(oe_outclocken_wire), - .phymemclock(phy_mem_clock) - `ifndef ALTERA_RESERVED_QIS - , - .areset(1'b0), - .dfflo(), - .dffhi(), - .devpor(1'b1), - .devclrn(1'b1) - `endif - ); - end - else - begin: oe_path_enhanced_ddr - fiftyfivenm_ddio_oe - #( - .async_mode(ASYNC_MODE), - .sync_mode(SYNC_MODE), - .use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER), - .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER), - .enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY), - .power_up(DDIO_REG_POWER_UP) - ) fr_oe_data_ddio ( - .oe(~oe), - .dataout(oe_out), - .clk(oe_inclk_wire), - .ena(oe_outclocken_wire), - .phymemclock(phy_mem_clock) - `ifndef ALTERA_RESERVED_QIS - , - .areset(1'b0), - .sreset(1'b0), - .dfflo(), - .dffhi(), - .devpor(1'b1), - .devclrn(1'b1) - `endif - ); - end - end - else if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "false") - begin - if (ASYNC_MODE != "none") - begin: async_mode_oe_path_ddr - fiftyfivenm_ddio_oe - #( - .async_mode(ASYNC_MODE), - .sync_mode(SYNC_MODE), - .enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY), - .power_up(DDIO_REG_POWER_UP), - .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER) - ) fr_oe_data_ddio ( - .oe(~oe), - .dataout(oe_out), - .clk(oe_inclk_wire), - .areset(aset), - .ena(oe_outclocken_wire) - `ifndef ALTERA_RESERVED_QIS - , - .phymemclock(1'b0), - .sreset(1'b0), - .dfflo(), - .dffhi(), - .devpor(1'b1), - .devclrn(1'b1) - `endif - ); - end - else if (SYNC_MODE != "none") - begin: sync_mode_oe_path_ddr - fiftyfivenm_ddio_oe - #( - .async_mode(ASYNC_MODE), - .sync_mode(SYNC_MODE), - .enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY), - .power_up(DDIO_REG_POWER_UP), - .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER) - ) fr_oe_data_ddio ( - .oe(~oe), - .dataout(oe_out), - .clk(oe_inclk_wire), - .sreset(sclr), - .ena(oe_outclocken_wire) - `ifndef ALTERA_RESERVED_QIS - , - .areset(1'b0), - .phymemclock(1'b0), - .dfflo(), - .dffhi(), - .devpor(1'b1), - .devclrn(1'b1) - `endif - ); - end - else - begin: oe_path_ddr - fiftyfivenm_ddio_oe - #( - .async_mode(ASYNC_MODE), - .sync_mode(SYNC_MODE), - .enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY), - .power_up(DDIO_REG_POWER_UP), - .bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER) - ) fr_oe_data_ddio ( - .oe(~oe), - .dataout(oe_out), - .clk(oe_inclk_wire), - .ena(oe_outclocken_wire) - `ifndef ALTERA_RESERVED_QIS - , - .areset(1'b0), - .phymemclock(1'b0), - .sreset(1'b0), - .dfflo(), - .dffhi(), - .devpor(1'b1), - .devclrn(1'b1) - `endif - ); - end - end - end - else if (USE_ONE_REG_TO_DRIVE_OE == "true") - begin: oe_path_sdr - fiftyfivenm_ff oe_reg ( - .clk(oe_inclk_wire), - .d(~oe), - .clrn(1'b1), - .ena(1'b1), - .q(oe_out) - ); - end - else if (USE_ONE_REG_TO_DRIVE_OE == "false" && USE_DDIO_REG_TO_DRIVE_OE == "false") - begin: oe_path_reg_none - assign oe_out = ~oe; - end - end - endgenerate - - generate - if (PIN_TYPE == "input" || PIN_TYPE == "bidir") - begin - wire [1:0] ddr_input; - wire inclock_wire; - - if (REGISTER_MODE != "bypass") - begin - if (INVERT_INPUT_CLOCK == "false") - begin: normal_input_clock - assign inclock_wire = inclock; - end - else - begin: inverted_input_clock - assign inclock_wire = ~inclock; - end - end - - wire inclocken_wire; - assign inclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? inclocken : 1'b1; - - if (REGISTER_MODE == "ddr") - begin - if (USE_ENHANCED_DDR_HIO_REGISTER == "true" || USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY == "true") - begin - if (ENABLE_HR_CLOCK == "true") - begin - if (ASYNC_MODE != "none") - begin: async_mode_in_path_enhanced_ddr_with_halfrateresyncclk - fiftyfivenm_ddio_in - #( - .async_mode(ASYNC_MODE), - .sync_mode(SYNC_MODE), - .power_up(DDIO_REG_POWER_UP), - .invert_input_clock(INVERT_INPUT_CLOCK) - ) fr_in_ddio ( - .datain(buf_in), - .clk(inclock_wire), - .ena(inclocken_wire), - .halfrateresyncclk(hr_clock), - .regouthi(ddr_input[1]), - .regoutlo(ddr_input[0]), - .clkout(fr_clock), - .areset(aset) - `ifndef ALTERA_RESERVED_QIS - , - .sreset(1'b0), - .dfflo(), - .devpor(1'b1), - .devclrn(1'b1) - `endif - ); - end - else if (SYNC_MODE != "none") - begin:sync_mode_in_path_enhanced_ddr_with_halfrateresyncclk - fiftyfivenm_ddio_in - #( - .async_mode(ASYNC_MODE), - .sync_mode(SYNC_MODE), - .power_up(DDIO_REG_POWER_UP), - .invert_input_clock(INVERT_INPUT_CLOCK) - ) fr_in_ddio ( - .datain(buf_in), - .clk (inclock_wire), - .ena(inclocken_wire), - .sreset(sclr), - .halfrateresyncclk(hr_clock), - .regouthi(ddr_input[1]), - .regoutlo(ddr_input[0]), - .clkout(fr_clock) - `ifndef ALTERA_RESERVED_QIS - , - .areset(1'b0), - .dfflo(), - .devpor(1'b1), - .devclrn(1'b1) - `endif - ); - end - else - begin:in_path_enhanced_ddr_with_halfrateresyncclk - fiftyfivenm_ddio_in - #( - .async_mode(ASYNC_MODE), - .sync_mode(SYNC_MODE), - .power_up(DDIO_REG_POWER_UP), - .invert_input_clock(INVERT_INPUT_CLOCK) - ) fr_in_ddio ( - .datain(buf_in), - .clk (inclock_wire), - .ena(inclocken_wire), - .halfrateresyncclk(hr_clock), - .regouthi(ddr_input[1]), - .regoutlo(ddr_input[0]), - .clkout(fr_clock) - `ifndef ALTERA_RESERVED_QIS - , - .sreset(1'b0), - .areset(1'b0), - .dfflo(), - .devpor(1'b1), - .devclrn(1'b1) - `endif - ); - end - end - else - begin - if (ASYNC_MODE != "none") - begin: async_mode_in_path_enhanced_ddr - fiftyfivenm_ddio_in - #( - .async_mode(ASYNC_MODE), - .sync_mode(SYNC_MODE), - .power_up(DDIO_REG_POWER_UP), - .invert_input_clock(INVERT_INPUT_CLOCK) - ) fr_in_ddio ( - .datain(buf_in), - .clk(inclock_wire), - .ena(inclocken_wire), - .regouthi(ddr_input[1]), - .regoutlo(ddr_input[0]), - .clkout(fr_clock), - .areset(aset) - `ifndef ALTERA_RESERVED_QIS - , - .sreset(1'b0), - .dfflo(), - .devpor(1'b1), - .devclrn(1'b1), - .halfrateresyncclk(1'b0) - `endif - ); - end - else if (SYNC_MODE != "none") - begin:sync_mode_in_path_enhanced_ddr - fiftyfivenm_ddio_in - #( - .async_mode(ASYNC_MODE), - .sync_mode(SYNC_MODE), - .power_up(DDIO_REG_POWER_UP), - .invert_input_clock(INVERT_INPUT_CLOCK) - ) fr_in_ddio ( - .datain(buf_in), - .clk (inclock_wire), - .ena(inclocken_wire), - .sreset(sclr), - .regouthi(ddr_input[1]), - .regoutlo(ddr_input[0]), - .clkout(fr_clock) - `ifndef ALTERA_RESERVED_QIS - , - .areset(1'b0), - .dfflo(), - .devpor(1'b1), - .devclrn(1'b1), - .halfrateresyncclk(1'b0) - `endif - ); - end - else - begin:in_path_enhanced_ddr - fiftyfivenm_ddio_in - #( - .async_mode(ASYNC_MODE), - .sync_mode(SYNC_MODE), - .power_up(DDIO_REG_POWER_UP), - .invert_input_clock(INVERT_INPUT_CLOCK) - ) fr_in_ddio ( - .datain(buf_in), - .clk (inclock_wire), - .ena(inclocken_wire), - .regouthi(ddr_input[1]), - .regoutlo(ddr_input[0]), - .clkout(fr_clock) - `ifndef ALTERA_RESERVED_QIS - , - .sreset(1'b0), - .areset(1'b0), - .dfflo(), - .devpor(1'b1), - .devclrn(1'b1), - .halfrateresyncclk(1'b0) - `endif - ); - end - end - end - else if (ENABLE_PHASE_DETECTOR_FOR_CK == "true") - begin - assign mimic_clock = buf_in; - end - else - begin: in_path_ddr - wire input_cell_l_q; - wire input_aset; - - assign input_aset = ( ASYNC_MODE == "clear") ? !aset : aset; - - fiftyfivenm_ff input_cell_l ( - .clk(inclock_wire), - .d(buf_in), - .clrn(input_aset), - .ena(inclocken_wire), - .q(input_cell_l_q) - ); - - fiftyfivenm_ff input_latch_l ( - .clk(~inclock_wire), - .d(input_cell_l_q), - .clrn(input_aset), - .ena(inclocken_wire), - .q(ddr_input[0]) - ); - - fiftyfivenm_ff input_cell_h ( - .clk(~inclock_wire), - .d(buf_in), - .clrn(input_aset), - .ena(inclocken_wire), - .q(ddr_input[1]) - ); - - end - end - else if (REGISTER_MODE == "single-register") - begin: in_path_sdr - reg reg_data_in /* synthesis altera_attribute="FAST_INPUT_REGISTER=on" */; - always @(posedge inclock_wire) begin - reg_data_in <= buf_in; - end - assign ddr_input[0] = reg_data_in; - end - else - begin: in_path_reg_none - assign ddr_input[0] = buf_in; - end - - assign dout[DATA_SIZE - 1:0] = ddr_input[DATA_SIZE - 1:0]; - - end - endgenerate - - generate - if (PIN_TYPE == "output" || PIN_TYPE == "bidir") - begin - if(BUFFER_TYPE == "pseudo_differential") - begin: pseudo_diff_output_buf - - wire wire_pseudo_diff_o; - wire wire_pseudo_diff_o_bar; - - fiftyfivenm_io_obuf - #( - .bus_hold(BUS_HOLD), - .open_drain_output(OPEN_DRAIN_OUTPUT) - ) obuf_a ( - .i(wire_pseudo_diff_o), - .oe(~oe_out), - .o(pad), - .obar() - `ifndef ALTERA_RESERVED_QIS - , - .seriesterminationcontrol(16'b0), - .devoe(1'b1) - `endif - ); - - fiftyfivenm_io_obuf - #( - .bus_hold(BUS_HOLD), - .open_drain_output(OPEN_DRAIN_OUTPUT) - ) obuf_a_bar ( - .i(wire_pseudo_diff_o_bar), - .oe(~oe_out), - .o(pad_b), - .obar() - `ifndef ALTERA_RESERVED_QIS - , - .seriesterminationcontrol(16'b0), - .devoe(1'b1) - `endif - ); - - fiftyfivenm_pseudo_diff_out pseudo_diff_a - ( - .i(din_ddr), - .o(wire_pseudo_diff_o), - .obar(wire_pseudo_diff_o_bar) - ); - - - - end - else if (BUFFER_TYPE == "true_differential") - begin: true_diff_output_buf - fiftyfivenm_io_obuf - #( - .bus_hold(BUS_HOLD), - .open_drain_output(OPEN_DRAIN_OUTPUT) - ) obuf ( - .i(din_ddr), - .oe(~oe_out), - .o(pad), - .obar(pad_b) - `ifndef ALTERA_RESERVED_QIS - , - .seriesterminationcontrol(16'b0), - .devoe(1'b1) - `endif - ); - end - else - begin: output_buf - fiftyfivenm_io_obuf - #( - .bus_hold(BUS_HOLD), - .open_drain_output(OPEN_DRAIN_OUTPUT) - ) obuf ( - .i(din_ddr), - .oe(~oe_out), - .o(pad), - .obar() - `ifndef ALTERA_RESERVED_QIS - , - .seriesterminationcontrol(16'b0), - .devoe(1'b1) - `endif - ); - end - end - endgenerate - - assign nsleep_in = (ENABLE_NSLEEP_PORT == "true") ? nsleep : 1'b1; - - generate - if (PIN_TYPE == "input" || PIN_TYPE == "bidir") - begin - if(BUFFER_TYPE == "true_differential" || BUFFER_TYPE == "pseudo_differential") - begin: diff_input_buf - if (ENABLE_NSLEEP_PORT == "true") - begin: diff_input_buf_with_nsleep - fiftyfivenm_io_ibuf - #( - .bus_hold(BUS_HOLD) - ) ibuf ( - .i(pad), - .ibar(pad_b), - .o(buf_in), - .nsleep(nsleep_in) - ); - end - else - begin: diff_input_buf_without_nsleep - fiftyfivenm_io_ibuf - #( - .bus_hold(BUS_HOLD) - ) ibuf ( - .i(pad), - .ibar(pad_b), - .o(buf_in) - ); - end - end - else - begin:input_buf - if (ENABLE_NSLEEP_PORT == "true") - begin: input_buf_with_nsleep - fiftyfivenm_io_ibuf - #( - .bus_hold(BUS_HOLD) - ) ibuf ( - .i(pad), - .o(buf_in), - .nsleep(nsleep_in) - `ifndef ALTERA_RESERVED_QIS - , - .ibar(1'b0) - `endif - ); - end - else - begin: input_buf_without_nsleep - fiftyfivenm_io_ibuf - #( - .bus_hold(BUS_HOLD) - ) ibuf ( - .i(pad), - .o(buf_in) - `ifndef ALTERA_RESERVED_QIS - , - .ibar(1'b0) - `endif - ); - end - end - end - endgenerate - - generate - if (PIN_TYPE == "output") - begin - assign dout = {DATA_SIZE{1'b0}}; - end - - if (PIN_TYPE == "output" || REGISTER_MODE != "ddr" || USE_ENHANCED_DDR_HIO_REGISTER == "false") - begin - assign fr_clock = 1'b0; - end - - if (PIN_TYPE == "input" || PIN_TYPE == "output" || REGISTER_MODE != "ddr" || ENABLE_PHASE_DETECTOR_FOR_CK == "false") - begin - assign mimic_clock = 1'b0; - end - endgenerate - -endmodule - -module altera_gpio_lite( - inclock, - outclock, - inclocken, - outclocken, - oe, - din, - dout, - pad_io, - pad_io_b, - pad_in, - pad_in_b, - pad_out, - pad_out_b, - aset, - aclr, - phy_mem_clock, - sclr, - hr_clock, - fr_clock, - invert_hr_clock, - mimic_clock, - nsleep -); - - parameter PIN_TYPE = "output"; - parameter BUFFER_TYPE = "single-ended"; - parameter REGISTER_MODE = "bypass"; - parameter SIZE = 4; - parameter ASYNC_MODE = "none"; - parameter SYNC_MODE = "none"; - parameter BUS_HOLD = "false"; - parameter SET_REGISTER_OUTPUTS_HIGH = "false"; - parameter INVERT_OUTPUT = "false"; - parameter INVERT_INPUT_CLOCK = "false"; - parameter INVERT_OUTPUT_CLOCK = "false"; - parameter INVERT_OE_INCLOCK = "false"; - parameter USE_ONE_REG_TO_DRIVE_OE = "false"; - parameter USE_DDIO_REG_TO_DRIVE_OE = "false"; - parameter OPEN_DRAIN_OUTPUT = "false"; - parameter USE_ADVANCED_DDR_FEATURES = "false"; - parameter USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY = "false"; - parameter INVERT_CLKDIV_INPUT_CLOCK = "false"; - parameter ENABLE_HR_CLOCK = "false"; - parameter ENABLE_OE_HALF_CYCLE_DELAY = "true"; - parameter ENABLE_OE_PORT = "false"; - parameter ENABLE_CLOCK_ENA_PORT = "false"; - parameter ENABLE_PHASE_INVERT_CTRL_PORT = "false"; - parameter ENABLE_PHASE_DETECTOR_FOR_CK = "false"; - parameter ENABLE_NSLEEP_PORT = "false"; - - localparam USE_ENHANCED_DDR_HIO_REGISTER = USE_ADVANCED_DDR_FEATURES; - localparam BYPASS_THREE_QUARTER_REGISTER = (USE_ADVANCED_DDR_FEATURES == "true") ? "false" : "true"; - localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? 2 : 1; - - input inclock; - input outclock; - input inclocken; - input outclocken; - input [SIZE - 1:0] oe; - input [SIZE - 1:0] nsleep; - input [SIZE * DATA_SIZE - 1:0] din; - output [SIZE * DATA_SIZE - 1:0] dout; - inout [SIZE - 1:0] pad_io; - inout [SIZE - 1:0] pad_io_b; - input [SIZE - 1:0] pad_in; - input [SIZE - 1:0] pad_in_b; - output [SIZE - 1:0] pad_out; - output [SIZE - 1:0] pad_out_b; - input aset; - input aclr; - input sclr; - input phy_mem_clock; - input invert_hr_clock; - output [SIZE - 1:0] fr_clock; - output wire hr_clock; - output [SIZE - 1:0] mimic_clock; - - wire [SIZE * DATA_SIZE - 1:0] din_reordered; - wire [SIZE * DATA_SIZE - 1:0] dout_reordered; - wire aclr_aset_wire; - wire sclr_wire; - wire [SIZE - 1:0] pad_io; - wire [SIZE - 1:0] pad_io_b; - - - assign aclr_aset_wire = (ASYNC_MODE == "clear") ? aclr : (ASYNC_MODE == "preset") ? aset : 1'b1; - assign sclr_wire = (SYNC_MODE == "clear") ? sclr : 1'b0; - - generate - if (PIN_TYPE == "input") - begin - assign pad_io = pad_in; - assign pad_io_b = pad_in_b; - assign pad_out = {SIZE{1'b0}}; - assign pad_out_b = {SIZE{1'b0}}; - end - else if (PIN_TYPE == "output") - begin - assign pad_out = pad_io; - assign pad_out_b = pad_io_b; - end - else begin - assign pad_out = {SIZE{1'b0}}; - assign pad_out_b = {SIZE{1'b0}}; - end - endgenerate - - genvar j, k; - generate - begin : reorder - for(j = 0; j < SIZE ; j = j + 1) begin : j_loop - for(k = 0; k < DATA_SIZE; k = k + 1) begin : k_d_loop - assign din_reordered[j * DATA_SIZE + k] = din[j + k * SIZE]; - assign dout[j + k * SIZE] = dout_reordered[j * DATA_SIZE + k]; - end - end - end - endgenerate - - genvar i; - generate - begin : gpio_one_bit - for(i = 0 ; i < SIZE ; i = i + 1) begin : i_loop - wire oe_wire; - wire nsleep_wire; - - - assign oe_wire = (PIN_TYPE == "output" && ENABLE_OE_PORT == "false") ? 1'b1 : - (PIN_TYPE == "input") ? 1'b0 : oe[i]; - - - assign nsleep_wire = (PIN_TYPE == "input" && ENABLE_NSLEEP_PORT == "false") ? 1'b1 : - (PIN_TYPE == "output") ? 1'b0 : nsleep[i]; - - altgpio_one_bit #( - .PIN_TYPE(PIN_TYPE), - .BUFFER_TYPE(BUFFER_TYPE), - .REGISTER_MODE(REGISTER_MODE), - .ASYNC_MODE(ASYNC_MODE), - .SYNC_MODE(SYNC_MODE), - .BUS_HOLD(BUS_HOLD), - .SET_REGISTER_OUTPUTS_HIGH(SET_REGISTER_OUTPUTS_HIGH), - .USE_ENHANCED_DDR_HIO_REGISTER(USE_ENHANCED_DDR_HIO_REGISTER), - .USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY(USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY), - .BYPASS_THREE_QUARTER_REGISTER(BYPASS_THREE_QUARTER_REGISTER), - .INVERT_OUTPUT(INVERT_OUTPUT), - .INVERT_INPUT_CLOCK(INVERT_INPUT_CLOCK), - .INVERT_OUTPUT_CLOCK(INVERT_OUTPUT_CLOCK), - .INVERT_OE_INCLOCK(INVERT_OE_INCLOCK), - .USE_ONE_REG_TO_DRIVE_OE(USE_ONE_REG_TO_DRIVE_OE), - .USE_DDIO_REG_TO_DRIVE_OE(USE_DDIO_REG_TO_DRIVE_OE), - .OPEN_DRAIN_OUTPUT(OPEN_DRAIN_OUTPUT), - .ENABLE_OE_HALF_CYCLE_DELAY(ENABLE_OE_HALF_CYCLE_DELAY), - .ENABLE_CLOCK_ENA_PORT(ENABLE_CLOCK_ENA_PORT), - .ENABLE_HR_CLOCK(ENABLE_HR_CLOCK), - .ENABLE_PHASE_DETECTOR_FOR_CK(ENABLE_PHASE_DETECTOR_FOR_CK), - .ENABLE_NSLEEP_PORT(ENABLE_NSLEEP_PORT) - ) altgpio_bit_i ( - .inclock(inclock), - .outclock(outclock), - .phy_mem_clock(phy_mem_clock), - .inclocken(inclocken), - .outclocken(outclocken), - .oe(oe_wire), - .din(din_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]), - .dout(dout_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]), - .pad(pad_io[i]), - .pad_b(pad_io_b[i]), - .aset(aclr_aset_wire), - .sclr(sclr_wire), - .fr_clock(fr_clock[i]), - .hr_clock(hr_clock), - .mimic_clock(mimic_clock[i]), - .nsleep(nsleep_wire) - ); - end - end - endgenerate - - generate - if ((PIN_TYPE == "input" || PIN_TYPE == "bidir") && (ENABLE_HR_CLOCK == "true")) - begin - if (ENABLE_PHASE_INVERT_CTRL_PORT == "true") - begin - if (SYNC_MODE == "clear") - begin : clock_divider_sync_mode_invert_hr_clock - fiftyfivenm_io_clock_divider - #( - .invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK), - .use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT), - .sync_mode(SYNC_MODE) - ) io_clkdiv ( - .clk(inclock), - .phaseinvertctrl(invert_hr_clock), - .sreset(sclr_wire), - .clkout(hr_clock) - ); - end - else - begin : clock_divider_invert_hr_clock - fiftyfivenm_io_clock_divider - #( - .invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK), - .use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT), - .sync_mode(SYNC_MODE) - ) io_clkdiv ( - .clk(inclock), - .phaseinvertctrl(invert_hr_clock), - .clkout(hr_clock) - `ifndef ALTERA_RESERVED_QIS - , - .sreset(1'b0) - `endif - ); - end - end - else - begin - if (SYNC_MODE == "clear") - begin : clock_divider_sync_mode - fiftyfivenm_io_clock_divider - #( - .invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK), - .use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT), - .sync_mode(SYNC_MODE) - ) io_clkdiv ( - .clk(inclock), - .sreset(sclr_wire), - .clkout(hr_clock) - `ifndef ALTERA_RESERVED_QIS - , - .phaseinvertctrl(1'b0) - `endif - ); - end - else - begin : clock_divider - fiftyfivenm_io_clock_divider - #( - .invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK), - .use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT), - .sync_mode(SYNC_MODE) - ) io_clkdiv ( - .clk(inclock), - .clkout(hr_clock) - `ifndef ALTERA_RESERVED_QIS - , - .sreset(1'b0), - .phaseinvertctrl(1'b0) - `endif - ); - end - end - end - else begin - assign hr_clock = 1'b0; - end - endgenerate - -endmodule diff --git a/fw/rtl/intel/pll/intel_pll.ppf b/fw/rtl/intel/pll/intel_pll.ppf deleted file mode 100644 index bf13a5c..0000000 --- a/fw/rtl/intel/pll/intel_pll.ppf +++ /dev/null @@ -1,11 +0,0 @@ - - - - - - - - - - - diff --git a/fw/rtl/intel/pll/intel_pll.qip b/fw/rtl/intel/pll/intel_pll.qip deleted file mode 100644 index b7fa58d..0000000 --- a/fw/rtl/intel/pll/intel_pll.qip +++ /dev/null @@ -1,5 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "21.1" -set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "intel_pll.v"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "intel_pll.ppf"] diff --git a/fw/rtl/intel/pll/intel_pll.v b/fw/rtl/intel/pll/intel_pll.v deleted file mode 100644 index 64aa37d..0000000 --- a/fw/rtl/intel/pll/intel_pll.v +++ /dev/null @@ -1,340 +0,0 @@ -// megafunction wizard: %ALTPLL% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altpll - -// ============================================================ -// File Name: intel_pll.v -// Megafunction Name(s): -// altpll -// -// Simulation Library Files(s): -// -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 21.1.0 Build 842 10/21/2021 SJ Lite Edition -// ************************************************************ - - -//Copyright (C) 2021 Intel Corporation. All rights reserved. -//Your use of Intel Corporation's design tools, logic functions -//and other software and tools, and any partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Intel Program License -//Subscription Agreement, the Intel Quartus Prime License Agreement, -//the Intel FPGA IP License Agreement, or other applicable license -//agreement, including, without limitation, that your use is for -//the sole purpose of programming logic devices manufactured by -//Intel and sold by Intel or its authorized distributors. Please -//refer to the applicable agreement for further details, at -//https://fpgasoftware.intel.com/eula. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module intel_pll ( - inclk0, - c0, - c1, - locked); - - input inclk0; - output c0; - output c1; - output locked; - - wire [0:0] sub_wire2 = 1'h0; - wire [4:0] sub_wire3; - wire sub_wire6; - wire sub_wire0 = inclk0; - wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; - wire [1:1] sub_wire5 = sub_wire3[1:1]; - wire [0:0] sub_wire4 = sub_wire3[0:0]; - wire c0 = sub_wire4; - wire c1 = sub_wire5; - wire locked = sub_wire6; - - altpll altpll_component ( - .inclk (sub_wire1), - .clk (sub_wire3), - .locked (sub_wire6), - .activeclock (), - .areset (1'b0), - .clkbad (), - .clkena ({6{1'b1}}), - .clkloss (), - .clkswitch (1'b0), - .configupdate (1'b0), - .enable0 (), - .enable1 (), - .extclk (), - .extclkena ({4{1'b1}}), - .fbin (1'b1), - .fbmimicbidir (), - .fbout (), - .fref (), - .icdrclk (), - .pfdena (1'b1), - .phasecounterselect ({4{1'b1}}), - .phasedone (), - .phasestep (1'b1), - .phaseupdown (1'b1), - .pllena (1'b1), - .scanaclr (1'b0), - .scanclk (1'b0), - .scanclkena (1'b1), - .scandata (1'b0), - .scandataout (), - .scandone (), - .scanread (1'b0), - .scanwrite (1'b0), - .sclkout0 (), - .sclkout1 (), - .vcooverrange (), - .vcounderrange ()); - defparam - altpll_component.bandwidth_type = "AUTO", - altpll_component.clk0_divide_by = 1, - altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 2, - altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 1, - altpll_component.clk1_duty_cycle = 50, - altpll_component.clk1_multiply_by = 2, - altpll_component.clk1_phase_shift = "-1500", - altpll_component.compensate_clock = "CLK0", - altpll_component.inclk0_input_frequency = 20000, - altpll_component.intended_device_family = "MAX 10", - altpll_component.lpm_hint = "CBX_MODULE_PREFIX=intel_pll", - altpll_component.lpm_type = "altpll", - altpll_component.operation_mode = "NORMAL", - altpll_component.pll_type = "AUTO", - altpll_component.port_activeclock = "PORT_UNUSED", - altpll_component.port_areset = "PORT_UNUSED", - altpll_component.port_clkbad0 = "PORT_UNUSED", - altpll_component.port_clkbad1 = "PORT_UNUSED", - altpll_component.port_clkloss = "PORT_UNUSED", - altpll_component.port_clkswitch = "PORT_UNUSED", - altpll_component.port_configupdate = "PORT_UNUSED", - altpll_component.port_fbin = "PORT_UNUSED", - altpll_component.port_inclk0 = "PORT_USED", - altpll_component.port_inclk1 = "PORT_UNUSED", - altpll_component.port_locked = "PORT_USED", - altpll_component.port_pfdena = "PORT_UNUSED", - altpll_component.port_phasecounterselect = "PORT_UNUSED", - altpll_component.port_phasedone = "PORT_UNUSED", - altpll_component.port_phasestep = "PORT_UNUSED", - altpll_component.port_phaseupdown = "PORT_UNUSED", - altpll_component.port_pllena = "PORT_UNUSED", - altpll_component.port_scanaclr = "PORT_UNUSED", - altpll_component.port_scanclk = "PORT_UNUSED", - altpll_component.port_scanclkena = "PORT_UNUSED", - altpll_component.port_scandata = "PORT_UNUSED", - altpll_component.port_scandataout = "PORT_UNUSED", - altpll_component.port_scandone = "PORT_UNUSED", - altpll_component.port_scanread = "PORT_UNUSED", - altpll_component.port_scanwrite = "PORT_UNUSED", - altpll_component.port_clk0 = "PORT_USED", - altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_UNUSED", - altpll_component.port_clk3 = "PORT_UNUSED", - altpll_component.port_clk4 = "PORT_UNUSED", - altpll_component.port_clk5 = "PORT_UNUSED", - altpll_component.port_clkena0 = "PORT_UNUSED", - altpll_component.port_clkena1 = "PORT_UNUSED", - altpll_component.port_clkena2 = "PORT_UNUSED", - altpll_component.port_clkena3 = "PORT_UNUSED", - altpll_component.port_clkena4 = "PORT_UNUSED", - altpll_component.port_clkena5 = "PORT_UNUSED", - altpll_component.port_extclk0 = "PORT_UNUSED", - altpll_component.port_extclk1 = "PORT_UNUSED", - altpll_component.port_extclk2 = "PORT_UNUSED", - altpll_component.port_extclk3 = "PORT_UNUSED", - altpll_component.self_reset_on_loss_lock = "ON", - altpll_component.width_clock = 5; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" -// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" -// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" -// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" -// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000" -// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" -// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" -// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" -// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" -// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-54.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -// Retrieval info: PRIVATE: RECONFIG_FILE STRING "intel_pll.mif" -// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" -// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -// Retrieval info: PRIVATE: SPREAD_USE STRING "0" -// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" -// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" -// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" -// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: USE_CLK0 STRING "1" -// Retrieval info: PRIVATE: USE_CLK1 STRING "1" -// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" -// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" -// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" -// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" -// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-1500" -// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON" -// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" -// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" -// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll.ppf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL intel_pll_bb.v FALSE -// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/fw/rtl/mcu/mcu_spi.sv b/fw/rtl/mcu/mcu_spi.sv new file mode 100644 index 0000000..9cebb5f --- /dev/null +++ b/fw/rtl/mcu/mcu_spi.sv @@ -0,0 +1,92 @@ +module mcu_spi ( + input clk, + input reset, + + output logic frame_start, + output logic data_ready, + output logic [7:0] rx_data, + input [7:0] tx_data, + + input mcu_clk, + input mcu_cs, + input mcu_mosi, + output logic mcu_miso +); + + logic [2:0] mcu_clk_ff; + logic [2:0] mcu_cs_ff; + + always_ff @(posedge clk) begin + mcu_clk_ff <= {mcu_clk_ff[1:0], mcu_clk}; + mcu_cs_ff <= {mcu_cs_ff[1:0], mcu_cs}; + end + + logic mcu_clk_falling; + logic mcu_clk_rising; + logic mcu_cs_falling; + logic mcu_cs_rising; + + always_comb begin + mcu_clk_falling = mcu_clk_ff[2] && !mcu_clk_ff[1]; + mcu_clk_rising = !mcu_clk_ff[2] && mcu_clk_ff[1]; + mcu_cs_falling = mcu_cs_ff[2] && !mcu_cs_ff[1]; + mcu_cs_rising = !mcu_cs_ff[2] && mcu_cs_ff[1]; + end + + logic mcu_dq_in; + logic mcu_dq_out; + logic mcu_miso_out; + + assign mcu_miso = mcu_cs_ff[1] ? 1'bZ : mcu_miso_out; + + always_ff @(posedge clk) begin + mcu_dq_in <= mcu_mosi; + mcu_miso_out <= mcu_dq_out; + end + + logic [7:0] spi_tx_shift; + + assign mcu_dq_out = spi_tx_shift[7]; + + logic spi_enabled; + logic [2:0] spi_bit_counter; + + always_ff @(posedge clk) begin + frame_start <= 1'b0; + data_ready <= 1'b0; + + if (reset) begin + spi_enabled <= 1'b0; + spi_bit_counter <= 3'd0; + end else begin + if (mcu_cs_falling) begin + spi_enabled <= 1'b1; + spi_bit_counter <= 3'd0; + frame_start <= 1'b1; + end + + if (mcu_cs_rising) begin + spi_enabled <= 1'b0; + end + + if (spi_enabled) begin + if (mcu_clk_rising) begin + if (spi_bit_counter == 3'd0) begin + spi_tx_shift <= tx_data; + end else begin + spi_tx_shift <= {spi_tx_shift[6:0], 1'b0}; + end + end + + if (mcu_clk_falling) begin + spi_bit_counter <= spi_bit_counter + 1'd1; + rx_data <= {rx_data[6:0], mcu_dq_in}; + if (spi_bit_counter == 3'd7) begin + data_ready <= 1'b1; + end + end + end + end + end + +endmodule diff --git a/fw/rtl/mcu/mcu_top.sv b/fw/rtl/mcu/mcu_top.sv new file mode 100644 index 0000000..76e9996 --- /dev/null +++ b/fw/rtl/mcu/mcu_top.sv @@ -0,0 +1,901 @@ +module mcu_top ( + input clk, + input reset, + + n64_scb.controller n64_scb, + dd_scb.controller dd_scb, + usb_scb.controller usb_scb, + dma_scb.controller usb_dma_scb, + sd_scb.controller sd_scb, + dma_scb.controller sd_dma_scb, + flash_scb.controller flash_scb, + vendor_scb.controller vendor_scb, + + fifo_bus.controller fifo_bus, + mem_bus.controller mem_bus, + + input sd_det, + input button, + + output logic mcu_int, + input mcu_clk, + input mcu_cs, + input mcu_mosi, + output mcu_miso +); + + // Button input synchronization + + logic [2:0] sd_det_ff; + logic [2:0] button_ff; + + always_ff @(posedge clk) begin + sd_det_ff <= {sd_det_ff[1:0], sd_det}; + button_ff <= {button_ff[1:0], button}; + end + + + // MCU <-> FPGA transport + + logic frame_start; + logic data_ready; + logic [7:0] rdata; + logic [7:0] wdata; + + mcu_spi mcu_spi_inst ( + .clk(clk), + .reset(reset), + + .frame_start(frame_start), + .data_ready(data_ready), + .rx_data(rdata), + .tx_data(wdata), + + .mcu_clk(mcu_clk), + .mcu_cs(mcu_cs), + .mcu_mosi(mcu_mosi), + .mcu_miso(mcu_miso) + ); + + + // Protocol controller + + const bit [7:0] FPGA_ID = 8'h64; + + typedef enum bit [1:0] { + PHASE_CMD, + PHASE_ADDRESS, + PHASE_DATA, + PHASE_NOP + } phase_e; + + typedef enum bit [7:0] { + CMD_IDENTIFY, + CMD_REG_READ, + CMD_REG_WRITE, + CMD_MEM_READ, + CMD_MEM_WRITE, + CMD_USB_STATUS, + CMD_USB_READ, + CMD_USB_WRITE + } cmd_e; + + phase_e phase; + cmd_e cmd; + + logic [1:0] counter; + logic [7:0] address; + + logic reg_read; + logic reg_write; + logic [31:0] reg_rdata; + logic [31:0] reg_wdata; + + logic mem_read; + logic mem_write; + logic [15:0] mem_rdata; + logic [15:0] mem_wdata; + logic mem_word_select; + + always_ff @(posedge clk) begin + fifo_bus.rx_read <= 1'b0; + fifo_bus.tx_write <= 1'b0; + + reg_read <= 1'b0; + reg_write <= 1'b0; + + mem_read <= 1'b0; + mem_write <= 1'b0; + + if (reset) begin + end else begin + if (frame_start) begin + counter <= 2'd0; + phase <= PHASE_CMD; + end + + if (reg_read || reg_write || (mem_word_select && (mem_read || mem_write))) begin + address <= address + 1'd1; + end + + if (data_ready) begin + case (phase) + PHASE_CMD: begin + cmd <= cmd_e'(rdata); + phase <= PHASE_ADDRESS; + + if (rdata == CMD_USB_STATUS) begin + phase <= PHASE_NOP; + end + + if (rdata == CMD_USB_READ) begin + fifo_bus.rx_read <= 1'b1; + phase <= PHASE_DATA; + end + + if (rdata == CMD_USB_WRITE) begin + phase <= PHASE_DATA; + end + end + + PHASE_ADDRESS: begin + address <= rdata; + phase <= PHASE_DATA; + + if (cmd == CMD_REG_READ) begin + reg_read <= 1'b1; + end + + if (cmd == CMD_MEM_READ) begin + mem_read <= 1'b1; + mem_word_select <= 1'b0; + end + end + + PHASE_DATA: begin + counter <= counter + 1'd1; + + if (cmd == CMD_REG_READ) begin + if (counter == 2'd3) begin + reg_read <= 1'd1; + end + end + + if (cmd == CMD_REG_WRITE) begin + case (counter) + 2'd0: reg_wdata[7:0] <= rdata; + 2'd1: reg_wdata[15:8] <= rdata; + 2'd2: reg_wdata[23:16] <= rdata; + 2'd3: reg_wdata[31:24] <= rdata; + endcase + if (counter == 2'd3) begin + reg_write <= 1'd1; + end + end + + if (cmd == CMD_MEM_READ) begin + if (counter[0]) begin + mem_read <= 1'b1; + mem_word_select <= ~mem_word_select; + end + end + + if (cmd == CMD_MEM_WRITE) begin + case (counter[0]) + 1'd0: mem_wdata[15:8] <= rdata; + 1'd1: mem_wdata[7:0] <= rdata; + endcase + if (counter[0]) begin + mem_write <= 1'b1; + mem_word_select <= counter[1]; + end + end + + if (cmd == CMD_USB_READ) begin + phase <= PHASE_NOP; + end + + if (cmd == CMD_USB_WRITE) begin + fifo_bus.tx_write <= 1'b1; + fifo_bus.tx_wdata <= rdata; + phase <= PHASE_NOP; + end + end + + PHASE_NOP: begin end + endcase + end + end + end + + always_comb begin + wdata = 8'h00; + + case (cmd) + CMD_IDENTIFY: begin + wdata = FPGA_ID; + end + + CMD_REG_READ: begin + case (counter) + 2'd0: wdata = reg_rdata[7:0]; + 2'd1: wdata = reg_rdata[15:8]; + 2'd2: wdata = reg_rdata[23:16]; + 2'd3: wdata = reg_rdata[31:24]; + endcase + end + + CMD_REG_WRITE: begin + wdata = 8'h00; + end + + CMD_MEM_READ: begin + case (counter[0]) + 1'd0: wdata = mem_rdata[15:8]; + 1'd1: wdata = mem_rdata[7:0]; + endcase + end + + CMD_MEM_WRITE: begin + wdata = 8'h00; + end + + CMD_USB_STATUS: begin + wdata = {6'd0, ~fifo_bus.tx_full, ~fifo_bus.rx_empty}; + end + + CMD_USB_READ: begin + wdata = fifo_bus.rx_rdata; + end + + CMD_USB_WRITE: begin + wdata = 8'h00; + end + endcase + end + + + // Mem bus controller + + logic [15:0] mem_buffer [0:511]; + + logic mem_start; + logic mem_stop; + logic mem_direction; + logic [8:0] mem_length; + logic [31:0] mem_address; + + logic mem_busy; + logic mem_stop_pending; + logic [8:0] mem_counter; + + always_ff @(posedge clk) begin + if (reset) begin + mem_busy <= 1'b0; + mem_stop_pending <= 1'b0; + mem_bus.request <= 1'b0; + end else begin + if (mem_read) begin + mem_rdata <= mem_buffer[{address, mem_word_select}]; + end + + if (mem_write) begin + mem_buffer[{address, mem_word_select}] <= mem_wdata; + end + + if (mem_stop) begin + mem_stop_pending <= mem_busy; + end else if (mem_start && !mem_busy) begin + mem_bus.write <= mem_direction; + mem_bus.address <= mem_address; + mem_busy <= 1'b1; + mem_counter <= 9'd0; + end + + if (mem_busy) begin + if (!mem_bus.request) begin + mem_bus.request <= 1'b1; + mem_bus.wdata <= mem_buffer[mem_counter]; + end + + if (mem_bus.ack) begin + mem_bus.request <= 1'b0; + mem_bus.address <= mem_bus.address + 2'd2; + mem_counter <= mem_counter + 1'd1; + if (!mem_bus.write) begin + mem_buffer[mem_counter] <= mem_bus.rdata; + end + if ((mem_counter == mem_length) || mem_stop_pending) begin + mem_busy <= 1'b0; + mem_stop_pending <= 1'b0; + end + end + end + end + end + + always_comb begin + mem_bus.wmask = 2'b11; + end + + + // Register list + + typedef enum bit [7:0] { + REG_MEM_ADDRESS, + REG_MEM_SCR, + REG_USB_SCR, + REG_USB_DMA_ADDRESS, + REG_USB_DMA_LENGTH, + REG_USB_DMA_SCR, + REG_CFG_SCR, + REG_CFG_DATA_0, + REG_CFG_DATA_1, + REG_CFG_CMD, + REG_CFG_VERSION, + REG_FLASHRAM_SCR, + REG_FLASH_SCR, + REG_RTC_SCR, + REG_RTC_TIME_0, + REG_RTC_TIME_1, + REG_SD_SCR, + REG_SD_ARG, + REG_SD_CMD, + REG_SD_RSP_0, + REG_SD_RSP_1, + REG_SD_RSP_2, + REG_SD_RSP_3, + REG_SD_DAT, + REG_SD_DMA_ADDRESS, + REG_SD_DMA_LENGTH, + REG_SD_DMA_SCR, + REG_DD_SCR, + REG_DD_CMD_DATA, + REG_DD_HEAD_TRACK, + REG_DD_SECTOR_INFO, + REG_DD_DRIVE_ID, + REG_VENDOR_SCR, + REG_VENDOR_DATA, + REG_DEBUG_0, + REG_DEBUG_1 + } reg_address_e; + + logic bootloader_skip; + + assign n64_scb.cfg_version = 32'h53437632; + + logic dd_bm_ack; + + + // Register read logic + + always_ff @(posedge clk) begin + if (reg_read) begin + reg_rdata <= 32'd0; + + case (address) + REG_MEM_ADDRESS: begin + reg_rdata <= mem_address; + end + + REG_MEM_SCR: begin + reg_rdata <= { + 28'd0, + mem_busy, + 3'b000 + }; + end + + REG_USB_SCR: begin + reg_rdata <= { + 2'd0, + usb_scb.pwrsav, + usb_scb.reset_state, + usb_scb.tx_count, + usb_scb.rx_count, + 2'b00, + usb_scb.reset_pending, + ~fifo_bus.tx_full, + ~fifo_bus.rx_empty, + 1'b0 + }; + end + + REG_USB_DMA_ADDRESS: begin + reg_rdata <= { + 5'd0, + usb_dma_scb.starting_address + }; + end + + REG_USB_DMA_LENGTH: begin + reg_rdata <= { + 5'd0, + usb_dma_scb.transfer_length + }; + end + + REG_USB_DMA_SCR: begin + reg_rdata <= { + 28'd0, + usb_dma_scb.busy, + usb_dma_scb.direction, + 2'b00 + }; + end + + REG_CFG_SCR: begin + reg_rdata <= { + ~button_ff[2], + 19'd0, + n64_scb.rom_extended_enabled, + n64_scb.eeprom_16k_mode, + n64_scb.eeprom_enabled, + n64_scb.ddipl_enabled, + n64_scb.dd_enabled, + n64_scb.flashram_enabled, + n64_scb.sram_banked, + n64_scb.sram_enabled, + n64_scb.rom_shadow_enabled, + n64_scb.rom_write_enabled, + bootloader_skip, + n64_scb.bootloader_enabled + }; + end + + REG_CFG_DATA_0: begin + reg_rdata <= n64_scb.cfg_rdata[0]; + end + + REG_CFG_DATA_1: begin + reg_rdata <= n64_scb.cfg_rdata[1]; + end + + REG_CFG_CMD: begin + reg_rdata <= { + 23'd0, + n64_scb.cfg_pending, + n64_scb.cfg_cmd + }; + end + + REG_CFG_VERSION: begin + reg_rdata <= n64_scb.cfg_version; + end + + REG_FLASHRAM_SCR: begin + reg_rdata <= { + 18'd0, + n64_scb.flashram_write_or_erase, + n64_scb.flashram_sector_or_all, + n64_scb.flashram_sector, + n64_scb.flashram_pending, + 1'b0 + }; + end + + REG_FLASH_SCR: begin + reg_rdata <= { + 31'd0, + flash_scb.erase_pending + }; + end + + REG_RTC_SCR: begin + reg_rdata <= { + 24'h525443, + 7'd0, + n64_scb.rtc_pending + }; + end + + REG_RTC_TIME_0: begin + reg_rdata <= { + 5'd0, n64_scb.rtc_rdata[28:26], + 2'd0, n64_scb.rtc_rdata[19:14], + 1'd0, n64_scb.rtc_rdata[13:7], + 1'd0, n64_scb.rtc_rdata[6:0] + }; + end + + REG_RTC_TIME_1: begin + reg_rdata <= { + 8'd0, + n64_scb.rtc_rdata[41:34], + 3'd0, n64_scb.rtc_rdata[33:29], + 2'd0, n64_scb.rtc_rdata[25:20] + }; + end + + REG_SD_SCR: begin + reg_rdata <= { + 4'd0, + sd_scb.tx_count, + sd_scb.rx_count, + ~sd_det_ff[2], + sd_scb.card_busy, + sd_scb.cmd_error, + sd_scb.cmd_busy, + sd_scb.clock_mode + }; + end + + REG_SD_ARG: begin + reg_rdata <= sd_scb.cmd_arg; + end + + REG_SD_CMD: begin + reg_rdata <= { + 22'd0, + sd_scb.cmd_ignore_crc, + sd_scb.cmd_long_response, + sd_scb.cmd_reserved_response, + sd_scb.cmd_skip_response, + sd_scb.cmd_index + }; + end + + REG_SD_RSP_0: begin + reg_rdata <= sd_scb.cmd_rsp[31:0]; + end + + REG_SD_RSP_1: begin + reg_rdata <= sd_scb.cmd_rsp[63:32]; + end + + REG_SD_RSP_2: begin + reg_rdata <= sd_scb.cmd_rsp[95:64]; + end + + REG_SD_RSP_3: begin + reg_rdata <= sd_scb.cmd_rsp[127:96]; + end + + REG_SD_DAT: begin + reg_rdata <= { + 18'd0, + sd_scb.dat_error, + sd_scb.dat_busy, + 12'd0 + }; + end + + REG_SD_DMA_ADDRESS: begin + reg_rdata <= { + 5'd0, + sd_dma_scb.starting_address + }; + end + + REG_SD_DMA_LENGTH: begin + reg_rdata <= { + 5'd0, + sd_dma_scb.transfer_length + }; + end + + REG_SD_DMA_SCR: begin + reg_rdata <= { + 28'd0, + sd_dma_scb.busy, + sd_dma_scb.direction, + 2'b00 + }; + end + + REG_DD_SCR: begin + reg_rdata <= { + 14'd0, + dd_bm_ack, + dd_scb.bm_micro_error, + dd_scb.bm_transfer_c2, + dd_scb.bm_transfer_data, + dd_scb.bm_transfer_blocks, + dd_scb.bm_transfer_mode, + 1'b0, + dd_scb.bm_stop_pending, + 1'b0, + dd_scb.bm_start_pending, + dd_scb.disk_changed, + dd_scb.disk_inserted, + 1'b0, + dd_scb.bm_pending, + 1'b0, + dd_scb.cmd_pending, + 1'b0, + dd_scb.hard_reset + }; + end + + REG_DD_CMD_DATA: begin + reg_rdata <= {8'd0, dd_scb.cmd, dd_scb.data}; + end + + REG_DD_HEAD_TRACK: begin + reg_rdata <= {18'd0, dd_scb.index_lock, dd_scb.head_track}; + end + + REG_DD_SECTOR_INFO: begin + reg_rdata <= { + dd_scb.sectors_in_block, + dd_scb.sector_size_full, + dd_scb.sector_size, + dd_scb.sector_num + }; + end + + REG_VENDOR_SCR: begin + reg_rdata <= vendor_scb.control_rdata; + end + + REG_VENDOR_DATA: begin + reg_rdata <= vendor_scb.data_rdata; + end + + REG_DEBUG_0: begin + reg_rdata <= n64_scb.pi_debug[31:0]; + end + + REG_DEBUG_1: begin + reg_rdata <= { + 28'd0, + n64_scb.pi_debug[35:32] + }; + end + endcase + end + end + + + // Register write logic + + always_ff @(posedge clk) begin + mem_start <= 1'b0; + mem_stop <= 1'b0; + + usb_scb.write_buffer_flush <= 1'b0; + usb_scb.reset_ack <= 1'b0; + usb_scb.fifo_flush <= 1'b0; + + usb_dma_scb.start <= 1'b0; + usb_dma_scb.stop <= 1'b0; + + sd_scb.cmd_start <= 1'b0; + sd_scb.dat_fifo_flush <= 1'b0; + sd_scb.dat_start_write <= 1'b0; + sd_scb.dat_start_read <= 1'b0; + sd_scb.dat_stop <= 1'b0; + + sd_dma_scb.start <= 1'b0; + sd_dma_scb.stop <= 1'b0; + + n64_scb.cfg_done <= 1'b0; + n64_scb.cfg_error <= 1'b0; + n64_scb.cfg_irq <= 1'b0; + + n64_scb.flashram_done <= 1'b0; + + n64_scb.rtc_done <= 1'b0; + + dd_scb.hard_reset_clear <= 1'b0; + dd_scb.cmd_ready <= 1'b0; + dd_scb.bm_start_clear <= 1'b0; + dd_scb.bm_stop_clear <= 1'b0; + dd_scb.bm_clear <= 1'b0; + dd_scb.bm_ready <= 1'b0; + + vendor_scb.control_valid <= 1'b0; + + if (n64_scb.n64_nmi) begin + n64_scb.bootloader_enabled <= !bootloader_skip; + end + + if (flash_scb.erase_done) begin + flash_scb.erase_pending <= 1'b0; + end + + if (dd_scb.bm_interrupt_ack) begin + dd_bm_ack <= 1'b1; + end + + if (reset) begin + mcu_int <= 1'b0; + sd_scb.clock_mode <= 2'd0; + n64_scb.rom_extended_enabled <= 1'b0; + n64_scb.eeprom_16k_mode <= 1'b0; + n64_scb.eeprom_enabled <= 1'b0; + n64_scb.dd_enabled <= 1'b0; + n64_scb.ddipl_enabled <= 1'b0; + n64_scb.flashram_enabled <= 1'b0; + n64_scb.sram_banked <= 1'b0; + n64_scb.sram_enabled <= 1'b0; + n64_scb.rom_shadow_enabled <= 1'b0; + n64_scb.rom_write_enabled <= 1'b0; + bootloader_skip <= 1'b0; + n64_scb.bootloader_enabled <= 1'b1; + flash_scb.erase_pending <= 1'b0; + dd_bm_ack <= 1'b0; + n64_scb.rtc_wdata_valid <= 1'b0; + end else if (reg_write) begin + case (address) + REG_MEM_ADDRESS: begin + mem_address <= reg_wdata; + end + + REG_MEM_SCR: begin + { + mem_length, + mem_direction, + mem_stop, + mem_start + } <= {(reg_wdata[14:5] - 1'd1), reg_wdata[2:0]}; + end + + REG_USB_SCR: begin + { + usb_scb.write_buffer_flush, + usb_scb.reset_ack, + usb_scb.fifo_flush + } <= {reg_wdata[5:4], reg_wdata[0]}; + end + + REG_USB_DMA_ADDRESS: begin + usb_dma_scb.starting_address <= reg_wdata[26:0]; + end + + REG_USB_DMA_LENGTH: begin + usb_dma_scb.transfer_length <= reg_wdata[26:0]; + end + + REG_USB_DMA_SCR: begin + { + usb_dma_scb.direction, + usb_dma_scb.stop, + usb_dma_scb.start + } <= reg_wdata[2:0]; + end + + REG_CFG_SCR: begin + { + n64_scb.rom_extended_enabled, + n64_scb.eeprom_16k_mode, + n64_scb.eeprom_enabled, + n64_scb.ddipl_enabled, + n64_scb.dd_enabled, + n64_scb.flashram_enabled, + n64_scb.sram_banked, + n64_scb.sram_enabled, + n64_scb.rom_shadow_enabled, + n64_scb.rom_write_enabled, + bootloader_skip, + n64_scb.bootloader_enabled + } <= reg_wdata[11:0]; + end + + REG_CFG_DATA_0: begin + n64_scb.cfg_wdata[0] <= reg_wdata; + end + + REG_CFG_DATA_1: begin + n64_scb.cfg_wdata[1] <= reg_wdata; + end + + REG_CFG_CMD: begin + { + n64_scb.cfg_irq, + n64_scb.cfg_error, + n64_scb.cfg_done + } <= reg_wdata[11:9]; + end + + REG_FLASHRAM_SCR: begin + n64_scb.flashram_done <= reg_wdata[0]; + end + + REG_FLASH_SCR: begin + flash_scb.erase_pending <= 1'b1; + flash_scb.erase_block <= reg_wdata[23:16]; + end + + REG_RTC_SCR: begin + n64_scb.rtc_done <= reg_wdata[1]; + end + + REG_RTC_TIME_0: begin + n64_scb.rtc_wdata_valid <= 1'b0; + n64_scb.rtc_wdata[28:26] <= reg_wdata[26:24]; + n64_scb.rtc_wdata[19:14] <= reg_wdata[21:16]; + n64_scb.rtc_wdata[13:7] <= reg_wdata[14:8]; + n64_scb.rtc_wdata[6:0] <= reg_wdata[6:0]; + end + + REG_RTC_TIME_1: begin + n64_scb.rtc_wdata_valid <= 1'b1; + n64_scb.rtc_wdata[41:34] <= reg_wdata[23:16]; + n64_scb.rtc_wdata[33:29] <= reg_wdata[12:8]; + n64_scb.rtc_wdata[25:20] <= reg_wdata[5:0]; + end + + REG_SD_SCR: begin + sd_scb.clock_mode <= reg_wdata[1:0]; + end + + REG_SD_ARG: begin + sd_scb.cmd_arg <= reg_wdata; + end + + REG_SD_CMD: begin + sd_scb.cmd_start <= 1'b1; + sd_scb.cmd_ignore_crc <= reg_wdata[9]; + sd_scb.cmd_long_response <= reg_wdata[8]; + sd_scb.cmd_reserved_response <= reg_wdata[7]; + sd_scb.cmd_skip_response <= reg_wdata[6]; + sd_scb.cmd_index <= reg_wdata[5:0]; + end + + REG_SD_DAT: begin + sd_scb.dat_blocks <= reg_wdata[11:4]; + sd_scb.dat_stop <= reg_wdata[3]; + sd_scb.dat_start_read <= reg_wdata[2]; + sd_scb.dat_start_write <= reg_wdata[1]; + sd_scb.dat_fifo_flush <= reg_wdata[0]; + end + + REG_SD_DMA_ADDRESS: begin + sd_dma_scb.starting_address <= reg_wdata[26:0]; + end + + REG_SD_DMA_LENGTH: begin + sd_dma_scb.transfer_length <= reg_wdata[26:0]; + end + + REG_SD_DMA_SCR: begin + { + sd_dma_scb.direction, + sd_dma_scb.stop, + sd_dma_scb.start + } <= reg_wdata[2:0]; + end + + REG_DD_SCR: begin + dd_scb.bm_clear <= reg_wdata[19]; + if (reg_wdata[18]) begin + dd_bm_ack <= 1'b0; + end + dd_scb.bm_micro_error <= reg_wdata[16]; + dd_scb.bm_transfer_c2 <= reg_wdata[15]; + dd_scb.bm_transfer_data <= reg_wdata[14]; + dd_scb.bm_stop_clear <= reg_wdata[11]; + dd_scb.bm_start_clear <= reg_wdata[9]; + dd_scb.disk_changed <= reg_wdata[7]; + dd_scb.disk_inserted <= reg_wdata[6]; + dd_scb.bm_ready <= reg_wdata[5]; + dd_scb.cmd_ready <= reg_wdata[3]; + dd_scb.hard_reset_clear <= reg_wdata[1]; + end + + REG_DD_CMD_DATA: begin + dd_scb.cmd_data <= reg_wdata[15:0]; + end + + REG_DD_HEAD_TRACK: begin + {dd_scb.index_lock, dd_scb.head_track} <= reg_wdata[13:0]; + end + + REG_DD_DRIVE_ID: begin + dd_scb.drive_id <= reg_wdata[15:0]; + end + + REG_VENDOR_SCR: begin + vendor_scb.control_valid <= 1'b1; + vendor_scb.control_wdata <= reg_wdata; + end + + REG_VENDOR_DATA: begin + vendor_scb.data_wdata <= reg_wdata; + end + endcase + end + end + +endmodule diff --git a/fw/rtl/memory/mem_bus.sv b/fw/rtl/memory/mem_bus.sv new file mode 100644 index 0000000..75e92f5 --- /dev/null +++ b/fw/rtl/memory/mem_bus.sv @@ -0,0 +1,31 @@ +interface mem_bus (); + + logic request; + logic ack; + logic write; + logic [1:0] wmask; + logic [26:0] address; + logic [15:0] rdata; + logic [15:0] wdata; + + modport controller ( + output request, + input ack, + output write, + output wmask, + output address, + input rdata, + output wdata + ); + + modport memory ( + input request, + output ack, + input write, + input wmask, + input address, + output rdata, + input wdata + ); + +endinterface diff --git a/fw/rtl/memory/memory_arbiter.sv b/fw/rtl/memory/memory_arbiter.sv new file mode 100644 index 0000000..adaf700 --- /dev/null +++ b/fw/rtl/memory/memory_arbiter.sv @@ -0,0 +1,231 @@ +module memory_arbiter ( + input clk, + input reset, + + n64_scb.arbiter n64_scb, + + mem_bus.memory n64_bus, + mem_bus.memory cfg_bus, + mem_bus.memory usb_dma_bus, + mem_bus.memory sd_dma_bus, + + mem_bus.controller sdram_mem_bus, + mem_bus.controller flash_mem_bus, + mem_bus.controller bram_mem_bus +); + + typedef enum bit [1:0] { + SOURCE_N64, + SOURCE_CFG, + SOURCE_USB_DMA, + SOURCE_SD_DMA + } e_source_request; + + logic n64_sdram_request; + logic cfg_sdram_request; + logic usb_dma_sdram_request; + logic sd_dma_sdram_request; + + logic n64_flash_request; + logic cfg_flash_request; + logic usb_dma_flash_request; + logic sd_dma_flash_request; + + logic n64_bram_request; + logic cfg_bram_request; + logic usb_dma_bram_request; + logic sd_dma_bram_request; + + assign n64_sdram_request = n64_bus.request && !n64_bus.address[26]; + assign cfg_sdram_request = !n64_scb.pi_sdram_active && cfg_bus.request && !cfg_bus.address[26]; + assign usb_dma_sdram_request = !n64_scb.pi_sdram_active && usb_dma_bus.request && !usb_dma_bus.address[26]; + assign sd_dma_sdram_request = !n64_scb.pi_sdram_active && sd_dma_bus.request && !sd_dma_bus.address[26]; + + assign n64_flash_request = n64_bus.request && (n64_bus.address[26:24] == 3'b100); + assign cfg_flash_request = !n64_scb.pi_flash_active && cfg_bus.request && (cfg_bus.address[26:24] == 3'b100); + assign usb_dma_flash_request = !n64_scb.pi_flash_active && usb_dma_bus.request && (usb_dma_bus.address[26:24] == 3'b100); + assign sd_dma_flash_request = !n64_scb.pi_flash_active && sd_dma_bus.request && (sd_dma_bus.address[26:24] == 3'b100); + + assign n64_bram_request = n64_bus.request && (n64_bus.address[26:24] >= 3'b101); + assign cfg_bram_request = cfg_bus.request && (cfg_bus.address[26:24] >= 3'b101); + assign usb_dma_bram_request = usb_dma_bus.request && (usb_dma_bus.address[26:24] >= 3'b101); + assign sd_dma_bram_request = sd_dma_bus.request && (sd_dma_bus.address[26:24] >= 3'b101); + + e_source_request sdram_source_request; + + always_ff @(posedge clk) begin + if (reset) begin + sdram_mem_bus.request <= 1'b0; + end else begin + if (!sdram_mem_bus.request) begin + sdram_mem_bus.request <= ( + n64_sdram_request || + cfg_sdram_request || + usb_dma_sdram_request || + sd_dma_sdram_request + ); + + if (n64_sdram_request) begin + sdram_mem_bus.write <= n64_bus.write; + sdram_mem_bus.wmask <= n64_bus.wmask; + sdram_mem_bus.address <= n64_bus.address; + sdram_mem_bus.wdata <= n64_bus.wdata; + sdram_source_request <= SOURCE_N64; + end else if (cfg_sdram_request) begin + sdram_mem_bus.write <= cfg_bus.write; + sdram_mem_bus.wmask <= cfg_bus.wmask; + sdram_mem_bus.address <= cfg_bus.address; + sdram_mem_bus.wdata <= cfg_bus.wdata; + sdram_source_request <= SOURCE_CFG; + end else if (usb_dma_sdram_request) begin + sdram_mem_bus.write <= usb_dma_bus.write; + sdram_mem_bus.wmask <= usb_dma_bus.wmask; + sdram_mem_bus.address <= usb_dma_bus.address; + sdram_mem_bus.wdata <= usb_dma_bus.wdata; + sdram_source_request <= SOURCE_USB_DMA; + end else if (sd_dma_sdram_request) begin + sdram_mem_bus.write <= sd_dma_bus.write; + sdram_mem_bus.wmask <= sd_dma_bus.wmask; + sdram_mem_bus.address <= sd_dma_bus.address; + sdram_mem_bus.wdata <= sd_dma_bus.wdata; + sdram_source_request <= SOURCE_SD_DMA; + end + end + + if (sdram_mem_bus.ack) begin + sdram_mem_bus.request <= 1'b0; + end + end + end + + e_source_request flash_source_request; + + always_ff @(posedge clk) begin + if (reset) begin + flash_mem_bus.request <= 1'b0; + end else begin + if (!flash_mem_bus.request) begin + flash_mem_bus.request <= ( + n64_flash_request || + cfg_flash_request || + usb_dma_flash_request || + sd_dma_flash_request + ); + + if (n64_flash_request) begin + flash_mem_bus.write <= n64_bus.write; + flash_mem_bus.wmask <= n64_bus.wmask; + flash_mem_bus.address <= n64_bus.address; + flash_mem_bus.wdata <= n64_bus.wdata; + flash_source_request <= SOURCE_N64; + end else if (cfg_flash_request) begin + flash_mem_bus.write <= cfg_bus.write; + flash_mem_bus.wmask <= cfg_bus.wmask; + flash_mem_bus.address <= cfg_bus.address; + flash_mem_bus.wdata <= cfg_bus.wdata; + flash_source_request <= SOURCE_CFG; + end else if (usb_dma_flash_request) begin + flash_mem_bus.write <= usb_dma_bus.write; + flash_mem_bus.wmask <= usb_dma_bus.wmask; + flash_mem_bus.address <= usb_dma_bus.address; + flash_mem_bus.wdata <= usb_dma_bus.wdata; + flash_source_request <= SOURCE_USB_DMA; + end else if (sd_dma_flash_request) begin + flash_mem_bus.write <= sd_dma_bus.write; + flash_mem_bus.wmask <= sd_dma_bus.wmask; + flash_mem_bus.address <= sd_dma_bus.address; + flash_mem_bus.wdata <= sd_dma_bus.wdata; + flash_source_request <= SOURCE_SD_DMA; + end + end + + if (flash_mem_bus.ack) begin + flash_mem_bus.request <= 1'b0; + end + end + end + + e_source_request bram_source_request; + + always_ff @(posedge clk) begin + if (reset) begin + bram_mem_bus.request <= 1'b0; + end else begin + if (!bram_mem_bus.request) begin + bram_mem_bus.request <= ( + n64_bram_request || + cfg_bram_request || + usb_dma_bram_request || + sd_dma_bram_request + ); + + if (n64_bram_request) begin + bram_mem_bus.write <= n64_bus.write; + bram_mem_bus.wmask <= n64_bus.wmask; + bram_mem_bus.address <= n64_bus.address; + bram_mem_bus.wdata <= n64_bus.wdata; + bram_source_request <= SOURCE_N64; + end else if (cfg_bram_request) begin + bram_mem_bus.write <= cfg_bus.write; + bram_mem_bus.wmask <= cfg_bus.wmask; + bram_mem_bus.address <= cfg_bus.address; + bram_mem_bus.wdata <= cfg_bus.wdata; + bram_source_request <= SOURCE_CFG; + end else if (usb_dma_bram_request) begin + bram_mem_bus.write <= usb_dma_bus.write; + bram_mem_bus.wmask <= usb_dma_bus.wmask; + bram_mem_bus.address <= usb_dma_bus.address; + bram_mem_bus.wdata <= usb_dma_bus.wdata; + bram_source_request <= SOURCE_USB_DMA; + end else if (sd_dma_bram_request) begin + bram_mem_bus.write <= sd_dma_bus.write; + bram_mem_bus.wmask <= sd_dma_bus.wmask; + bram_mem_bus.address <= sd_dma_bus.address; + bram_mem_bus.wdata <= sd_dma_bus.wdata; + bram_source_request <= SOURCE_SD_DMA; + end + end + + if (bram_mem_bus.ack) begin + bram_mem_bus.request <= 1'b0; + end + end + end + + always_comb begin + n64_bus.ack = ( + ((sdram_source_request == SOURCE_N64) && sdram_mem_bus.ack) || + ((flash_source_request == SOURCE_N64) && flash_mem_bus.ack) || + ((bram_source_request == SOURCE_N64) && bram_mem_bus.ack) + ); + cfg_bus.ack = ( + ((sdram_source_request == SOURCE_CFG) && sdram_mem_bus.ack) || + ((flash_source_request == SOURCE_CFG) && flash_mem_bus.ack) || + ((bram_source_request == SOURCE_CFG) && bram_mem_bus.ack) + ); + usb_dma_bus.ack = ( + ((sdram_source_request == SOURCE_USB_DMA) && sdram_mem_bus.ack) || + ((flash_source_request == SOURCE_USB_DMA) && flash_mem_bus.ack) || + ((bram_source_request == SOURCE_USB_DMA) && bram_mem_bus.ack) + ); + sd_dma_bus.ack = ( + ((sdram_source_request == SOURCE_SD_DMA) && sdram_mem_bus.ack) || + ((flash_source_request == SOURCE_SD_DMA) && flash_mem_bus.ack) || + ((bram_source_request == SOURCE_SD_DMA) && bram_mem_bus.ack) + ); + + n64_bus.rdata = n64_bram_request ? bram_mem_bus.rdata : + n64_flash_request ? flash_mem_bus.rdata : + sdram_mem_bus.rdata; + cfg_bus.rdata = cfg_bram_request ? bram_mem_bus.rdata : + cfg_flash_request ? flash_mem_bus.rdata : + sdram_mem_bus.rdata; + usb_dma_bus.rdata = usb_dma_bram_request ? bram_mem_bus.rdata : + usb_dma_flash_request ? flash_mem_bus.rdata : + sdram_mem_bus.rdata; + sd_dma_bus.rdata = sd_dma_bram_request ? bram_mem_bus.rdata : + sd_dma_flash_request ? flash_mem_bus.rdata : + sdram_mem_bus.rdata; + end + +endmodule diff --git a/fw/rtl/memory/memory_bram.sv b/fw/rtl/memory/memory_bram.sv new file mode 100644 index 0000000..689dabf --- /dev/null +++ b/fw/rtl/memory/memory_bram.sv @@ -0,0 +1,164 @@ +module memory_bram ( + input clk, + + n64_scb.bram n64_scb, + + mem_bus.memory mem_bus +); + + // Request logic + + logic [1:0] last_request; + logic write; + + always_ff @(posedge clk) begin + last_request <= {last_request[0], mem_bus.request}; + end + + always_ff @(posedge clk) begin + mem_bus.ack <= mem_bus.request && last_request[0] && !last_request[1]; + end + + always_comb begin + write = mem_bus.request && !last_request[0] && mem_bus.write; + end + + + // Address decoding + + logic buffer_selected; + logic eeprom_selected; + logic dd_selected; + logic flashram_selected; + + always_comb begin + buffer_selected = 1'b0; + eeprom_selected = 1'b0; + dd_selected = 1'b0; + flashram_selected = 1'b0; + if (mem_bus.address[25:24] == 2'b01 && mem_bus.address[23:14] == 10'd0) begin + buffer_selected = mem_bus.address[13] == 1'b0; + eeprom_selected = mem_bus.address[13:11] == 3'b100; + dd_selected = mem_bus.address[13:8] == 6'b101000; + flashram_selected = mem_bus.address[13:7] == 7'b1010010; + end + end + + + // Buffer memory + + logic [15:0] buffer_bram [0:4095]; + logic [15:0] buffer_bram_rdata; + + always_ff @(posedge clk) begin + if (write && buffer_selected) begin + if (mem_bus.wmask[1]) buffer_bram[mem_bus.address[12:1]][15:8] <= mem_bus.wdata[15:8]; + if (mem_bus.wmask[0]) buffer_bram[mem_bus.address[12:1]][7:0] <= mem_bus.wdata[7:0]; + end + end + + always_ff @(posedge clk) begin + buffer_bram_rdata <= buffer_bram[mem_bus.address[12:1]]; + end + + + // EEPROM memory + + logic [7:0] eeprom_bram_high [0:1023]; + logic [7:0] eeprom_bram_low [0:1023]; + logic [7:0] eeprom_bram_high_rdata; + logic [7:0] eeprom_bram_low_rdata; + logic [7:0] eeprom_bram_high_n64_rdata; + logic [7:0] eeprom_bram_low_n64_rdata; + logic [15:0] eeprom_bram_rdata; + + always_ff @(posedge clk) begin + if (write && mem_bus.wmask[1] && eeprom_selected) begin + eeprom_bram_high[mem_bus.address[10:1]] <= mem_bus.wdata[15:8]; + end + if (n64_scb.eeprom_write && !n64_scb.eeprom_address[0]) begin + eeprom_bram_high[n64_scb.eeprom_address[10:1]] <= n64_scb.eeprom_wdata; + end + end + + always_ff @(posedge clk) begin + if (write && mem_bus.wmask[0] && eeprom_selected) begin + eeprom_bram_low[mem_bus.address[10:1]] <= mem_bus.wdata[7:0]; + end + if (n64_scb.eeprom_write && n64_scb.eeprom_address[0]) begin + eeprom_bram_low[n64_scb.eeprom_address[10:1]] <= n64_scb.eeprom_wdata; + end + end + + always_ff @(posedge clk) begin + eeprom_bram_high_rdata <= eeprom_bram_high[mem_bus.address[10:1]]; + end + + always_ff @(posedge clk) begin + eeprom_bram_low_rdata <= eeprom_bram_low[mem_bus.address[10:1]]; + end + + always_ff @(posedge clk) begin + eeprom_bram_high_n64_rdata <= eeprom_bram_high[n64_scb.eeprom_address[10:1]]; + end + + always_ff @(posedge clk) begin + eeprom_bram_low_n64_rdata <= eeprom_bram_low[n64_scb.eeprom_address[10:1]]; + end + + always_comb begin + eeprom_bram_rdata = {eeprom_bram_high_rdata, eeprom_bram_low_rdata}; + n64_scb.eeprom_rdata = n64_scb.eeprom_address[0] ? eeprom_bram_low_n64_rdata : eeprom_bram_high_n64_rdata; + end + + + // DD memory + + logic [15:0] dd_bram [0:127]; + logic [15:0] dd_bram_rdata; + + always_ff @(posedge clk) begin + if (write && dd_selected) begin + dd_bram[mem_bus.address[7:1]] <= mem_bus.wdata; + end + if (n64_scb.dd_write) begin + dd_bram[n64_scb.dd_address] <= n64_scb.dd_wdata; + end + end + + always_ff @(posedge clk) begin + dd_bram_rdata <= dd_bram[mem_bus.address[7:1]]; + end + + always_ff @(posedge clk) begin + n64_scb.dd_rdata <= dd_bram[n64_scb.dd_address]; + end + + + // FlashRAM memory + + logic [15:0] flashram_bram [0:63]; + logic [15:0] flashram_bram_rdata; + + always_ff @(posedge clk) begin + if (n64_scb.flashram_write) begin + flashram_bram[n64_scb.flashram_address] <= n64_scb.flashram_wdata; + end + end + + always_ff @(posedge clk) begin + flashram_bram_rdata <= flashram_bram[mem_bus.address[6:1]]; + end + + + // Output data mux + + always_ff @(posedge clk) begin + mem_bus.rdata <= 16'd0; + if (buffer_selected) mem_bus.rdata <= buffer_bram_rdata; + if (eeprom_selected) mem_bus.rdata <= eeprom_bram_rdata; + if (dd_selected) mem_bus.rdata <= dd_bram_rdata; + if (flashram_selected) mem_bus.rdata <= flashram_bram_rdata; + end + +endmodule diff --git a/fw/rtl/memory/memory_dma.sv b/fw/rtl/memory/memory_dma.sv new file mode 100644 index 0000000..fcba0bd --- /dev/null +++ b/fw/rtl/memory/memory_dma.sv @@ -0,0 +1,243 @@ +interface dma_scb (); + + logic start; + logic stop; + logic busy; + logic direction; + logic [26:0] starting_address; + logic [26:0] transfer_length; + + modport controller ( + output start, + output stop, + input busy, + output direction, + output starting_address, + output transfer_length + ); + + modport dma ( + input start, + input stop, + output busy, + input direction, + input starting_address, + input transfer_length + ); + +endinterface + + +module memory_dma ( + input clk, + input reset, + + dma_scb.dma dma_scb, + + fifo_bus.controller fifo_bus, + mem_bus.controller mem_bus +); + + // DMA start/stop control + + logic dma_start; + logic dma_stop; + + always_comb begin + dma_start = dma_scb.start && !dma_scb.stop && !dma_scb.busy; + dma_stop = dma_scb.stop; + end + + + // Remaining counter and FIFO enable + + logic [26:0] remaining; + logic trx_enabled; + + always_comb begin + trx_enabled = remaining > 27'd0; + end + + + // RX FIFO controller + + logic rx_rdata_pop; + logic rx_rdata_shift; + logic rx_rdata_valid; + logic [15:0] rx_buffer; + logic rx_buffer_valid; + logic [1:0] rx_buffer_counter; + logic [1:0] rx_buffer_valid_counter; + + always_comb begin + rx_buffer_valid = rx_buffer_valid_counter == 2'd2; + end + + always_ff @(posedge clk) begin + rx_rdata_pop <= ( + !rx_rdata_pop && + !fifo_bus.rx_read && + trx_enabled && + rx_buffer_counter < 2'd2 && + !fifo_bus.rx_empty && + mem_bus.write + ); + rx_rdata_shift <= 1'b0; + fifo_bus.rx_read <= rx_rdata_pop; + rx_rdata_valid <= fifo_bus.rx_read; + + if (dma_start) begin + if (dma_scb.starting_address[0]) begin + mem_bus.wmask <= 2'b01; + rx_buffer_counter <= 2'd1; + rx_buffer_valid_counter <= 2'd1; + end else begin + mem_bus.wmask <= 2'b11; + rx_buffer_counter <= 2'd0; + rx_buffer_valid_counter <= 2'd0; + end + end + + if (rx_rdata_pop) begin + rx_buffer_counter <= rx_buffer_counter + 1'd1; + end + + if (rx_rdata_shift || rx_rdata_valid) begin + rx_buffer <= {rx_buffer[7:0], fifo_bus.rx_rdata}; + rx_buffer_valid_counter <= rx_buffer_valid_counter + 1'd1; + if (remaining == 27'd0 && rx_buffer_counter == 2'd1) begin + mem_bus.wmask <= 2'b10; + rx_rdata_shift <= 1'b1; + rx_buffer_counter <= rx_buffer_counter + 1'd1; + end + end + + if (rx_buffer_valid && !mem_bus.request) begin + rx_buffer_counter <= 2'd0; + rx_buffer_valid_counter <= 2'd0; + end + end + + + // TX FIFO controller + + logic tx_wdata_push; + logic tx_wdata_first_push; + logic [7:0] tx_buffer; + logic tx_buffer_counter; + logic tx_buffer_ready; + logic tx_buffer_valid; + + always_comb begin + fifo_bus.tx_write = tx_wdata_push; + end + + always_ff @(posedge clk) begin + tx_wdata_push <= ( + !tx_wdata_push && + trx_enabled && + tx_buffer_valid && + !fifo_bus.tx_full && + !mem_bus.write + ); + + if (reset || dma_stop) begin + tx_buffer_ready <= 1'b0; + tx_buffer_valid <= 1'b0; + end + + if (dma_start) begin + tx_wdata_first_push <= 1'b1; + tx_buffer_ready <= 1'b1; + tx_buffer_valid <= 1'b0; + end + + if (tx_buffer_ready && mem_bus.request) begin + tx_buffer_ready <= 1'b0; + end + + if (mem_bus.ack) begin + tx_wdata_first_push <= 1'b0; + tx_buffer_counter <= 1'd1; + tx_buffer_valid <= 1'b1; + {fifo_bus.tx_wdata, tx_buffer} <= mem_bus.rdata; + if (tx_wdata_first_push && dma_scb.starting_address[0]) begin + fifo_bus.tx_wdata <= mem_bus.rdata[7:0]; + tx_buffer_counter <= 1'd0; + end + end + + if (tx_wdata_push) begin + tx_buffer_counter <= tx_buffer_counter - 1'd1; + fifo_bus.tx_wdata <= tx_buffer; + if (tx_buffer_counter == 1'd0) begin + tx_buffer_ready <= 1'b1; + tx_buffer_valid <= 1'b0; + end + end + end + + + // Remaining counter controller + + always_ff @(posedge clk) begin + if (reset || dma_stop) begin + remaining <= 27'd0; + end else begin + if (dma_start) begin + remaining <= dma_scb.transfer_length; + end + + if ((mem_bus.write && rx_rdata_pop) || (!mem_bus.write && tx_wdata_push)) begin + remaining <= remaining - 1'd1; + end + end + end + + + // Mem bus controller + + always_ff @(posedge clk) begin + dma_scb.busy <= mem_bus.request || trx_enabled; + end + + always_ff @(posedge clk) begin + if (reset) begin + mem_bus.request <= 1'b0; + end else begin + if (!mem_bus.request) begin + if (mem_bus.write) begin + if (rx_buffer_valid) begin + mem_bus.request <= 1'b1; + mem_bus.wdata <= rx_buffer; + end + end else begin + if (tx_buffer_ready) begin + mem_bus.request <= 1'b1; + end + end + end + end + + if (mem_bus.ack) begin + mem_bus.request <= 1'b0; + end + end + + always_ff @(posedge clk) begin + if (dma_start) begin + mem_bus.write <= dma_scb.direction; + end + end + + always_ff @(posedge clk) begin + if (dma_start) begin + mem_bus.address <= {dma_scb.starting_address[26:1], 1'b0}; + end + + if (mem_bus.ack) begin + mem_bus.address <= mem_bus.address + 2'd2; + end + end + +endmodule diff --git a/fw/rtl/memory/memory_flash.sv b/fw/rtl/memory/memory_flash.sv new file mode 100644 index 0000000..5d3abfc --- /dev/null +++ b/fw/rtl/memory/memory_flash.sv @@ -0,0 +1,492 @@ +interface flash_scb (); + + logic erase_pending; + logic erase_done; + logic [7:0] erase_block; + + modport controller ( + output erase_pending, + input erase_done, + output erase_block + ); + + modport flash ( + input erase_pending, + output erase_done, + input erase_block + ); + +endinterface + + +module flash_qspi ( + input clk, + input reset, + + input start, + input finish, + output logic busy, + output logic valid, + input output_enable, + input quad_enable, + output logic [7:0] rdata, + input [7:0] wdata, + + output logic flash_clk, + output logic flash_cs, + inout [3:0] flash_dq +); + + logic flash_dq_oe_s; + logic flash_dq_oe_q; + logic [3:0] flash_dq_out; + + assign flash_dq[0] = flash_dq_oe_s ? flash_dq_out[0] : 1'bZ; + assign flash_dq[3:1] = flash_dq_oe_q ? flash_dq_out[3:1] : 3'bZZZ; + + logic ff_clk; + logic ff_cs; + logic ff_dq_oe_s; + logic ff_dq_oe_q; + logic [3:0] ff_dq_out; + logic [3:0] ff_dq_in; + + always_ff @(posedge clk) begin + flash_clk <= ff_clk; + flash_cs <= ff_cs; + flash_dq_oe_s <= ff_dq_oe_s; + flash_dq_oe_q <= ff_dq_oe_q; + flash_dq_out <= ff_dq_out; + ff_dq_in <= flash_dq; + end + + logic running; + logic exit; + logic valid_enable; + logic quad_mode; + logic [2:0] counter; + logic [7:0] output_shift; + logic [2:0] sample_s; + logic [2:0] sample_q; + logic [2:0] valid_ff; + + assign ff_dq_out = quad_mode ? output_shift[7:4] : {3'bXXX, output_shift[7]}; + + always_ff @(posedge clk) begin + sample_s <= {sample_s[1:0], 1'b0}; + sample_q <= {sample_q[1:0], 1'b0}; + valid_ff <= {valid_ff[1:0], 1'b0}; + if (reset) begin + ff_clk <= 1'b0; + ff_cs <= 1'b1; + ff_dq_oe_s <= 1'b0; + ff_dq_oe_q <= 1'b0; + busy <= 1'b0; + running <= 1'b0; + end else begin + if (running) begin + ff_clk <= ~ff_clk; + if (!ff_clk) begin + if (counter == 3'd0) begin + busy <= 1'b0; + valid_ff[0] <= valid_enable; + end + if (!quad_mode) begin + sample_s[0] <= 1'b1; + end else begin + sample_q[0] <= 1'b1; + end + end else begin + counter <= counter - 1'd1; + if (counter == 3'd0) begin + running <= 1'b0; + end + if (!quad_mode) begin + output_shift <= {output_shift[6:0], 1'bX}; + end else begin + output_shift <= {output_shift[3:0], 4'bXXXX}; + end + end + end + + if (exit) begin + ff_cs <= 1'b1; + counter <= counter - 1'd1; + if (counter == 3'd0) begin + busy <= 1'b0; + exit <= 1'b0; + end + end + + if (!busy) begin + if (start) begin + ff_clk <= 1'b0; + ff_cs <= 1'b0; + ff_dq_oe_s <= !quad_enable || (quad_enable && output_enable); + ff_dq_oe_q <= quad_enable && output_enable; + busy <= 1'b1; + running <= 1'b1; + valid_enable <= !output_enable; + quad_mode <= quad_enable; + counter <= quad_enable ? 3'd1 : 3'd7; + output_shift <= wdata; + end else if (finish) begin + busy <= 1'b1; + exit <= 1'b1; + counter <= wdata[2:0]; + end + end + end + end + + always_ff @(posedge clk) begin + valid <= 1'b0; + if (sample_s[2]) begin + rdata <= {rdata[6:0], ff_dq_in[1]}; + end + if (sample_q[2]) begin + rdata <= {rdata[3:0], ff_dq_in}; + end + if (valid_ff[2]) begin + valid <= 1'b1; + end + end + +endmodule + + +module memory_flash ( + input clk, + input reset, + + flash_scb.flash flash_scb, + + mem_bus.memory mem_bus, + + output flash_clk, + output flash_cs, + inout [3:0] flash_dq +); + + logic start; + logic finish; + logic busy; + logic valid; + logic output_enable; + logic quad_enable; + logic [7:0] rdata; + logic [7:0] wdata; + + flash_qspi flash_qspi_inst ( + .clk(clk), + .reset(reset), + + .start(start), + .finish(finish), + .busy(busy), + .valid(valid), + .output_enable(output_enable), + .quad_enable(quad_enable), + .rdata(rdata), + .wdata(wdata), + + .flash_clk(flash_clk), + .flash_cs(flash_cs), + .flash_dq(flash_dq) + ); + + typedef enum bit [7:0] { + FLASH_CMD_PAGE_PROGRAM = 8'h02, + FLASH_CMD_READ_STATUS_1 = 8'h05, + FLASH_CMD_WRITE_ENABLE = 8'h06, + FLASH_CMD_BLOCK_ERASE_64KB = 8'hD8, + FLASH_CMD_FAST_READ_QUAD_IO = 8'hEB + } e_flash_cmd; + + typedef enum { + FLASH_STATUS_1_BUSY = 0 + } e_flash_status_1; + + typedef enum bit [3:0] { + STATE_IDLE, + STATE_WRITE_ENABLE, + STATE_ERASE, + STATE_PROGRAM_START, + STATE_PROGRAM, + STATE_PROGRAM_END, + STATE_WAIT, + STATE_READ_START, + STATE_READ, + STATE_READ_END + } e_state; + + e_state state; + logic [2:0] counter; + logic valid_counter; + logic [23:0] current_address; + + always_ff @(posedge clk) begin + start <= 1'b0; + finish <= 1'b0; + flash_scb.erase_done <= 1'b0; + mem_bus.ack <= 1'b0; + + if (reset) begin + state <= STATE_IDLE; + end else begin + if (!busy && (start || finish)) begin + counter <= counter + 1'd1; + end + + case (state) + STATE_IDLE: begin + output_enable <= 1'b1; + quad_enable <= 1'b0; + counter <= 3'd0; + if (flash_scb.erase_pending) begin + state <= STATE_WRITE_ENABLE; + end else if (mem_bus.request) begin + current_address <= {mem_bus.address[23:1], 1'b0}; + if (mem_bus.write) begin + state <= STATE_WRITE_ENABLE; + end else begin + state <= STATE_READ_START; + end + end + end + + STATE_WRITE_ENABLE: begin + case (counter) + 3'd0: begin + start <= 1'b1; + wdata <= FLASH_CMD_WRITE_ENABLE; + end + 3'd1: begin + finish <= 1'b1; + wdata <= 8'd4; + if (!busy) begin + counter <= 3'd0; + if (flash_scb.erase_pending) begin + state <= STATE_ERASE; + end else begin + state <= STATE_PROGRAM_START; + end + end + end + endcase + end + + STATE_ERASE: begin + case (counter) + 3'd0: begin + start <= 1'b1; + wdata <= FLASH_CMD_BLOCK_ERASE_64KB; + end + 3'd1: begin + start <= 1'b1; + wdata <= flash_scb.erase_block; + end + 3'd2: begin + start <= 1'b1; + wdata <= 8'd0; + end + 3'd3: begin + start <= 1'b1; + wdata <= 8'd0; + end + 3'd4: begin + finish <= 1'b1; + wdata <= 8'd4; + if (!busy) begin + flash_scb.erase_done <= 1'b1; + counter <= 3'd0; + state <= STATE_WAIT; + end + end + endcase + end + + STATE_PROGRAM_START: begin + case (counter) + 3'd0: begin + start <= 1'b1; + wdata <= FLASH_CMD_PAGE_PROGRAM; + end + 3'd1: begin + start <= 1'b1; + wdata <= mem_bus.address[23:16]; + end + 3'd2: begin + start <= 1'b1; + wdata <= mem_bus.address[15:8]; + end + 3'd3: begin + start <= 1'b1; + wdata <= mem_bus.address[7:0]; + if (!busy) begin + counter <= 3'd0; + state <= STATE_PROGRAM; + end + end + endcase + end + + STATE_PROGRAM: begin + case (counter) + 3'd0: begin + start <= 1'b1; + wdata <= mem_bus.wdata[15:8]; + end + 3'd1: begin + start <= 1'b1; + wdata <= mem_bus.wdata[7:0]; + if (!busy) begin + mem_bus.ack <= 1'b1; + current_address <= current_address + 2'd2; + end + end + 3'd2: begin + if (current_address[7:0] == 8'h00) begin + state <= STATE_PROGRAM_END; + end else if (flash_scb.erase_pending) begin + state <= STATE_PROGRAM_END; + end else if (mem_bus.request && !mem_bus.ack) begin + if (!mem_bus.write || (mem_bus.address[23:0] != current_address)) begin + state <= STATE_PROGRAM_END; + end else begin + counter <= 3'd0; + end + end + end + endcase + end + + STATE_PROGRAM_END: begin + finish <= 1'b1; + wdata <= 8'd4; + if (!busy) begin + counter <= 3'd0; + state <= STATE_WAIT; + end + end + + STATE_WAIT: begin + case (counter) + 3'd0: begin + start <= 1'b1; + output_enable <= 1'b1; + wdata <= FLASH_CMD_READ_STATUS_1; + end + 3'd1: begin + start <= 1'b1; + output_enable <= 1'b0; + end + 3'd2: begin + finish <= 1'b1; + wdata <= 8'd0; + end + 3'd3: begin + counter <= counter; + end + endcase + if (valid) begin + if (rdata[FLASH_STATUS_1_BUSY]) begin + counter <= 3'd0; + end else begin + state <= STATE_IDLE; + end + end + end + + STATE_READ_START: begin + case (counter) + 3'd0: begin + start <= 1'b1; + wdata <= FLASH_CMD_FAST_READ_QUAD_IO; + end + 3'd1: begin + start <= 1'b1; + quad_enable <= 1'b1; + wdata <= mem_bus.address[23:16]; + end + 3'd2: begin + start <= 1'b1; + wdata <= mem_bus.address[15:8]; + end + 3'd3: begin + start <= 1'b1; + wdata <= mem_bus.address[7:0]; + end + 3'd4: begin + start <= 1'b1; + wdata <= 8'hFF; + end + 3'd5: begin + start <= 1'b1; + end + 3'd6: begin + start <= 1'b1; + if (!busy) begin + counter <= 3'd0; + valid_counter <= 1'b0; + state <= STATE_READ; + end + end + endcase + end + + STATE_READ: begin + case (counter) + 3'd0: begin + start <= 1'b1; + output_enable <= 1'b0; + end + 3'd1: begin + start <= 1'b1; + end + 3'd2: begin end + 3'd3: begin + if (flash_scb.erase_pending) begin + state <= STATE_READ_END; + end else if (mem_bus.request && !mem_bus.ack) begin + if (mem_bus.write || (mem_bus.address[23:0] != current_address)) begin + state <= STATE_READ_END; + end else begin + start <= 1'b1; + counter <= 3'd0; + end + end + end + endcase + if (valid) begin + valid_counter <= ~valid_counter; + if (valid_counter) begin + mem_bus.ack <= 1'b1; + counter <= counter + 1'd1; + current_address <= current_address + 2'd2; + end + end + end + + STATE_READ_END: begin + finish <= 1'b1; + wdata <= 8'd0; + if (!busy) begin + state <= STATE_IDLE; + end + end + + default: begin + state <= STATE_IDLE; + end + endcase + end + end + + always_ff @(posedge clk) begin + if (valid) begin + mem_bus.rdata <= {mem_bus.rdata[7:0], rdata}; + end + end + +endmodule diff --git a/fw/rtl/memory/memory_sdram.sv b/fw/rtl/memory/memory_sdram.sv index 06e3e51..fce983a 100644 --- a/fw/rtl/memory/memory_sdram.sv +++ b/fw/rtl/memory/memory_sdram.sv @@ -1,48 +1,41 @@ module memory_sdram ( - if_system sys, + input clk, + input reset, - input request, - output ack, - input write, - input [25:0] address, - output [15:0] rdata, - input [15:0] wdata, + mem_bus.memory mem_bus, - output sdram_cs, - output sdram_ras, - output sdram_cas, - output sdram_we, - output [1:0] sdram_ba, - output [12:0] sdram_a, + output logic sdram_cs, + output logic sdram_ras, + output logic sdram_cas, + output logic sdram_we, + output logic [1:0] sdram_ba, + output logic [12:0] sdram_a, + output logic [1:0] sdram_dqm, inout [15:0] sdram_dq ); - parameter [2:0] CAS_LATENCY = 3'd2; + localparam [2:0] CAS_LATENCY = 3'd2; - parameter real T_INIT = 100_000.0; - parameter real T_RC = 60.0; - parameter real T_RP = 15.0; - parameter real T_RCD = 15.0; - // parameter real T_RAS = 37.0; //TODO: handle this timing - // parameter real T_WR = T_RAS - T_RCD; //TODO: handle this timing - parameter real T_MRD = 14.0; - parameter real T_REF = 7_800.0; + localparam real T_INIT = 100_000.0; + localparam real T_RC = 60.0; + localparam real T_RP = 15.0; + localparam real T_RCD = 15.0; + localparam real T_MRD = 14.0; + localparam real T_REF = 7_800.0; - localparam real T_CLK = (1.0 / sc64::CLOCK_FREQUENCY) * 1_000_000_000.0; + localparam real T_CLK = (1.0 / 100_000_000) * 1_000_000_000.0; localparam int C_INIT = int'((T_INIT + T_CLK - 1) / T_CLK); localparam int C_RC = int'((T_RC + T_CLK - 1) / T_CLK); localparam int C_RP = int'((T_RP + T_CLK - 1) / T_CLK); localparam int C_RCD = int'((T_RCD + T_CLK - 1) / T_CLK); - // localparam int C_RAS = int'((T_RAS + T_CLK - 1) / T_CLK); - // localparam int C_WR = int'((T_WR + T_CLK - 1) / T_CLK); localparam int C_MRD = int'((T_MRD + T_CLK - 1) / T_CLK); localparam int C_REF = int'((T_REF + T_CLK - 1) / T_CLK); - localparam INIT_PRECHARGE = C_INIT; - localparam INIT_REFRESH_1 = C_INIT + C_RP; - localparam INIT_REFRESH_2 = C_INIT + C_RP + C_RC; - localparam INIT_MODE_REG = C_INIT + C_RP + (2 * C_RC); - localparam INIT_DONE = C_INIT + C_RP + (2 * C_RC) + C_MRD; + localparam INIT_PRECHARGE = 4'd0; + localparam INIT_REFRESH_1 = C_RP; + localparam INIT_REFRESH_2 = C_RP + C_RC; + localparam INIT_MODE_REG = C_RP + (2 * C_RC); + localparam INIT_DONE = C_RP + (2 * C_RC) + C_MRD; typedef enum bit [3:0] { CMD_DESL = 4'b1111, @@ -63,37 +56,51 @@ module memory_sdram ( logic [14:0] current_active_bank_row; logic request_in_current_active_bank_row; - always_ff @(posedge sys.clk) begin + always_ff @(posedge clk) begin {sdram_cs, sdram_ras, sdram_cas, sdram_we} <= 4'(sdram_next_cmd); {sdram_ba, sdram_a} <= 15'd0; + sdram_dqm <= 2'b00; sdram_dq_input <= sdram_dq; - sdram_dq_output <= wdata; + sdram_dq_output <= mem_bus.wdata; sdram_dq_output_enable <= 1'b0; case (sdram_next_cmd) CMD_READ, CMD_WRITE: begin - {sdram_ba, sdram_a} <= {address[25:24], 3'b000, address[10:1]}; - sdram_dq_output_enable <= sdram_next_cmd == CMD_WRITE; + {sdram_ba, sdram_a} <= {mem_bus.address[25:24], 3'b000, mem_bus.address[10:1]}; + sdram_dqm <= (sdram_next_cmd == CMD_WRITE) ? (~mem_bus.wmask) : 2'b00; + sdram_dq_output_enable <= (sdram_next_cmd == CMD_WRITE); end + CMD_ACT: begin - {sdram_ba, sdram_a} <= address[25:11]; - current_active_bank_row <= address[25:11]; + {sdram_ba, sdram_a} <= mem_bus.address[25:11]; + sdram_dqm <= 2'b00; + current_active_bank_row <= mem_bus.address[25:11]; + end + + CMD_PRE: begin + {sdram_ba, sdram_a} <= {2'b00, 2'b00, 1'b1, 10'd0}; + sdram_dqm <= 2'b00; + end + + CMD_MRS: begin + {sdram_ba, sdram_a} <= {2'b00, 1'b0, 1'b0, 2'b00, CAS_LATENCY, 1'b0, 3'b000}; + sdram_dqm <= 2'b00; end - CMD_PRE: {sdram_ba, sdram_a} <= {2'b00, 2'b00, 1'b1, 10'd0}; - CMD_MRS: {sdram_ba, sdram_a} <= {2'b00, 1'b0, 1'b0, 2'b00, CAS_LATENCY, 1'b0, 3'b000}; endcase end + assign sdram_dq = sdram_dq_output_enable ? sdram_dq_output : 16'hZZZZ; + always_comb begin - rdata = sdram_dq_input; - sdram_dq = sdram_dq_output_enable ? sdram_dq_output : 16'hZZZZ; - request_in_current_active_bank_row = address[25:11] == current_active_bank_row; + mem_bus.rdata = sdram_dq_input; + request_in_current_active_bank_row = mem_bus.address[25:11] == current_active_bank_row; end typedef enum bit [2:0] { + S_POWERUP, S_INIT, S_IDLE, S_ACTIVATING, @@ -106,44 +113,54 @@ module memory_sdram ( e_state state; e_state next_state; - always_ff @(posedge sys.clk) begin - if (sys.reset) begin - state <= S_INIT; + always_ff @(posedge clk) begin + if (reset) begin + state <= S_POWERUP; end else begin state <= next_state; end end - logic [13:0] wait_counter; + logic [13:0] powerup_coutner; + logic powerup_done; + logic [4:0] wait_counter; logic [9:0] refresh_counter; logic pending_refresh; - always_ff @(posedge sys.clk) begin - if (sys.reset || state != next_state) begin - wait_counter <= 14'd0; + always_ff @(posedge clk) begin + if (reset) begin + powerup_coutner <= 14'd0; + powerup_done <= 1'b0; + end else if (powerup_coutner < C_INIT) begin + powerup_coutner <= powerup_coutner + 1'd1; + end else begin + powerup_done <= 1'b1; + end + + if (reset || state != next_state) begin + wait_counter <= 5'd0; end else begin wait_counter <= wait_counter + 1'd1; end if (sdram_next_cmd == CMD_REF) begin refresh_counter <= 10'd0; - end else if (refresh_counter < 10'h3FF) begin + pending_refresh <= 1'b0; + end else if (refresh_counter < C_REF) begin refresh_counter <= refresh_counter + 1'd1; + end else begin + pending_refresh <= 1'b1; end end - always_comb begin - pending_refresh = refresh_counter >= C_REF; - end - logic [(CAS_LATENCY):0] read_cmd_ack_delay; - always_ff @(posedge sys.clk) begin - ack <= 1'b0; + always_ff @(posedge clk) begin + mem_bus.ack <= 1'b0; read_cmd_ack_delay <= {sdram_next_cmd == CMD_READ, read_cmd_ack_delay[(CAS_LATENCY):1]}; if (sdram_next_cmd == CMD_WRITE || read_cmd_ack_delay[0]) begin - ack <= 1'b1; + mem_bus.ack <= 1'b1; end end @@ -152,10 +169,14 @@ module memory_sdram ( next_state = state; case (state) - S_INIT: begin - if (wait_counter < INIT_PRECHARGE) begin - sdram_next_cmd = CMD_DESL; + S_POWERUP: begin + sdram_next_cmd = CMD_DESL; + if (powerup_done) begin + next_state = S_INIT; end + end + + S_INIT: begin if (wait_counter == INIT_PRECHARGE) begin sdram_next_cmd = CMD_PRE; end @@ -174,7 +195,7 @@ module memory_sdram ( if (pending_refresh) begin next_state = S_REFRESH; sdram_next_cmd = CMD_REF; - end else if (request) begin + end else if (mem_bus.request) begin next_state = S_ACTIVATING; sdram_next_cmd = CMD_ACT; end @@ -190,10 +211,10 @@ module memory_sdram ( if (pending_refresh) begin next_state = S_PRECHARGE; sdram_next_cmd = CMD_PRE; - end else if (request) begin + end else if (mem_bus.request) begin if (request_in_current_active_bank_row) begin next_state = S_BUSY; - sdram_next_cmd = write ? CMD_WRITE : CMD_READ; + sdram_next_cmd = mem_bus.write ? CMD_WRITE : CMD_READ; end else begin next_state = S_PRECHARGE; sdram_next_cmd = CMD_PRE; @@ -202,7 +223,7 @@ module memory_sdram ( end S_BUSY: begin - if (ack) begin + if (mem_bus.ack) begin next_state = S_ACTIVE; end end diff --git a/fw/rtl/n64/n64_bootloader.sv b/fw/rtl/n64/n64_bootloader.sv deleted file mode 100644 index 0f5942e..0000000 --- a/fw/rtl/n64/n64_bootloader.sv +++ /dev/null @@ -1,124 +0,0 @@ -module n64_bootloader ( - if_system.sys sys, - if_n64_bus bus, - if_flash.memory flash -); - - logic mem_request; - logic csr_ack; - logic data_ack; - logic write_ack; - logic data_busy; - logic mem_write; - logic [31:0] mem_address; - logic [31:0] csr_rdata; - logic [31:0] data_rdata; - logic [31:0] mem_wdata; - - typedef enum bit [0:0] { - S_IDLE, - S_WAIT - } e_state; - - typedef enum bit [0:0] { - T_N64, - T_CPU - } e_source_request; - - e_state state; - e_source_request source_request; - - always_ff @(posedge sys.clk) begin - csr_ack <= 1'b0; - write_ack <= 1'b0; - - if (sys.reset) begin - state <= S_IDLE; - mem_request <= 1'b0; - end else begin - case (state) - S_IDLE: begin - if (bus.request || flash.request) begin - state <= S_WAIT; - mem_request <= 1'b1; - if (bus.request) begin - mem_write <= 1'b0; - mem_address <= bus.address; - mem_wdata <= bus.wdata; - source_request <= T_N64; - end else if (flash.request) begin - mem_write <= flash.write; - mem_address <= flash.address; - mem_wdata <= flash.wdata; - source_request <= T_CPU; - end - end - end - - S_WAIT: begin - if (mem_address[27] && source_request != T_N64 && !csr_ack) begin - mem_request <= 1'b0; - csr_ack <= 1'b1; - end - if ((!mem_address[27] || source_request == T_N64) && !data_busy) begin - mem_request <= 1'b0; - end - if (!mem_address[27] && mem_write && !data_busy && !write_ack) begin - write_ack <= 1'b1; - end - if (csr_ack || data_ack || write_ack) begin - state <= S_IDLE; - end - end - endcase - end - end - - logic csr_or_data; - logic csr_read; - logic csr_write; - logic data_read; - logic data_write; - - always_comb begin - csr_or_data = mem_address[27] && source_request == T_CPU; - csr_read = csr_or_data && mem_request && !mem_write; - csr_write = csr_or_data && mem_request && mem_write; - data_read = !csr_or_data && mem_request && !mem_write; - data_write = !csr_or_data && mem_request && mem_write; - - bus.ack = source_request == T_N64 && data_ack; - bus.rdata = 16'd0; - if (bus.ack && bus.address >= 32'h10000000 && bus.address < 32'h10016800) begin - if (bus.address[1]) bus.rdata = {data_rdata[23:16], data_rdata[31:24]}; - else bus.rdata = {data_rdata[7:0], data_rdata[15:8]}; - end - - flash.ack = source_request == T_CPU && (csr_ack || data_ack || write_ack); - flash.rdata = 32'd0; - if (flash.ack) begin - flash.rdata = csr_or_data ? csr_rdata : data_rdata; - end - end - - intel_flash intel_flash_inst ( - .clock(sys.clk), - .reset_n(~sys.reset), - - .avmm_csr_addr(mem_address[2]), - .avmm_csr_read(csr_read), - .avmm_csr_writedata(mem_wdata), - .avmm_csr_write(csr_write), - .avmm_csr_readdata(csr_rdata), - - .avmm_data_addr(mem_address[31:2]), - .avmm_data_read(data_read), - .avmm_data_writedata(mem_wdata), - .avmm_data_write(data_write), - .avmm_data_readdata(data_rdata), - .avmm_data_waitrequest(data_busy), - .avmm_data_readdatavalid(data_ack), - .avmm_data_burstcount(2'd1) - ); - -endmodule diff --git a/fw/rtl/n64/n64_bus.sv b/fw/rtl/n64/n64_bus.sv deleted file mode 100644 index e3c90aa..0000000 --- a/fw/rtl/n64/n64_bus.sv +++ /dev/null @@ -1,67 +0,0 @@ -interface if_n64_bus (); - - localparam sc64::e_n64_id NUM_DEVICES = sc64::__ID_N64_END; - - sc64::e_n64_id id; - logic request; - logic ack; - logic write; - logic [31:0] address; - logic [15:0] wdata; - logic [15:0] rdata; - logic [31:0] real_address; - logic read_op; - logic write_op; - - logic device_ack [(NUM_DEVICES - 1):0]; - logic [15:0] device_rdata [(NUM_DEVICES - 1):0]; - - always_comb begin - ack = 1'b0; - rdata = 16'd0; - - for (integer i = 0; i < NUM_DEVICES; i++) begin - ack = ack | device_ack[i]; - rdata = rdata | device_rdata[i]; - end - end - - modport n64 ( - output id, - output request, - input ack, - output write, - output address, - output wdata, - input rdata, - - output real_address, - output read_op, - output write_op - ); - - genvar n; - generate - for (n = 0; n < NUM_DEVICES; n++) begin : at - logic device_request; - - always_comb begin - device_request = request && id == sc64::e_n64_id'(n); - end - - modport device ( - input .request(device_request), - output .ack(device_ack[n]), - input .write(write), - input .address(address), - input .wdata(wdata), - output .rdata(device_rdata[n]), - - input .real_address(real_address), - input .read_op(read_op), - input .write_op(write_op) - ); - end - endgenerate - -endinterface diff --git a/fw/rtl/n64/n64_cfg.sv b/fw/rtl/n64/n64_cfg.sv index 486d343..e5b4212 100644 --- a/fw/rtl/n64/n64_cfg.sv +++ b/fw/rtl/n64/n64_cfg.sv @@ -1,83 +1,137 @@ module n64_cfg ( - if_system sys, - if_n64_bus bus, - if_config.n64 cfg + input clk, + input reset, + + n64_reg_bus.cfg reg_bus, + + n64_scb.cfg n64_scb, + + output logic irq ); typedef enum bit [3:0] { - R_SR, - R_COMMAND, - R_DATA_0_H, - R_DATA_0_L, - R_DATA_1_H, - R_DATA_1_L, - R_VERSION_H, - R_VERSION_L - } e_reg_id; + REG_STATUS, + REG_COMMAND, + REG_DATA_0_H, + REG_DATA_0_L, + REG_DATA_1_H, + REG_DATA_1_L, + REG_VERSION_H, + REG_VERSION_L, + REG_KEY_H, + REG_KEY_L + } e_reg; - typedef enum bit [0:0] { - S_IDLE, - S_WAIT - } e_state; - - e_state state; + logic cfg_error; always_comb begin - bus.rdata = 16'd0; - if (bus.ack) begin - case (bus.address[3:1]) - R_SR: bus.rdata = { - cfg.cpu_ready, - cfg.cpu_busy, - 1'b0, - cfg.cmd_error, - 12'd0 + reg_bus.rdata = 16'd0; + if (reg_bus.address[16] && (reg_bus.address[15:5] == 11'd0)) begin + case (reg_bus.address[4:1]) + REG_STATUS: reg_bus.rdata = { + n64_scb.cfg_pending, + cfg_error, + irq, + 13'd0 }; - R_COMMAND: bus.rdata = {8'd0, cfg.cmd}; - R_DATA_0_H: bus.rdata = cfg.data[0][31:16]; - R_DATA_0_L: bus.rdata = cfg.data[0][15:0]; - R_DATA_1_H: bus.rdata = cfg.data[1][31:16]; - R_DATA_1_L: bus.rdata = cfg.data[1][15:0]; - R_VERSION_H: bus.rdata = sc64::SC64_VER[31:16]; - R_VERSION_L: bus.rdata = sc64::SC64_VER[15:0]; + REG_COMMAND: reg_bus.rdata = {8'd0, n64_scb.cfg_cmd}; + REG_DATA_0_H: reg_bus.rdata = n64_scb.cfg_wdata[0][31:16]; + REG_DATA_0_L: reg_bus.rdata = n64_scb.cfg_wdata[0][15:0]; + REG_DATA_1_H: reg_bus.rdata = n64_scb.cfg_wdata[1][31:16]; + REG_DATA_1_L: reg_bus.rdata = n64_scb.cfg_wdata[1][15:0]; + REG_VERSION_H: reg_bus.rdata = n64_scb.cfg_version[31:16]; + REG_VERSION_L: reg_bus.rdata = n64_scb.cfg_version[15:0]; + REG_KEY_H: reg_bus.rdata = 16'd0; + REG_KEY_L: reg_bus.rdata = 16'd0; endcase end end - always_ff @(posedge sys.clk) begin - bus.ack <= 1'b0; - cfg.cmd_request <= 1'b0; + logic unlock_flag; + logic lock_sequence_counter; - if (cfg.data_write[0]) cfg.data[0] <= cfg.wdata; - if (cfg.data_write[1]) cfg.data[1] <= cfg.wdata; + always_ff @(posedge clk) begin + if (n64_scb.cfg_done) begin + n64_scb.cfg_pending <= 1'b0; + cfg_error <= n64_scb.cfg_error; + end - if (sys.reset) begin - state <= S_IDLE; - end else begin - case (state) - S_IDLE: begin - if (bus.request) begin - state <= S_WAIT; - bus.ack <= 1'b1; - if (bus.write) begin - case (bus.address[3:1]) - R_COMMAND: begin - cfg.cmd <= bus.wdata[7:0]; - cfg.cmd_request <= 1'b1; - end - R_DATA_0_H: cfg.data[0][31:16] <= bus.wdata; - R_DATA_0_L: cfg.data[0][15:0] <= bus.wdata; - R_DATA_1_H: cfg.data[1][31:16] <= bus.wdata; - R_DATA_1_L: cfg.data[1][15:0] <= bus.wdata; - endcase + if (n64_scb.cfg_irq) begin + irq <= 1'b1; + end + + if (unlock_flag) begin + n64_scb.cfg_unlock <= 1'b1; + end + + if (reset || n64_scb.n64_reset || n64_scb.n64_nmi) begin + n64_scb.cfg_unlock <= 1'b0; + n64_scb.cfg_pending <= 1'b0; + n64_scb.cfg_cmd <= 8'h00; + irq <= 1'b0; + cfg_error <= 1'b0; + lock_sequence_counter <= 1'd0; + end else if (n64_scb.cfg_unlock) begin + if (reg_bus.write && reg_bus.address[16] && (reg_bus.address[15:5] == 11'd0)) begin + case (reg_bus.address[4:1]) + REG_COMMAND: begin + n64_scb.cfg_pending <= 1'b1; + n64_scb.cfg_cmd <= reg_bus.wdata[7:0]; + cfg_error <= 1'b0; + end + REG_DATA_0_H: n64_scb.cfg_rdata[0][31:16] <= reg_bus.wdata; + REG_DATA_0_L: n64_scb.cfg_rdata[0][15:0] <= reg_bus.wdata; + REG_DATA_1_H: n64_scb.cfg_rdata[1][31:16] <= reg_bus.wdata; + REG_DATA_1_L: n64_scb.cfg_rdata[1][15:0] <= reg_bus.wdata; + REG_VERSION_H: irq <= 1'b0; + REG_KEY_H, REG_KEY_L: begin + lock_sequence_counter <= lock_sequence_counter + 1'd1; + if (reg_bus.wdata != 16'hFFFF) begin + lock_sequence_counter <= 1'd0; + end + if (lock_sequence_counter == 1'd1) begin + n64_scb.cfg_unlock <= (reg_bus.wdata != 16'hFFFF); end end - end + endcase + end + end + end - S_WAIT: begin - state <= S_IDLE; - end - endcase + const bit [15:0] UNLOCK_SEQUENCE [4] = { + 16'h5F55, + 16'h4E4C, + 16'h4F43, + 16'h4B5F + }; + + logic [1:0] unlock_sequence_counter; + + always_ff @(posedge clk) begin + unlock_flag <= 1'b0; + + if (reset || n64_scb.n64_reset || n64_scb.n64_nmi) begin + unlock_sequence_counter <= 2'd0; + end else if (!n64_scb.cfg_unlock) begin + if (reg_bus.write && reg_bus.address[16] && (reg_bus.address[15:5] == 11'd0)) begin + case (reg_bus.address[4:1]) + REG_KEY_H, REG_KEY_L: begin + for (int index = 0; index < $size(UNLOCK_SEQUENCE); index++) begin + if (index == unlock_sequence_counter) begin + if (reg_bus.wdata == UNLOCK_SEQUENCE[index]) begin + unlock_sequence_counter <= unlock_sequence_counter + 1'd1; + if (index == ($size(UNLOCK_SEQUENCE) - 1'd1)) begin + unlock_flag <= 1'b1; + unlock_sequence_counter <= 2'd0; + end + end else begin + unlock_sequence_counter <= 2'd0; + end + end + end + end + endcase + end end end diff --git a/fw/rtl/n64/n64_dd.sv b/fw/rtl/n64/n64_dd.sv index 2c36d48..4716c2e 100644 --- a/fw/rtl/n64/n64_dd.sv +++ b/fw/rtl/n64/n64_dd.sv @@ -1,21 +1,4 @@ -interface if_dd ( - output dd_interrupt -); - - // Sector buffer regs - - logic [6:0] n64_sector_address; - logic n64_sector_address_valid; - logic n64_sector_write; - logic [15:0] n64_sector_wdata; - - logic [5:0] cpu_sector_address; - logic cpu_sector_address_valid; - logic cpu_sector_write; - logic [31:0] cpu_sector_wdata; - - logic [31:0] sector_rdata; - +interface dd_scb (); // N64 controlled regs @@ -55,11 +38,38 @@ interface if_dd ( logic [12:0] head_track; logic [15:0] drive_id; + modport controller ( + input hard_reset, + input data, + input cmd, + input cmd_pending, + input bm_start_pending, + input bm_stop_pending, + input bm_transfer_mode, + input bm_transfer_blocks, + input bm_pending, + input bm_interrupt_ack, + input sector_num, + input sector_size, + input sector_size_full, + input sectors_in_block, - always_comb begin - dd_interrupt = cmd_interrupt || bm_interrupt; - end - + output hard_reset_clear, + output cmd_data, + output cmd_ready, + output bm_start_clear, + output bm_stop_clear, + output bm_transfer_c2, + output bm_transfer_data, + output bm_micro_error, + output bm_ready, + output bm_clear, + output disk_inserted, + output disk_changed, + output index_lock, + output head_track, + output drive_id + ); modport dd ( output hard_reset, @@ -93,90 +103,36 @@ interface if_dd ( input disk_changed, input index_lock, input head_track, - input drive_id, - - output .sector_address(n64_sector_address), - output .sector_address_valid(n64_sector_address_valid), - output .sector_write(n64_sector_write), - output .sector_wdata(n64_sector_wdata), - input sector_rdata - ); - - modport cpu ( - input hard_reset, - input data, - input cmd, - input cmd_pending, - input bm_start_pending, - input bm_stop_pending, - input bm_transfer_mode, - input bm_transfer_blocks, - input bm_pending, - input bm_interrupt_ack, - input sector_num, - input sector_size, - input sector_size_full, - input sectors_in_block, - - output hard_reset_clear, - output cmd_data, - output cmd_ready, - output bm_start_clear, - output bm_stop_clear, - output bm_transfer_c2, - output bm_transfer_data, - output bm_micro_error, - output bm_ready, - output bm_clear, - output disk_inserted, - output disk_changed, - output index_lock, - output head_track, - output drive_id, - - output .sector_address(cpu_sector_address), - output .sector_address_valid(cpu_sector_address_valid), - output .sector_write(cpu_sector_write), - output .sector_wdata(cpu_sector_wdata), - input sector_rdata - ); - - modport sector_buffer ( - input n64_sector_address, - input n64_sector_address_valid, - input n64_sector_write, - input n64_sector_wdata, - - input cpu_sector_address, - input cpu_sector_address_valid, - input cpu_sector_write, - input cpu_sector_wdata, - - output sector_rdata + input drive_id ); endinterface module n64_dd ( - if_system.sys sys, - if_n64_bus bus, - if_dd.dd dd + input clk, + input reset, + + n64_reg_bus.dd reg_bus, + + n64_scb.dd n64_scb, + dd_scb.dd dd_scb, + + output logic irq ); - const bit [31:0] M_BASE = 32'h0500_0000; - const bit [31:0] M_C2_BUFFER = M_BASE + 11'h000; - const bit [31:0] M_SECTOR_BUFFER = M_BASE + 11'h400; + const bit [10:0] MEM_C2_BUFFER = 11'h000; + const bit [10:0] MEM_SECTOR_BUFFER = 11'h400; typedef enum bit [10:0] { - R_DATA = 11'h500, - R_CMD_SR = 11'h508, - R_TRK_CUR = 11'h50C, - R_BM_SCR = 11'h510, - R_RESET = 11'h520, - R_SEC_SIZ = 11'h528, - R_SEC_INFO = 11'h530, - R_ID = 11'h540 + REG_DATA = 11'h500, + REG_CMD_SR = 11'h508, + REG_TRK_CUR = 11'h50C, + REG_BM_SCR = 11'h510, + REG_RESET = 11'h520, + REG_SEC_SIZ = 11'h528, + REG_SEC_INFO = 11'h530, + REG_ID = 11'h540 } e_reg_id; typedef enum bit [3:0] { @@ -187,218 +143,144 @@ module n64_dd ( BM_CONTROL_MECHANIC_INTERRUPT_RESET = 4'd8 } e_bm_control_id; - typedef enum bit [0:0] { - S_IDLE, - S_WAIT - } e_state; - - e_state state; - always_comb begin - dd.sector_address = bus.address[7:1]; - dd.sector_address_valid = bus.request && bus.address[11:8] == M_SECTOR_BUFFER[11:8]; - dd.sector_write = bus.write && dd.sector_address_valid; - dd.sector_wdata = bus.wdata; - end - - always_comb begin - bus.rdata = 16'd0; - if (bus.ack) begin - if (bus.address[10:8] == M_SECTOR_BUFFER[10:8]) begin - if (bus.address[1]) begin - bus.rdata = dd.sector_rdata[15:0]; - end else begin - bus.rdata = dd.sector_rdata[31:16]; - end - end else begin - case (bus.address[10:0]) - R_DATA: bus.rdata = dd.data; - R_CMD_SR: bus.rdata = { - 1'b0, - dd.bm_transfer_data, - 1'b0, - dd.bm_transfer_c2, - 1'b0, - dd.bm_interrupt, - dd.cmd_interrupt, - dd.disk_inserted, - dd.cmd_pending, - dd.hard_reset, - 1'b0, - 1'b0, - 1'b0, - 1'b0, - 1'b0, - dd.disk_changed - }; - R_TRK_CUR: bus.rdata = {1'd0, {2{dd.index_lock}}, dd.head_track}; - R_BM_SCR: bus.rdata = {6'd0, dd.bm_micro_error, 9'd0}; - R_ID: bus.rdata = {dd.drive_id}; - default: bus.rdata = 16'd0; - endcase - end - end - end - - always_ff @(posedge sys.clk) begin - bus.ack <= 1'b0; - dd.bm_interrupt_ack <= 1'b0; - - if (dd.hard_reset_clear) begin - dd.hard_reset <= 1'b0; - end - if (dd.cmd_ready) begin - dd.data <= dd.cmd_data; - dd.cmd_pending <= 1'b0; - dd.cmd_interrupt <= 1'b1; - end - if (dd.bm_start_clear) begin - dd.bm_start_pending <= 1'b0; - end - if (dd.bm_stop_clear) begin - dd.bm_stop_pending <= 1'b0; - end - if (dd.bm_clear) begin - dd.bm_pending <= 1'b0; - end - if (dd.bm_ready) begin - dd.bm_interrupt <= 1'b1; - end - if (bus.real_address == (M_C2_BUFFER + ({dd.sector_size[7:1], 1'b0} * 3'd4)) && bus.read_op) begin - dd.bm_pending <= 1'b1; - end - if (bus.real_address == (M_SECTOR_BUFFER + {dd.sector_size[7:1], 1'b0}) && (bus.read_op || bus.write_op)) begin - dd.bm_pending <= 1'b1; - end - if (bus.real_address == (M_BASE + R_CMD_SR) && bus.read_op) begin - dd.bm_interrupt <= 1'b0; - dd.bm_interrupt_ack <= 1'b1; - end - - if (sys.reset || sys.n64_hard_reset) begin - dd.hard_reset <= 1'b1; - dd.cmd_pending <= 1'b0; - dd.cmd_interrupt <= 1'b0; - dd.bm_start_pending <= 1'b0; - dd.bm_stop_pending <= 1'b0; - dd.bm_pending <= 1'b0; - dd.bm_interrupt <= 1'b0; - state <= S_IDLE; + reg_bus.rdata = 16'd0; + if (reg_bus.address[10:8] == MEM_SECTOR_BUFFER[10:8]) begin + reg_bus.rdata = n64_scb.dd_rdata; end else begin - case (state) - S_IDLE: begin - if (bus.request) begin - state <= S_WAIT; - bus.ack <= 1'b1; - if (bus.write) begin - case (bus.address[10:0]) - R_DATA: begin - dd.data <= bus.wdata; - end + case (reg_bus.address[10:0]) + REG_DATA: reg_bus.rdata = dd_scb.data; + REG_CMD_SR: reg_bus.rdata = { + 1'b0, + dd_scb.bm_transfer_data, + 1'b0, + dd_scb.bm_transfer_c2, + 1'b0, + dd_scb.bm_interrupt, + dd_scb.cmd_interrupt, + dd_scb.disk_inserted, + dd_scb.cmd_pending, + dd_scb.hard_reset, + 1'b0, + 1'b0, + 1'b0, + 1'b0, + 1'b0, + dd_scb.disk_changed + }; + REG_TRK_CUR: reg_bus.rdata = {1'd0, {2{dd_scb.index_lock}}, dd_scb.head_track}; + REG_BM_SCR: reg_bus.rdata = {6'd0, dd_scb.bm_micro_error, 9'd0}; + REG_ID: reg_bus.rdata = dd_scb.drive_id; + endcase + end + end - R_CMD_SR: begin - dd.cmd <= bus.wdata[7:0]; - dd.cmd_pending <= 1'b1; - end + always_ff @(posedge clk) begin + dd_scb.bm_interrupt_ack <= 1'b0; - R_BM_SCR: begin - dd.sector_num <= bus.wdata[7:0]; - if (bus.wdata[BM_CONTROL_START_BUFFER_MANAGER]) begin - dd.bm_start_pending <= 1'b1; - dd.bm_stop_pending <= 1'b0; - dd.bm_transfer_mode <= bus.wdata[BM_CONTROL_BUFFER_MANAGER_MODE]; - dd.bm_transfer_blocks <= bus.wdata[BM_CONTROL_BLOCK_TRANSFER]; - end - if (bus.wdata[BM_CONTROL_BUFFER_MANAGER_RESET]) begin - dd.bm_start_pending <= 1'b0; - dd.bm_stop_pending <= 1'b1; - dd.bm_transfer_mode <= 1'b0; - dd.bm_transfer_blocks <= 1'b0; - dd.bm_pending <= 1'b0; - dd.bm_interrupt <= 1'b0; - end - if (bus.wdata[BM_CONTROL_MECHANIC_INTERRUPT_RESET]) begin - dd.cmd_interrupt <= 1'b0; - end - end + if (dd_scb.hard_reset_clear) begin + dd_scb.hard_reset <= 1'b0; + end + if (dd_scb.cmd_ready) begin + dd_scb.data <= dd_scb.cmd_data; + dd_scb.cmd_pending <= 1'b0; + dd_scb.cmd_interrupt <= 1'b1; + end + if (dd_scb.bm_start_clear) begin + dd_scb.bm_start_pending <= 1'b0; + end + if (dd_scb.bm_stop_clear) begin + dd_scb.bm_stop_pending <= 1'b0; + end + if (dd_scb.bm_clear) begin + dd_scb.bm_pending <= 1'b0; + end + if (dd_scb.bm_ready) begin + dd_scb.bm_interrupt <= 1'b1; + end + if (reg_bus.address[10:0] == (MEM_C2_BUFFER + ({dd_scb.sector_size[7:1], 1'b0} * 3'd4)) && reg_bus.read) begin + dd_scb.bm_pending <= 1'b1; + end + if (reg_bus.address[10:0] == (MEM_SECTOR_BUFFER + {dd_scb.sector_size[7:1], 1'b0}) && (reg_bus.read || reg_bus.write)) begin + dd_scb.bm_pending <= 1'b1; + end + if (reg_bus.address[10:0] == REG_CMD_SR && reg_bus.read) begin + dd_scb.bm_interrupt <= 1'b0; + dd_scb.bm_interrupt_ack <= 1'b1; + end - R_RESET: begin - if (bus.wdata == 16'hAAAA) begin - dd.hard_reset <= 1'b1; - dd.cmd_pending <= 1'b0; - dd.cmd_interrupt <= 1'b0; - dd.bm_start_pending <= 1'b0; - dd.bm_stop_pending <= 1'b0; - dd.bm_pending <= 1'b0; - dd.bm_interrupt <= 1'b0; - end - end + if (reset || n64_scb.n64_reset) begin + dd_scb.hard_reset <= 1'b1; + dd_scb.cmd_pending <= 1'b0; + dd_scb.cmd_interrupt <= 1'b0; + dd_scb.bm_start_pending <= 1'b0; + dd_scb.bm_stop_pending <= 1'b0; + dd_scb.bm_pending <= 1'b0; + dd_scb.bm_interrupt <= 1'b0; + end else if (reg_bus.write) begin + case (reg_bus.address[10:0]) + REG_DATA: begin + dd_scb.data <= reg_bus.wdata; + end - R_SEC_SIZ: begin - dd.sector_size <= bus.wdata[7:0]; - end + REG_CMD_SR: begin + dd_scb.cmd <= reg_bus.wdata[7:0]; + dd_scb.cmd_pending <= 1'b1; + end - R_SEC_INFO: begin - dd.sectors_in_block <= bus.wdata[15:8]; - dd.sector_size_full <= bus.wdata[7:0]; - end - endcase - end + REG_BM_SCR: begin + dd_scb.sector_num <= reg_bus.wdata[7:0]; + if (reg_bus.wdata[BM_CONTROL_START_BUFFER_MANAGER]) begin + dd_scb.bm_start_pending <= 1'b1; + dd_scb.bm_stop_pending <= 1'b0; + dd_scb.bm_transfer_mode <= reg_bus.wdata[BM_CONTROL_BUFFER_MANAGER_MODE]; + dd_scb.bm_transfer_blocks <= reg_bus.wdata[BM_CONTROL_BLOCK_TRANSFER]; + end + if (reg_bus.wdata[BM_CONTROL_BUFFER_MANAGER_RESET]) begin + dd_scb.bm_start_pending <= 1'b0; + dd_scb.bm_stop_pending <= 1'b1; + dd_scb.bm_transfer_mode <= 1'b0; + dd_scb.bm_transfer_blocks <= 1'b0; + dd_scb.bm_pending <= 1'b0; + dd_scb.bm_interrupt <= 1'b0; + end + if (reg_bus.wdata[BM_CONTROL_MECHANIC_INTERRUPT_RESET]) begin + dd_scb.cmd_interrupt <= 1'b0; end end - S_WAIT: begin - state <= S_IDLE; + REG_RESET: begin + if (reg_bus.wdata == 16'hAAAA) begin + dd_scb.hard_reset <= 1'b1; + dd_scb.cmd_pending <= 1'b0; + dd_scb.cmd_interrupt <= 1'b0; + dd_scb.bm_start_pending <= 1'b0; + dd_scb.bm_stop_pending <= 1'b0; + dd_scb.bm_pending <= 1'b0; + dd_scb.bm_interrupt <= 1'b0; + end + end + + REG_SEC_SIZ: begin + dd_scb.sector_size <= reg_bus.wdata[7:0]; + end + + REG_SEC_INFO: begin + dd_scb.sectors_in_block <= reg_bus.wdata[15:8]; + dd_scb.sector_size_full <= reg_bus.wdata[7:0]; end endcase end end -endmodule - - -module n64_dd_sector_buffer ( - if_system.sys sys, - if_dd.sector_buffer dd -); - - logic [5:0] sector_address; - logic [31:0] sector_buffer [0:63]; - logic [15:0] sector_high_buffer; - logic sector_write; - logic [31:0] sector_wdata; + always_comb begin + irq = dd_scb.cmd_interrupt || dd_scb.bm_interrupt; + end always_comb begin - sector_address = 6'd0; - sector_write = 1'b0; - sector_wdata = 32'd0; - - if (dd.n64_sector_address_valid) begin - sector_address = dd.n64_sector_address[6:1]; - end else if (dd.cpu_sector_address_valid) begin - sector_address = dd.cpu_sector_address; - end - - if (dd.n64_sector_write && dd.n64_sector_address[0]) begin - sector_write = 1'b1; - sector_wdata = {sector_high_buffer, dd.n64_sector_wdata}; - end else if (dd.cpu_sector_write) begin - sector_write = 1'b1; - sector_wdata = dd.cpu_sector_wdata; - end - end - - always_ff @(posedge sys.clk) begin - if (dd.n64_sector_write && !dd.n64_sector_address[0]) begin - sector_high_buffer <= dd.n64_sector_wdata; - end - end - - always_ff @(posedge sys.clk) begin - dd.sector_rdata <= sector_buffer[sector_address]; - if (sector_write) begin - sector_buffer[sector_address] <= sector_wdata; - end + n64_scb.dd_write = reg_bus.write && reg_bus.address[10:8] == MEM_SECTOR_BUFFER[10:8]; + n64_scb.dd_address = reg_bus.address[7:1]; + n64_scb.dd_wdata = reg_bus.wdata; end endmodule diff --git a/fw/rtl/n64/n64_flashram.sv b/fw/rtl/n64/n64_flashram.sv index 8ca686f..bbc9464 100644 --- a/fw/rtl/n64/n64_flashram.sv +++ b/fw/rtl/n64/n64_flashram.sv @@ -1,189 +1,152 @@ module n64_flashram ( - if_system.sys sys, - if_n64_bus bus, - if_config.flashram cfg, - if_flashram.flashram flashram + input clk, + input reset, + + n64_reg_bus.flashram reg_bus, + + n64_scb.flashram n64_scb ); localparam [31:0] FLASH_TYPE_ID = 32'h1111_8001; localparam [31:0] FLASH_MODEL_ID = 32'h00C2_001D; typedef enum bit [7:0] { - CMD_STATUS_MODE = 8'hD2, - CMD_READID_MODE = 8'hE1, - CMD_READ_MODE = 8'hF0, - CMD_ERASE_SECTOR = 8'h4B, - CMD_ERASE_CHIP = 8'h3C, - CMD_BUFFER_MODE = 8'hB4, - CMD_ERASE_START = 8'h78, - CMD_WRITE_START = 8'hA5 + CMD_STATUS_MODE = 8'hD2, + CMD_READID_MODE = 8'hE1, + CMD_READ_MODE = 8'hF0, + CMD_ERASE_SECTOR = 8'h4B, + CMD_ERASE_CHIP = 8'h3C, + CMD_BUFFER_MODE = 8'hB4, + CMD_ERASE_START = 8'h78, + CMD_WRITE_START = 8'hA5 } e_cmd; - typedef enum bit [0:0] { - S_IDLE, - S_WAIT - } e_bus_state; + typedef enum bit [1:0] { + STATE_STATUS, + STATE_ID, + STATE_READ, + STATE_BUFFER + } e_state; typedef enum bit [1:0] { - FS_STATUS, - FS_ID, - FS_READ, - FS_BUFFER - } e_flashram_state; + WRITE_BUSY, + ERASE_BUSY, + WRITE_DONE, + ERASE_DONE + } e_status_bits; - typedef enum bit [1:0] { - B_WRITE_BUSY, - B_ERASE_BUSY, - B_WRITE_DONE, - B_ERASE_DONE - } e_flashram_status; - - e_bus_state bus_state; - e_flashram_state flashram_state; - logic [3:0] flashram_status; - logic [7:0] flashram_command; - logic flashram_erase_enabled; - - logic [31:0] write_buffer [0:31]; - logic [1:0] write_buffer_wmask; - logic [15:0] high_buffer; + e_state state; + logic [3:0] status; + logic [7:0] cmd; + logic erase_enabled; always_comb begin - write_buffer_wmask = 2'b00; - if (bus.request && bus.write && !bus.address[16] && flashram_state == FS_BUFFER) begin - write_buffer_wmask[0] = !bus.address[1]; - write_buffer_wmask[1] = bus.address[1]; + n64_scb.flashram_read_mode = (state == STATE_READ); + + reg_bus.rdata = 16'd0; + if (state == STATE_ID) begin + case (reg_bus.address[2:1]) + 0: reg_bus.rdata = FLASH_TYPE_ID[31:16]; + 1: reg_bus.rdata = FLASH_TYPE_ID[15:0]; + 2: reg_bus.rdata = FLASH_MODEL_ID[31:16]; + 3: reg_bus.rdata = FLASH_MODEL_ID[15:0]; + endcase + end else if (reg_bus.address[1]) begin + reg_bus.rdata = {12'd0, status}; end end - always_ff @(posedge sys.clk) begin - if (write_buffer_wmask[0]) high_buffer <= bus.wdata; - end - - always_ff @(posedge sys.clk) begin - flashram.rdata <= write_buffer[flashram.address]; - if (write_buffer_wmask[1]) write_buffer[bus.address[6:2]] <= {high_buffer, bus.wdata}; - end - - always_comb begin - bus.rdata = 16'd0; - if (bus.ack) begin - if (bus.address[1]) begin - bus.rdata = {12'd0, flashram_status}; - end - if (flashram_state == FS_ID) begin - case (bus.address[2:1]) - 0: bus.rdata = FLASH_TYPE_ID[31:16]; - 1: bus.rdata = FLASH_TYPE_ID[15:0]; - 2: bus.rdata = FLASH_MODEL_ID[31:16]; - 3: bus.rdata = FLASH_MODEL_ID[15:0]; - endcase - end - end - - cfg.flashram_read_mode = flashram_state == FS_READ; - end - - always_ff @(posedge sys.clk) begin - bus.ack <= 1'b0; - - if (sys.reset) begin - bus_state <= S_IDLE; - flashram_state <= FS_STATUS; - flashram_status <= 4'b0000; - flashram_erase_enabled <= 1'b0; - flashram.operation_pending <= 1'b0; + always_ff @(posedge clk) begin + if (reset) begin + state <= STATE_STATUS; + status <= 4'b0000; + erase_enabled <= 1'b0; + n64_scb.flashram_pending <= 1'b0; end else begin - if (flashram.operation_done) begin - flashram.operation_pending <= 1'b0; - if (flashram.write_or_erase) begin - flashram_status[B_ERASE_BUSY] <= 1'b0; - flashram_status[B_ERASE_DONE] <= 1'b1; + if (n64_scb.flashram_done) begin + n64_scb.flashram_pending <= 1'b0; + if (n64_scb.flashram_write_or_erase) begin + status[ERASE_BUSY] <= 1'b0; + status[ERASE_DONE] <= 1'b1; end else begin - flashram_status[B_WRITE_BUSY] <= 1'b0; - flashram_status[B_WRITE_DONE] <= 1'b1; + status[WRITE_BUSY] <= 1'b0; + status[WRITE_DONE] <= 1'b1; end end - case (bus_state) - S_IDLE: begin - if (bus.request) begin - bus_state <= S_WAIT; - bus.ack <= 1'b1; - if (bus.write && !flashram.operation_pending) begin - if (bus.address[16]) begin - if (!bus.address[1]) begin - flashram_command <= bus.wdata[15:8]; - end else begin - flashram_erase_enabled <= 1'b0; + if (reg_bus.write && !n64_scb.flashram_pending) begin + if (reg_bus.address[16]) begin + if (!reg_bus.address[1]) begin + cmd <= reg_bus.wdata[15:8]; + end else begin + erase_enabled <= 1'b0; - case (flashram_command) - CMD_STATUS_MODE: begin - flashram_state <= FS_STATUS; - end + case (cmd) + CMD_STATUS_MODE: begin + state <= STATE_STATUS; + end - CMD_READID_MODE: begin - flashram_state <= FS_ID; - end + CMD_READID_MODE: begin + state <= STATE_ID; + end - CMD_READ_MODE: begin - flashram_state <= FS_READ; - end + CMD_READ_MODE: begin + state <= STATE_READ; + end - CMD_ERASE_SECTOR: begin - flashram_state <= FS_STATUS; - flashram_erase_enabled <= 1'b1; - flashram.sector <= bus.wdata[9:0]; - flashram.sector_or_all <= 1'b0; - end + CMD_ERASE_SECTOR: begin + state <= STATE_STATUS; + erase_enabled <= 1'b1; + n64_scb.flashram_sector <= reg_bus.wdata[9:0]; + n64_scb.flashram_sector_or_all <= 1'b0; + end - CMD_ERASE_CHIP: begin - flashram_state <= FS_STATUS; - flashram_erase_enabled <= 1'b1; - flashram.sector <= 10'd0; - flashram.sector_or_all <= 1'b1; - end + CMD_ERASE_CHIP: begin + state <= STATE_STATUS; + erase_enabled <= 1'b1; + n64_scb.flashram_sector <= 10'd0; + n64_scb.flashram_sector_or_all <= 1'b1; + end - CMD_BUFFER_MODE: begin - flashram_state <= FS_BUFFER; - end + CMD_BUFFER_MODE: begin + state <= STATE_BUFFER; + end - CMD_ERASE_START: begin - flashram_state <= FS_STATUS; - if (flashram_erase_enabled) begin - flashram_status[B_ERASE_BUSY] <= 1'b1; - flashram_status[B_ERASE_DONE] <= 1'b0; - flashram.operation_pending <= 1'b1; - flashram.write_or_erase <= 1'b1; - end - end - - CMD_WRITE_START: begin - flashram_state <= FS_STATUS; - flashram_status[B_WRITE_BUSY] <= 1'b1; - flashram_status[B_WRITE_DONE] <= 1'b0; - flashram.sector <= bus.wdata[9:0]; - flashram.operation_pending <= 1'b1; - flashram.write_or_erase <= 1'b0; - flashram.sector_or_all <= 1'b0; - end - endcase - end - end else begin - if (bus.address[1] && flashram_state == FS_STATUS) begin - flashram_status[B_ERASE_BUSY] <= bus.wdata[B_ERASE_BUSY]; - flashram_status[B_WRITE_BUSY] <= bus.wdata[B_WRITE_BUSY]; + CMD_ERASE_START: begin + state <= STATE_STATUS; + if (erase_enabled) begin + status[ERASE_BUSY] <= 1'b1; + status[ERASE_DONE] <= 1'b0; + n64_scb.flashram_pending <= 1'b1; + n64_scb.flashram_write_or_erase <= 1'b1; end end - end + + CMD_WRITE_START: begin + state <= STATE_STATUS; + status[WRITE_BUSY] <= 1'b1; + status[WRITE_DONE] <= 1'b0; + n64_scb.flashram_sector <= reg_bus.wdata[9:0]; + n64_scb.flashram_pending <= 1'b1; + n64_scb.flashram_write_or_erase <= 1'b0; + n64_scb.flashram_sector_or_all <= 1'b0; + end + endcase + end + end else begin + if (reg_bus.address[1] && state != STATE_BUFFER) begin + status[ERASE_BUSY] <= reg_bus.wdata[ERASE_BUSY]; + status[WRITE_BUSY] <= reg_bus.wdata[WRITE_BUSY]; end end - - S_WAIT: begin - bus_state <= S_IDLE; - end - endcase + end end end + always_comb begin + n64_scb.flashram_write = reg_bus.write && !reg_bus.address[16] && state == STATE_BUFFER; + n64_scb.flashram_address = reg_bus.address[6:1]; + n64_scb.flashram_wdata = reg_bus.wdata; + end + endmodule diff --git a/fw/rtl/n64/n64_pi.sv b/fw/rtl/n64/n64_pi.sv index 8d012c8..e15da47 100644 --- a/fw/rtl/n64/n64_pi.sv +++ b/fw/rtl/n64/n64_pi.sv @@ -1,8 +1,14 @@ module n64_pi ( - if_system.sys sys, - if_config.pi cfg, - if_n64_bus.n64 bus, + input clk, + input reset, + mem_bus.controller mem_bus, + n64_reg_bus.controller reg_bus, + + n64_scb.pi n64_scb, + + input n64_reset, + input n64_nmi, input n64_pi_alel, input n64_pi_aleh, input n64_pi_read, @@ -10,81 +16,36 @@ module n64_pi ( inout [15:0] n64_pi_ad ); - // FIFOs - - logic read_fifo_flush; - - logic read_fifo_full; - logic read_fifo_write; - logic [15:0] read_fifo_wdata; - - logic read_fifo_empty; - logic read_fifo_read; - logic [15:0] read_fifo_rdata; - - n64_pi_fifo read_fifo_inst ( - .sys(sys), - - .flush(read_fifo_flush), - - .full(read_fifo_full), - .write(read_fifo_write), - .wdata(read_fifo_wdata), - - .empty(read_fifo_empty), - .read(read_fifo_read), - .rdata(read_fifo_rdata) - ); - - logic write_fifo_flush; - - logic write_fifo_full; - logic write_fifo_write; - logic [15:0] write_fifo_wdata; - - logic write_fifo_empty; - logic write_fifo_read; - logic [15:0] write_fifo_rdata; - - n64_pi_fifo write_fifo_inst ( - .sys(sys), - - .flush(write_fifo_flush), - - .full(write_fifo_full), - .write(write_fifo_write), - .wdata(write_fifo_wdata), - - .empty(write_fifo_empty), - .read(write_fifo_read), - .rdata(write_fifo_rdata) - ); - - // Control signals and input synchronization - logic [2:0] n64_pi_alel_ff; - logic [2:0] n64_pi_aleh_ff; - logic [2:0] n64_pi_read_ff; + logic [1:0] n64_reset_ff; + logic [1:0] n64_nmi_ff; + logic [3:0] n64_pi_alel_ff; + logic [3:0] n64_pi_aleh_ff; + logic [1:0] n64_pi_read_ff; logic [2:0] n64_pi_write_ff; - always_ff @(posedge sys.clk) begin - n64_pi_aleh_ff <= {n64_pi_aleh_ff[1:0], n64_pi_aleh}; - n64_pi_alel_ff <= {n64_pi_alel_ff[1:0], n64_pi_alel}; - n64_pi_read_ff <= {n64_pi_read_ff[1:0], n64_pi_read}; + always_ff @(posedge clk) begin + n64_reset_ff <= {n64_reset_ff[0], n64_reset}; + n64_nmi_ff <= {n64_nmi_ff[0], n64_nmi}; + n64_pi_aleh_ff <= {n64_pi_aleh_ff[2:0], n64_pi_aleh}; + n64_pi_alel_ff <= {n64_pi_alel_ff[2:0], n64_pi_alel}; + n64_pi_read_ff <= {n64_pi_read_ff[0], n64_pi_read}; n64_pi_write_ff <= {n64_pi_write_ff[1:0], n64_pi_write}; end logic pi_reset; + logic pi_nmi; logic pi_aleh; logic pi_alel; logic pi_read; logic pi_write; always_comb begin - pi_reset = sys.n64_hard_reset; - pi_aleh = n64_pi_aleh_ff[2]; - pi_alel = n64_pi_alel_ff[2]; + pi_reset = n64_reset_ff[1]; + pi_nmi = n64_nmi_ff[1]; + pi_aleh = n64_pi_aleh_ff[3]; + pi_alel = n64_pi_alel_ff[3]; pi_read = n64_pi_read_ff[1]; pi_write = n64_pi_write_ff[2]; end @@ -99,16 +60,30 @@ module n64_pi ( PI_MODE_VALID = 2'b00 } e_pi_mode; + typedef enum bit [1:0] { + PORT_NONE, + PORT_MEM, + PORT_REG + } e_port; + e_pi_mode pi_mode; - e_pi_mode last_pi_mode; - logic last_read; - logic last_write; + + e_port read_port; + e_port write_port; always_comb begin pi_mode = e_pi_mode'({pi_aleh, pi_alel}); end - always_ff @(posedge sys.clk) begin + logic last_reset; + logic last_nmi; + e_pi_mode last_pi_mode; + logic last_read; + logic last_write; + + always_ff @(posedge clk) begin + last_reset <= pi_reset; + last_nmi <= pi_nmi; last_pi_mode <= pi_mode; last_read <= pi_read; last_write <= pi_write; @@ -121,250 +96,394 @@ module n64_pi ( logic end_op; always_comb begin - aleh_op = !pi_reset && last_pi_mode != PI_MODE_HIGH && pi_mode == PI_MODE_HIGH; - alel_op = !pi_reset && last_pi_mode == PI_MODE_HIGH && pi_mode == PI_MODE_LOW; - read_op = !pi_reset && pi_mode == PI_MODE_VALID && last_read && !pi_read; - write_op = !pi_reset && pi_mode == PI_MODE_VALID && last_write && !pi_write; - end_op = !pi_reset && last_pi_mode == PI_MODE_VALID && pi_mode != PI_MODE_VALID; + n64_scb.n64_reset = !last_reset && pi_reset; + n64_scb.n64_nmi = !last_nmi && pi_nmi; + aleh_op = pi_reset && (last_pi_mode != PI_MODE_HIGH) && (pi_mode == PI_MODE_HIGH); + alel_op = pi_reset && (last_pi_mode == PI_MODE_HIGH) && (pi_mode == PI_MODE_LOW); + read_op = pi_reset && (pi_mode == PI_MODE_VALID) && (read_port != PORT_NONE) && (last_read && !pi_read); + write_op = pi_reset && (pi_mode == PI_MODE_VALID) && (write_port != PORT_NONE) && (last_write && !pi_write); + end_op = pi_reset && (last_pi_mode == PI_MODE_VALID) && (pi_mode != PI_MODE_VALID); end // Input and output data sampling - logic [15:0] n64_pi_ad_input; - logic [15:0] n64_pi_ad_output; - logic [15:0] n64_pi_ad_output_data; - logic n64_pi_ad_output_enable; - logic n64_pi_ad_output_enable_data; - - logic n64_pi_address_valid; - logic pending_operation; - logic pending_write; + logic n64_pi_ad_oe; + logic [15:0] n64_pi_ad_out; + logic [15:0] n64_pi_dq_in; + logic [15:0] n64_pi_dq_out; - always_comb begin - n64_pi_ad = n64_pi_ad_output_enable ? n64_pi_ad_output : 16'hZZZZ; - n64_pi_ad_output_enable_data = !pi_reset && pi_mode == PI_MODE_VALID && n64_pi_address_valid && !n64_pi_read_ff[2]; + assign n64_pi_ad = n64_pi_ad_oe ? n64_pi_ad_out : 16'hZZZZ; + + always_ff @(posedge clk) begin + n64_pi_ad_oe <= pi_reset && (pi_mode == PI_MODE_VALID) && !last_read && (read_port != PORT_NONE); + n64_pi_ad_out <= n64_pi_dq_out; + n64_pi_dq_in <= n64_pi_ad; end - always_ff @(posedge sys.clk) begin - n64_pi_ad_input <= n64_pi_ad; - n64_pi_ad_output <= n64_pi_ad_output_data; - n64_pi_ad_output_enable <= n64_pi_ad_output_enable_data; - end - - logic wait_for_read_fifo; - logic wait_for_write_fifo; - always_comb begin - read_fifo_write = bus.ack && !bus.write; - read_fifo_wdata = bus.rdata; - - write_fifo_wdata = n64_pi_ad_input; - end + // Debug: last accessed PI address - always_ff @(posedge sys.clk) begin - read_fifo_read <= 1'b0; - write_fifo_write <= 1'b0; - - if (sys.reset || sys.n64_hard_reset) begin - wait_for_read_fifo <= 1'b0; - wait_for_write_fifo <= 1'b0; - end else if (n64_pi_address_valid) begin - if (read_op || wait_for_read_fifo) begin - if (read_fifo_empty) begin - wait_for_read_fifo <= 1'b1; - end else begin - n64_pi_ad_output_data <= read_fifo_rdata; - read_fifo_read <= 1'b1; - wait_for_read_fifo <= 1'b0; - end - end - if (write_op || wait_for_write_fifo) begin - if (write_fifo_full) begin - wait_for_write_fifo <= 1'b1; - end else begin - write_fifo_write <= 1'b1; - wait_for_write_fifo <= 1'b0; - end - end - end - end - - always_comb begin - bus.read_op = read_op; - bus.write_op = write_op; - end - - always_ff @(posedge sys.clk) begin + always_ff @(posedge clk) begin if (aleh_op) begin - bus.real_address[31:16] <= n64_pi_ad_input; + n64_scb.pi_debug[31:16] <= n64_pi_dq_in; end if (alel_op) begin - bus.real_address[15:0] <= {n64_pi_ad_input[15:1], 1'b0}; - end - if (read_op || write_op) begin - bus.real_address <= bus.real_address + 2'd2; + n64_scb.pi_debug[15:0] <= n64_pi_dq_in; end end // Address decoding - sc64::e_n64_id next_id; - logic [31:0] next_offset; - logic sram_selected; - logic cfg_selected; + const bit [31:0] DDIPL_OFFSET = 32'h03BC_0000; + const bit [31:0] SAVE_OFFSET = 32'h03FE_0000; + const bit [31:0] FLASH_OFFSET = 32'h0400_0000; + const bit [31:0] BOOTLOADER_OFFSET = 32'h04E0_0000; + const bit [31:0] SHADOW_OFFSET = 32'h04FE_0000; + const bit [31:0] BUFFER_OFFSET = 32'h0500_0000; - always_ff @(posedge sys.clk) begin - if (aleh_op) begin - n64_pi_address_valid <= 1'b0; - next_offset <= 32'd0; - sram_selected <= 1'b0; - cfg_selected <= 1'b0; - if (cfg.dd_enabled) begin - if (n64_pi_ad_input == 16'h0500) begin - n64_pi_address_valid <= 1'b1; - next_id <= sc64::ID_N64_DD; - end - if (n64_pi_ad_input >= 16'h0600 && n64_pi_ad_input < 16'h0640) begin - n64_pi_address_valid <= 1'b1; - next_id <= sc64::ID_N64_SDRAM; - next_offset <= cfg.ddipl_offset + 32'h0A00_0000; + logic [31:0] mem_offset; + + always_ff @(posedge clk) begin + if (reset || !pi_reset || end_op) begin + n64_scb.pi_sdram_active <= 1'b0; + n64_scb.pi_flash_active <= 1'b0; + end + + if (reset) begin + read_port <= PORT_NONE; + write_port <= PORT_NONE; + reg_bus.dd_select <= 1'b0; + reg_bus.flashram_select <= 1'b0; + reg_bus.cfg_select <= 1'b0; + end else if (aleh_op) begin + read_port <= PORT_NONE; + write_port <= PORT_NONE; + mem_offset <= 32'd0; + reg_bus.dd_select <= 1'b0; + reg_bus.flashram_select <= 1'b0; + reg_bus.cfg_select <= 1'b0; + + if (n64_scb.dd_enabled) begin + if (n64_pi_dq_in == 16'h0500) begin + read_port <= PORT_REG; + write_port <= PORT_REG; + reg_bus.dd_select <= 1'b1; end end - if (cfg.flashram_enabled) begin - if (n64_pi_ad_input >= 16'h0800 && n64_pi_ad_input < 16'h0802) begin - n64_pi_address_valid <= 1'b1; - next_id <= sc64::ID_N64_FLASHRAM; - if (cfg.flashram_read_mode) begin - next_offset <= cfg.save_offset + 32'h0800_0000; + + if (n64_scb.ddipl_enabled) begin + if (n64_pi_dq_in >= 16'h0600 && n64_pi_dq_in < 16'h0640) begin + read_port <= PORT_MEM; + write_port <= PORT_NONE; + mem_offset <= (-32'h0600_0000) + DDIPL_OFFSET; + n64_scb.pi_sdram_active <= 1'b1; + end + end + + if (n64_scb.flashram_enabled) begin + if (n64_pi_dq_in >= 16'h0800 && n64_pi_dq_in < 16'h0802) begin + read_port <= PORT_REG; + write_port <= PORT_REG; + mem_offset <= (-32'h0800_0000) + SAVE_OFFSET; + reg_bus.flashram_select <= 1'b1; + if (n64_scb.flashram_read_mode) begin + read_port <= PORT_MEM; + n64_scb.pi_sdram_active <= 1'b1; end end - end else if (cfg.sram_enabled) begin - if (cfg.sram_banked) begin - if (n64_pi_ad_input >= 16'h0800 && n64_pi_ad_input < 16'h0810) begin - if (n64_pi_ad_input[3:2] != 2'b11 && n64_pi_ad_input[1:0] == 2'b00) begin - n64_pi_address_valid <= 1'b1; - next_id <= sc64::ID_N64_SDRAM; - next_offset <= cfg.save_offset - {n64_pi_ad_input[3:2], 18'd0} + {n64_pi_ad_input[3:2], 15'd0} + 32'h0800_0000; - sram_selected <= 1'b1; + end else if (n64_scb.sram_enabled) begin + if (n64_scb.sram_banked) begin + if (n64_pi_dq_in >= 16'h0800 && n64_pi_dq_in < 16'h0810) begin + if (n64_pi_dq_in[3:2] != 2'b11 && n64_pi_dq_in[1:0] == 2'b00) begin + read_port <= PORT_MEM; + write_port <= PORT_MEM; + mem_offset <= (-32'h0800_0000) - {n64_pi_dq_in[3:2], 18'd0} + {n64_pi_dq_in[3:2], 15'd0} + SAVE_OFFSET; + n64_scb.pi_sdram_active <= 1'b1; end end end else begin - if (n64_pi_ad_input == 16'h0800) begin - n64_pi_address_valid <= 1'b1; - next_id <= sc64::ID_N64_SDRAM; - next_offset <= cfg.save_offset + 32'h0800_0000; - sram_selected <= 1'b1; + if (n64_pi_dq_in >= 16'h0800 && n64_pi_dq_in < 16'h0802) begin + read_port <= PORT_MEM; + write_port <= PORT_MEM; + mem_offset <= (-32'h0800_0000) + SAVE_OFFSET; + n64_scb.pi_sdram_active <= 1'b1; end end end - if (n64_pi_ad_input >= 16'h1000 && n64_pi_ad_input < 16'h1400) begin - n64_pi_address_valid <= 1'b1; - next_id <= cfg.sdram_switch ? sc64::ID_N64_SDRAM : sc64::ID_N64_BOOTLOADER; - end - if (n64_pi_ad_input == 16'h1FFF) begin - n64_pi_address_valid <= 1'b1; - next_id <= sc64::ID_N64_CFG; - cfg_selected <= 1'b1; - end - end - if (alel_op) begin - if (next_id == sc64::ID_N64_DD) begin - if (|n64_pi_ad_input[15:11]) begin - n64_pi_address_valid <= 1'b0; + + if (n64_scb.bootloader_enabled) begin + if (n64_pi_dq_in >= 16'h1000 && n64_pi_dq_in < 16'h101C) begin + read_port <= PORT_MEM; + write_port <= PORT_NONE; + mem_offset <= (-32'h1000_0000) + BOOTLOADER_OFFSET; + n64_scb.pi_flash_active <= 1'b1; + end + end else begin + if (n64_pi_dq_in >= 16'h1000 && n64_pi_dq_in < 16'h1400) begin + read_port <= PORT_MEM; + write_port <= n64_scb.rom_write_enabled ? PORT_MEM : PORT_NONE; + mem_offset <= (-32'h1000_0000); + n64_scb.pi_sdram_active <= 1'b1; end end - if (sram_selected) begin - if (n64_pi_ad_input[15]) begin - n64_pi_address_valid <= 1'b0; + + if (n64_scb.rom_shadow_enabled) begin + if (n64_pi_dq_in >= 16'h13FE && n64_pi_dq_in < 16'h1400) begin + read_port <= PORT_MEM; + write_port <= PORT_NONE; + mem_offset <= (-32'h13FE_0000) + SHADOW_OFFSET; + n64_scb.pi_flash_active <= 1'b1; end end - if (cfg_selected) begin - if (|n64_pi_ad_input[15:4]) begin - n64_pi_address_valid <= 1'b0; + + if (n64_scb.rom_extended_enabled) begin + if (n64_pi_dq_in >= 16'h1400 && n64_pi_dq_in < 16'h14E0) begin + read_port <= PORT_MEM; + write_port <= PORT_NONE; + mem_offset <= (-32'h1400_0000) + FLASH_OFFSET; + n64_scb.pi_flash_active <= 1'b1; end end + + if (n64_scb.cfg_unlock) begin + if (n64_pi_dq_in >= 16'h1FFC && n64_pi_dq_in < 16'h1FFE) begin + read_port <= PORT_MEM; + write_port <= PORT_NONE; + mem_offset <= (-32'h1FFC_0000) + SHADOW_OFFSET; + n64_scb.pi_flash_active <= 1'b1; + end + + if (n64_pi_dq_in >= 16'h1FFE && n64_pi_dq_in < 16'h1FFF) begin + read_port <= PORT_MEM; + write_port <= PORT_MEM; + mem_offset <= (-32'h1FFE_0000) + BUFFER_OFFSET; + end + end + + if (n64_pi_dq_in >= 16'h1FFF && n64_pi_dq_in < 16'h2000) begin + read_port <= n64_scb.cfg_unlock ? PORT_REG : PORT_NONE; + write_port <= PORT_REG; + reg_bus.cfg_select <= 1'b1; + end end end - // Bus controller + // Mem bus read FIFO controller + + logic read_fifo_full; + logic read_fifo_write; + logic [15:0] read_fifo_wdata; + + logic read_fifo_empty; + logic read_fifo_read; + logic [15:0] read_fifo_rdata; + + logic read_fifo_wait; + + n64_pi_fifo read_fifo_inst ( + .clk(clk), + .reset(reset), + + .flush(reset || !pi_reset || alel_op), + + .full(read_fifo_full), + .write(read_fifo_write), + .wdata(read_fifo_wdata), + + .empty(read_fifo_empty), + .read(read_fifo_read), + .rdata(read_fifo_rdata) + ); + + always_ff @(posedge clk) begin + read_fifo_read <= 1'b0; + + if (!pi_reset) begin + n64_scb.pi_debug[33:32] <= 2'b00; + end + + if (reset || !pi_reset || alel_op) begin + read_fifo_wait <= 1'b0; + end + + if (read_port == PORT_MEM) begin + if (read_op) begin + if (read_fifo_empty) begin + read_fifo_wait <= 1'b1; + n64_scb.pi_debug[32] <= 1'b1; + if (read_fifo_wait) begin + n64_scb.pi_debug[33] <= 1'b1; + end + end else begin + read_fifo_read <= 1'b1; + n64_pi_dq_out <= read_fifo_rdata; + end + end + + if (!read_fifo_empty && read_fifo_wait) begin + read_fifo_read <= 1'b1; + read_fifo_wait <= 1'b0; + n64_pi_dq_out <= read_fifo_rdata; + end + end + + if (read_port == PORT_REG) begin + if (read_op) begin + n64_pi_dq_out <= reg_bus.rdata; + end + end + end + + + // Mem bus write FIFO controller + + logic write_fifo_full; + logic write_fifo_write; + logic [15:0] write_fifo_wdata; + + logic write_fifo_empty; + logic write_fifo_read; + logic [15:0] write_fifo_rdata; + + logic write_fifo_wait; + + n64_pi_fifo write_fifo_inst ( + .clk(clk), + .reset(reset), + + .flush(reset), + + .full(write_fifo_full), + .write(write_fifo_write), + .wdata(write_fifo_wdata), + + .empty(write_fifo_empty), + .read(write_fifo_read), + .rdata(write_fifo_rdata) + ); + + always_ff @(posedge clk) begin + write_fifo_write <= 1'b0; + + if (!pi_reset) begin + n64_scb.pi_debug[35:34] <= 2'b00; + end + + if (reset) begin + write_fifo_wait <= 1'b0; + end + + if (write_port == PORT_MEM) begin + if (write_op) begin + if (write_fifo_full) begin + write_fifo_wait <= 1'b1; + n64_scb.pi_debug[34] <= 1'b1; + if (write_fifo_wait) begin + n64_scb.pi_debug[35] <= 1'b1; + end + end else begin + write_fifo_write <= 1'b1; + write_fifo_wdata <= n64_pi_dq_in; + end + end + + if (!write_fifo_full && write_fifo_wait) begin + write_fifo_write <= 1'b1; + write_fifo_wait <= 1'b0; + write_fifo_wdata <= n64_pi_dq_in; + end + end + end + + + // Mem bus controller - logic can_read; - logic first_write_op; - logic load_starting_address; - sc64::e_n64_id starting_id; logic [31:0] starting_address; + logic load_starting_address; + logic read_enabled; + logic first_write_op; - always_ff @(posedge sys.clk) begin - read_fifo_flush <= 1'b0; - + always_ff @(posedge clk) begin write_fifo_read <= 1'b0; + load_starting_address <= 1'b0; - if (sys.reset || sys.n64_hard_reset) begin - bus.request <= 1'b0; - read_fifo_flush <= 1'b1; - write_fifo_flush <= 1'b1; + if (reset || !pi_reset) begin + mem_bus.request <= 1'b0; + read_enabled <= 1'b0; end else begin - write_fifo_flush <= starting_id == sc64::ID_N64_SDRAM && !cfg.sdram_writable && !sram_selected; - if (aleh_op) begin - starting_address[31:16] <= n64_pi_ad_input; + starting_address[31:16] <= n64_pi_dq_in; end if (alel_op) begin - read_fifo_flush <= 1'b1; - can_read <= 1'b1; - first_write_op <= 1'b1; + starting_address <= {starting_address[31:16], n64_pi_dq_in} + mem_offset; load_starting_address <= 1'b1; - starting_id <= next_id; - starting_address <= {starting_address[31:16], n64_pi_ad_input[15:1], 1'b0}; + read_enabled <= 1'b1; + first_write_op <= 1'b1; end - if (write_op) begin - can_read <= 1'b0; - if (first_write_op) begin - first_write_op <= 1'b0; - load_starting_address <= 1'b1; - end + if (load_starting_address) begin + mem_bus.address <= starting_address; end - if (!bus.request) begin - if (!write_fifo_empty) begin - bus.request <= 1'b1; - bus.write <= 1'b1; - if (load_starting_address) begin - bus.id <= starting_id; - bus.address <= starting_address + next_offset; - if (starting_id == sc64::ID_N64_FLASHRAM) begin - bus.address <= starting_address; - end - load_starting_address <= 1'b0; - end - bus.wdata <= write_fifo_rdata; + if (!mem_bus.request) begin + if ((write_port == PORT_MEM) && !write_fifo_empty) begin + mem_bus.request <= 1'b1; + mem_bus.write <= 1'b1; + mem_bus.wdata <= write_fifo_rdata; write_fifo_read <= 1'b1; - end else if (!read_fifo_full && can_read) begin - bus.request <= 1'b1; - bus.write <= 1'b0; - if (load_starting_address) begin - bus.id <= starting_id; - bus.address <= starting_address + next_offset; - if (starting_id == sc64::ID_N64_FLASHRAM && cfg.flashram_read_mode) begin - bus.id <= sc64::ID_N64_SDRAM; - end - load_starting_address <= 1'b0; + read_enabled <= 1'b0; + if (first_write_op) begin + mem_bus.address <= starting_address; + first_write_op <= 1'b0; end + end else if ((read_port == PORT_MEM) && !read_fifo_full && read_enabled) begin + mem_bus.request <= 1'b1; + mem_bus.write <= 1'b0; end - end else if (bus.ack) begin - bus.request <= 1'b0; - bus.address <= bus.address + 2'd2; + end + + if (mem_bus.ack) begin + mem_bus.request <= 1'b0; + mem_bus.address[16:0] <= mem_bus.address[16:0] + 2'd2; end if (end_op) begin - can_read <= 1'b0; + read_enabled <= 1'b0; end end end + always_comb begin + read_fifo_write = !mem_bus.write && mem_bus.ack; + read_fifo_wdata = mem_bus.rdata; + mem_bus.wmask = 2'b11; + end + + + // Reg bus controller + + always_ff @(posedge clk) begin + if (aleh_op) begin + reg_bus.address[16] <= n64_pi_dq_in[0]; + end + + if (alel_op) begin + reg_bus.address[15:0] <= n64_pi_dq_in; + end + + if (read_op || write_op) begin + reg_bus.address <= reg_bus.address + 2'd2; + end + end + + always_comb begin + reg_bus.read = read_op && (read_port == PORT_REG); + reg_bus.write = write_op && (write_port == PORT_REG); + reg_bus.wdata = n64_pi_dq_in; + end + endmodule diff --git a/fw/rtl/n64/n64_pi_fifo.sv b/fw/rtl/n64/n64_pi_fifo.sv index 63dde9e..80c27bd 100644 --- a/fw/rtl/n64/n64_pi_fifo.sv +++ b/fw/rtl/n64/n64_pi_fifo.sv @@ -1,5 +1,6 @@ module n64_pi_fifo ( - if_system.sys sys, + input clk, + input reset, input flush, @@ -18,15 +19,13 @@ module n64_pi_fifo ( logic empty_or_full; - always_comb begin - rdata = fifo_mem[fifo_rd_ptr[1:0]]; - empty_or_full = fifo_wr_ptr[1:0] == fifo_rd_ptr[1:0]; - empty = empty_or_full && fifo_wr_ptr[2] == fifo_rd_ptr[2]; - full = empty_or_full && fifo_wr_ptr[2] != fifo_rd_ptr[2]; - end + assign rdata = fifo_mem[fifo_rd_ptr[1:0]]; + assign empty_or_full = fifo_wr_ptr[1:0] == fifo_rd_ptr[1:0]; + assign empty = empty_or_full && fifo_wr_ptr[2] == fifo_rd_ptr[2]; + assign full = empty_or_full && fifo_wr_ptr[2] != fifo_rd_ptr[2]; - always_ff @(posedge sys.clk) begin - if (sys.reset || flush) begin + always_ff @(posedge clk) begin + if (reset || flush) begin fifo_wr_ptr <= 3'd0; fifo_rd_ptr <= 3'd0; end else begin diff --git a/fw/rtl/n64/n64_reg_bus.sv b/fw/rtl/n64/n64_reg_bus.sv new file mode 100644 index 0000000..07573b7 --- /dev/null +++ b/fw/rtl/n64/n64_reg_bus.sv @@ -0,0 +1,66 @@ +interface n64_reg_bus (); + + logic flashram_select; + logic dd_select; + logic cfg_select; + + logic read; + logic write; + logic [16:0] address; + logic [15:0] rdata; + logic [15:0] wdata; + + logic [15:0] flashram_rdata; + logic [15:0] dd_rdata; + logic [15:0] cfg_rdata; + + modport controller ( + output flashram_select, + output dd_select, + output cfg_select, + + output read, + output write, + output address, + input rdata, + output wdata + ); + + always_comb begin + rdata = 16'd0; + if (flashram_select) begin + rdata = flashram_rdata; + end + if (dd_select) begin + rdata = dd_rdata; + end + if (cfg_select) begin + rdata = cfg_rdata; + end + end + + modport flashram ( + input .read(read && flashram_select), + input .write(write && flashram_select), + input address, + output .rdata(flashram_rdata), + input wdata + ); + + modport dd ( + input .read(read && dd_select), + input .write(write && dd_select), + input address, + output .rdata(dd_rdata), + input wdata + ); + + modport cfg ( + input .read(read && cfg_select), + input .write(write && cfg_select), + input address, + output .rdata(cfg_rdata), + input wdata + ); + +endinterface diff --git a/fw/rtl/n64/n64_scb.sv b/fw/rtl/n64/n64_scb.sv new file mode 100644 index 0000000..c61f103 --- /dev/null +++ b/fw/rtl/n64/n64_scb.sv @@ -0,0 +1,197 @@ +interface n64_scb (); + + logic n64_reset; + logic n64_nmi; + + logic bootloader_enabled; + logic rom_write_enabled; + logic rom_shadow_enabled; + logic rom_extended_enabled; + logic sram_enabled; + logic sram_banked; + logic flashram_enabled; + logic dd_enabled; + logic ddipl_enabled; + logic eeprom_enabled; + logic eeprom_16k_mode; + + logic dd_write; + logic [6:0] dd_address; + logic [15:0] dd_rdata; + logic [15:0] dd_wdata; + + logic flashram_pending; + logic flashram_done; + logic [9:0] flashram_sector; + logic flashram_sector_or_all; + logic flashram_write_or_erase; + logic flashram_read_mode; + logic flashram_write; + logic [5:0] flashram_address; + logic [15:0] flashram_wdata; + + logic eeprom_write; + logic [10:0] eeprom_address; + logic [7:0] eeprom_rdata; + logic [7:0] eeprom_wdata; + + logic rtc_pending; + logic rtc_done; + logic rtc_wdata_valid; + logic [41:0] rtc_rdata; + logic [41:0] rtc_wdata; + + logic cfg_unlock; + logic cfg_pending; + logic cfg_done; + logic cfg_error; + logic cfg_irq; + logic [7:0] cfg_cmd; + logic [31:0] cfg_rdata [0:1]; + logic [31:0] cfg_wdata [0:1]; + logic [31:0] cfg_version; + + logic pi_sdram_active; + logic pi_flash_active; + logic [35:0] pi_debug; + + modport controller ( + input n64_reset, + input n64_nmi, + + output bootloader_enabled, + output rom_write_enabled, + output rom_shadow_enabled, + output rom_extended_enabled, + output sram_enabled, + output sram_banked, + output flashram_enabled, + output dd_enabled, + output ddipl_enabled, + output eeprom_enabled, + output eeprom_16k_mode, + + input flashram_pending, + output flashram_done, + input flashram_sector, + input flashram_sector_or_all, + input flashram_write_or_erase, + + input rtc_pending, + output rtc_done, + output rtc_wdata_valid, + input rtc_rdata, + output rtc_wdata, + + input cfg_pending, + output cfg_done, + output cfg_error, + output cfg_irq, + input cfg_cmd, + input cfg_rdata, + output cfg_wdata, + output cfg_version, + + input pi_debug + ); + + modport pi ( + output n64_reset, + output n64_nmi, + + input bootloader_enabled, + input rom_write_enabled, + input rom_shadow_enabled, + input rom_extended_enabled, + input sram_enabled, + input sram_banked, + input flashram_enabled, + input dd_enabled, + input ddipl_enabled, + + input flashram_read_mode, + + input cfg_unlock, + + output pi_sdram_active, + output pi_flash_active, + output pi_debug + ); + + modport flashram ( + output flashram_pending, + input flashram_done, + output flashram_sector, + output flashram_sector_or_all, + output flashram_write_or_erase, + + output flashram_read_mode, + + output flashram_write, + output flashram_address, + output flashram_wdata + ); + + modport si ( + input eeprom_enabled, + input eeprom_16k_mode, + + output eeprom_write, + output eeprom_address, + input eeprom_rdata, + output eeprom_wdata, + + output rtc_pending, + input rtc_done, + input rtc_wdata_valid, + output rtc_rdata, + input rtc_wdata + ); + + modport dd ( + input n64_reset, + input n64_nmi, + + output dd_write, + output dd_address, + input dd_rdata, + output dd_wdata + ); + + modport bram ( + input flashram_write, + input flashram_address, + input flashram_wdata, + + input eeprom_write, + input eeprom_address, + output eeprom_rdata, + input eeprom_wdata, + + input dd_write, + input dd_address, + output dd_rdata, + input dd_wdata + ); + + modport cfg ( + input n64_reset, + input n64_nmi, + + output cfg_unlock, + output cfg_pending, + input cfg_done, + input cfg_error, + input cfg_irq, + output cfg_cmd, + output cfg_rdata, + input cfg_wdata, + input cfg_version + ); + + modport arbiter ( + input pi_sdram_active, + input pi_flash_active + ); + +endinterface diff --git a/fw/rtl/n64/n64_sdram.sv b/fw/rtl/n64/n64_sdram.sv deleted file mode 100644 index cc0e6fc..0000000 --- a/fw/rtl/n64/n64_sdram.sv +++ /dev/null @@ -1,106 +0,0 @@ -module n64_sdram ( - if_system sys, - if_n64_bus bus, - if_dma.memory dma, - if_sdram.memory sdram, - - output sdram_cs, - output sdram_ras, - output sdram_cas, - output sdram_we, - output [1:0] sdram_ba, - output [12:0] sdram_a, - inout [15:0] sdram_dq -); - - logic mem_request; - logic mem_ack; - logic mem_write; - logic [31:0] mem_address; - logic [15:0] mem_rdata; - logic [15:0] mem_wdata; - - typedef enum bit [0:0] { - S_IDLE, - S_WAIT - } e_state; - - typedef enum bit [1:0] { - T_BUS, - T_DMA, - T_SDRAM - } e_source_request; - - e_state state; - e_source_request source_request; - - always_ff @(posedge sys.clk) begin - if (sys.reset) begin - state <= S_IDLE; - mem_request <= 1'b0; - end else begin - case (state) - S_IDLE: begin - if (bus.request || sdram.request || dma.request) begin - state <= S_WAIT; - mem_request <= 1'b1; - if (bus.request) begin - mem_write <= bus.write; - mem_address <= bus.address; - mem_wdata <= bus.wdata; - source_request <= T_BUS; - end else if (sdram.request) begin - mem_write <= sdram.write; - mem_address <= sdram.address; - mem_wdata <= sdram.wdata; - source_request <= T_SDRAM; - end else if (dma.request) begin - mem_write <= dma.write; - mem_address <= dma.address; - mem_wdata <= dma.wdata; - source_request <= T_DMA; - end - end - end - - S_WAIT: begin - if (mem_ack) begin - state <= S_IDLE; - mem_request <= 1'b0; - end - end - endcase - end - end - - always_comb begin - bus.ack = source_request == T_BUS && mem_ack; - bus.rdata = bus.ack ? mem_rdata : 16'd0; - - dma.ack = source_request == T_DMA && mem_ack; - dma.rdata = mem_rdata; - - sdram.ack = source_request == T_SDRAM && mem_ack; - sdram.rdata = mem_rdata; - end - - memory_sdram memory_sdram_inst ( - .sys(sys), - - .request(mem_request), - .ack(mem_ack), - .write(mem_write), - .address(mem_address[25:0]), - .rdata(mem_rdata), - .wdata(mem_wdata), - - .sdram_cs(sdram_cs), - .sdram_ras(sdram_ras), - .sdram_cas(sdram_cas), - .sdram_we(sdram_we), - .sdram_ba(sdram_ba), - .sdram_a(sdram_a), - .sdram_dq(sdram_dq) - ); - -endmodule diff --git a/fw/rtl/n64/n64_si.sv b/fw/rtl/n64/n64_si.sv index 6ecac5d..cbc7482 100644 --- a/fw/rtl/n64/n64_si.sv +++ b/fw/rtl/n64/n64_si.sv @@ -1,164 +1,253 @@ -interface if_si (); - - logic rx_reset; - logic rx_ready; - logic [6:0] rx_length; - logic [80:0] rx_data; - - logic tx_reset; - logic tx_start; - logic tx_busy; - logic [2:0] tx_wmask; - logic [6:0] tx_length; - logic [31:0] tx_data; - - modport si ( - input rx_reset, - output rx_ready, - output rx_length, - output rx_data, - input tx_reset, - input tx_start, - output tx_busy, - input tx_wmask, - input tx_length, - input tx_data - ); - - modport cpu ( - output rx_reset, - input rx_ready, - input rx_length, - input rx_data, - output tx_reset, - output tx_start, - input tx_busy, - output tx_wmask, - output tx_length, - output tx_data - ); - -endinterface - module n64_si ( - if_system.sys sys, - if_si.si si, + input clk, + input reset, + n64_scb.si n64_scb, + + input n64_reset, input n64_si_clk, inout n64_si_dq ); - // Control signals and input synchronization + // Input/output synchronization + logic [1:0] n64_reset_ff; logic [1:0] n64_si_clk_ff; - always_ff @(posedge sys.clk) begin + always_ff @(posedge clk) begin + n64_reset_ff <= {n64_reset_ff[0], n64_reset}; n64_si_clk_ff <= {n64_si_clk_ff[0], n64_si_clk}; end logic si_reset; logic si_clk; - logic si_dq; always_comb begin - si_reset = sys.n64_hard_reset; + si_reset = n64_reset_ff[1]; si_clk = n64_si_clk_ff[1]; - si_dq = n64_si_dq; end + logic si_dq_oe; + logic si_dq_out; + logic si_dq_in; + + assign n64_si_dq = si_dq_oe ? 1'b0 : 1'bZ; + + always_ff @(posedge clk) begin + si_dq_oe <= ~si_dq_out; + si_dq_in <= n64_si_dq; + end + + + // Clock falling/rising event generator + logic last_si_clk; - always_ff @(posedge sys.clk) begin + always_ff @(posedge clk) begin last_si_clk <= si_clk; end - logic si_clk_rising_edge; logic si_clk_falling_edge; + logic si_clk_rising_edge; always_comb begin - si_clk_rising_edge = !si_reset && !last_si_clk && si_clk; - si_clk_falling_edge = !si_reset && last_si_clk && !si_clk; - end - - logic si_dq_output_enable; - logic si_dq_output_enable_data; - - always_ff @(posedge sys.clk) begin - si_dq_output_enable <= si_dq_output_enable_data; - end - - always_comb begin - n64_si_dq = si_dq_output_enable ? 1'b0 : 1'bZ; + si_clk_falling_edge = si_reset && last_si_clk && !si_clk; + si_clk_rising_edge = si_reset && !last_si_clk && si_clk; end - // Data register and shifter + // Data falling/rising event generator - logic [80:0] trx_data; - logic rx_shift; - logic tx_shift; + logic last_si_dq_in; - always_comb begin - si.rx_data = trx_data; - end - - always_ff @(posedge sys.clk) begin - if (si.tx_wmask[0]) trx_data[80:49] <= si.tx_data; - if (si.tx_wmask[1]) trx_data[48:17] <= si.tx_data; - if (si.tx_wmask[2]) trx_data[16:0] <= si.tx_data[16:0]; - - if (rx_shift || tx_shift) begin - trx_data <= {trx_data[79:0], rx_sub_bit_counter < 2'd2}; + always_ff @(posedge clk) begin + if (si_clk_rising_edge) begin + last_si_dq_in <= si_dq_in; end end + logic si_dq_falling_edge; + logic si_dq_rising_edge; + + always_comb begin + si_dq_falling_edge = si_clk_rising_edge && last_si_dq_in && !si_dq_in; + si_dq_rising_edge = si_clk_rising_edge && !last_si_dq_in && si_dq_in; + end + + + // RX bit generator + + logic [3:0] rx_sub_bit_counter; + logic rx_timeout; + logic rx_bit_valid; + logic rx_bit_data; + + always_ff @(posedge clk) begin + if (si_clk_rising_edge && !(&rx_sub_bit_counter)) begin + rx_sub_bit_counter <= rx_sub_bit_counter + 1'd1; + end + if (si_dq_falling_edge) begin + rx_sub_bit_counter <= 4'd0; + end + end + + always_comb begin + rx_timeout = si_clk_rising_edge && si_dq_in && (&rx_sub_bit_counter); + rx_bit_valid = si_dq_rising_edge; + rx_bit_data = (rx_sub_bit_counter >= 4'd3) ? 1'b0 : 1'b1; + end + + + // RX byte generator + + logic [2:0] rx_bit_counter; + logic rx_byte_valid; + logic [7:0] rx_byte_data; + + always_ff @(posedge clk) begin + rx_byte_valid <= 1'b0; + if (rx_timeout) begin + rx_bit_counter <= 3'd0; + end + if (rx_bit_valid) begin + rx_bit_counter <= rx_bit_counter + 1'd1; + rx_byte_data <= {rx_byte_data[6:0], rx_bit_data}; + if (&rx_bit_counter) begin + rx_byte_valid <= 1'b1; + end + end + end + + + // RX stop generator + + logic rx_stop; + + always_comb begin + rx_stop = si_clk_rising_edge && si_dq_in && (rx_sub_bit_counter == 4'd7) && (rx_bit_counter == 3'd1); + end + + + // TX byte/stop generator + + logic tx_busy; + logic [2:0] tx_sub_bit_counter; + logic [2:0] tx_bit_counter; + logic [7:0] tx_shift; + logic tx_start; + logic tx_stop; + logic tx_byte_valid; + logic [7:0] tx_byte_data; + + always_ff @(posedge clk) begin + if (reset) begin + si_dq_out <= 1'b1; + tx_busy <= 1'b0; + end else begin + if (tx_busy) begin + if (si_clk_falling_edge) begin + tx_sub_bit_counter <= tx_sub_bit_counter + 1'd1; + if (&tx_sub_bit_counter) begin + tx_bit_counter <= tx_bit_counter + 1'd1; + tx_shift <= {tx_shift[6:0], 1'bX}; + if (&tx_bit_counter) begin + tx_busy <= 1'b0; + end + end + if (tx_shift[7]) begin + si_dq_out <= !(tx_sub_bit_counter < 3'd2); + end else begin + si_dq_out <= !(tx_sub_bit_counter < 3'd6); + end + end + end else begin + if (tx_byte_valid) begin + tx_busy <= 1'b1; + tx_sub_bit_counter <= 3'd0; + tx_bit_counter <= 3'd0; + tx_shift <= tx_byte_data; + end else if (tx_stop) begin + tx_busy <= 1'b1; + tx_sub_bit_counter <= 3'd0; + tx_bit_counter <= 3'd7; + tx_shift <= 8'hFF; + end + end + end + end + + + // Joybus CMDs + + typedef enum bit [7:0] { + CMD_EEPROM_STATUS = 8'h00, + CMD_EEPROM_READ = 8'h04, + CMD_EEPROM_WRITE = 8'h05, + CMD_RTC_STATUS = 8'h06, + CMD_RTC_READ = 8'h07, + CMD_RTC_WRITE = 8'h08 + } e_cmd; + + e_cmd cmd; + // RX path - typedef enum bit [0:0] { - S_RX_IDLE, - S_RX_WAITING + typedef enum bit [1:0] { + RX_STATE_IDLE, + RX_STATE_DATA, + RX_STATE_IGNORE } e_rx_state; e_rx_state rx_state; + logic [3:0] rx_byte_counter; + logic rx_data_valid; - logic [1:0] rx_sub_bit_counter; - logic [3:0] rx_timeout_counter; + always_comb begin + rx_data_valid = rx_byte_valid && (rx_state == RX_STATE_DATA); + end - always_ff @(posedge sys.clk) begin - rx_shift <= 1'b0; + always_ff @(posedge clk) begin + tx_start <= 1'b0; - if (si_clk_rising_edge) begin - if (rx_timeout_counter < 4'd8) begin - rx_timeout_counter <= rx_timeout_counter + 1'd1; - end else if (si.rx_length > 7'd0) begin - si.rx_ready <= 1'b1; - end + if (rx_byte_valid) begin + rx_byte_counter <= rx_byte_counter + 1'd1; end - if (sys.reset || si.rx_reset) begin - rx_state <= S_RX_IDLE; - si.rx_ready <= 1'b0; - si.rx_length <= 7'd0; - end else if (!si.tx_busy) begin + if (reset || rx_timeout) begin + rx_state <= RX_STATE_IDLE; + end else begin case (rx_state) - S_RX_IDLE: begin - if (si_clk_rising_edge && !si_dq) begin - rx_state <= S_RX_WAITING; - rx_sub_bit_counter <= 2'd0; - rx_timeout_counter <= 3'd0; + RX_STATE_IDLE: begin + if (rx_byte_valid) begin + cmd <= e_cmd'(rx_byte_data); + rx_byte_counter <= 4'd0; + rx_state <= RX_STATE_IGNORE; + case (rx_byte_data) + CMD_EEPROM_STATUS, + CMD_EEPROM_READ, + CMD_EEPROM_WRITE: begin + rx_state <= n64_scb.eeprom_enabled ? RX_STATE_DATA : RX_STATE_IGNORE; + end + CMD_RTC_STATUS, + CMD_RTC_READ, + CMD_RTC_WRITE: begin + rx_state <= RX_STATE_DATA; + end + endcase end end - S_RX_WAITING: begin - if (si_clk_rising_edge) begin - if (si_dq) begin - rx_state <= S_RX_IDLE; - rx_shift <= 1'b1; - si.rx_length <= si.rx_length + 1'd1; - end else if (rx_sub_bit_counter < 2'd3) begin - rx_sub_bit_counter <= rx_sub_bit_counter + 1'd1; - end + RX_STATE_DATA: begin + if (rx_stop) begin + tx_start <= 1'b1; + rx_state <= RX_STATE_IGNORE; + end + end + + RX_STATE_IGNORE: begin + if (rx_stop) begin + rx_state <= RX_STATE_IDLE; end end endcase @@ -168,57 +257,217 @@ module n64_si ( // TX path - typedef enum bit [0:0] { - S_TX_IDLE, - S_TX_SENDING + typedef enum bit [1:0] { + TX_STATE_IDLE, + TX_STATE_DATA, + TX_STATE_STOP } e_tx_state; e_tx_state tx_state; - logic [2:0] tx_sub_bit_counter; - logic [6:0] tx_bit_counter; + logic [3:0] tx_byte_counter; + logic [3:0] tx_length; - always_ff @(posedge sys.clk) begin - tx_shift <= 1'b0; + always_ff @(posedge clk) begin + tx_byte_valid <= 1'b0; + tx_stop <= 1'b0; - if (sys.reset || si.tx_reset) begin - tx_state <= S_TX_IDLE; - si_dq_output_enable_data <= 1'b0; - si.tx_busy <= 1'b0; + if (!tx_busy && tx_byte_valid) begin + tx_byte_counter <= tx_byte_counter + 1'd1; + end + + if (reset) begin + tx_state <= TX_STATE_IDLE; end else begin case (tx_state) - S_TX_IDLE: begin - if (si.tx_start) begin - tx_state <= S_TX_SENDING; - tx_sub_bit_counter <= 3'd0; - tx_bit_counter <= si.tx_length; - si.tx_busy <= 1'b1; + TX_STATE_IDLE: begin + if (tx_start) begin + tx_byte_counter <= 4'd0; + tx_state <= TX_STATE_DATA; end end - S_TX_SENDING: begin - if (si_clk_falling_edge) begin - tx_sub_bit_counter <= tx_sub_bit_counter + 1'd1; - if (tx_sub_bit_counter == 3'd7) begin - tx_shift <= 1'b1; - if (tx_bit_counter >= 7'd1) begin - tx_bit_counter <= tx_bit_counter - 1'd1; - end else begin - tx_state <= S_TX_IDLE; - si.tx_busy <= 1'b0; - end - end - if (tx_bit_counter == 7'd0) begin - si_dq_output_enable_data <= tx_sub_bit_counter < 3'd4; - end else if (trx_data[80]) begin - si_dq_output_enable_data <= tx_sub_bit_counter < 3'd2; - end else begin - si_dq_output_enable_data <= tx_sub_bit_counter < 3'd6; + TX_STATE_DATA: begin + tx_byte_valid <= 1'b1; + if (!tx_busy && tx_byte_valid) begin + if (tx_byte_counter == tx_length) begin + tx_state <= TX_STATE_STOP; end end end + + TX_STATE_STOP: begin + tx_stop <= 1'b1; + if (!tx_busy && tx_stop) begin + tx_state <= TX_STATE_IDLE; + end + end endcase end end + + // Joybus address latching + + logic [7:0] joybus_address; + logic [2:0] joybus_subaddress; + logic [10:0] joybus_full_address; + + always_comb begin + joybus_full_address = {joybus_address, joybus_subaddress}; + end + + always_ff @(posedge clk) begin + if (rx_data_valid || (!tx_busy && tx_byte_valid)) begin + joybus_subaddress <= joybus_subaddress + 1'd1; + end + if (rx_data_valid) begin + if (rx_byte_counter == 4'd0) begin + joybus_address <= rx_byte_data; + joybus_subaddress <= 3'd0; + end + end + end + + + // EEPROM controller + + always_comb begin + n64_scb.eeprom_write = rx_data_valid && (cmd == CMD_EEPROM_WRITE) && rx_byte_counter > 4'd0; + n64_scb.eeprom_address = joybus_full_address; + n64_scb.eeprom_wdata = rx_byte_data; + end + + + // RTC controller + + logic rtc_backup_wp; + logic rtc_time_wp; + logic [1:0] rtc_stopped; + logic [6:0] rtc_time_second; + logic [6:0] rtc_time_minute; + logic [5:0] rtc_time_hour; + logic [5:0] rtc_time_day; + logic [2:0] rtc_time_weekday; + logic [4:0] rtc_time_month; + logic [7:0] rtc_time_year; + + always_ff @(posedge clk) begin + if (reset) begin + rtc_backup_wp <= 1'b1; + rtc_time_wp <= 1'b1; + rtc_stopped <= 2'b00; + n64_scb.rtc_pending <= 1'b0; + end + + if (n64_scb.rtc_done) begin + n64_scb.rtc_pending <= 1'b0; + end + + if (!(|rtc_stopped) && !n64_scb.rtc_pending && n64_scb.rtc_wdata_valid && (tx_state != TX_STATE_DATA)) begin + { + rtc_time_year, + rtc_time_month, + rtc_time_weekday, + rtc_time_day, + rtc_time_hour, + rtc_time_minute, + rtc_time_second + } <= n64_scb.rtc_wdata; + end + + if (rx_data_valid && (cmd == CMD_RTC_WRITE)) begin + if (joybus_address[1:0] == 2'd0) begin + case (rx_byte_counter) + 4'd1: {rtc_time_wp, rtc_backup_wp} <= rx_byte_data[1:0]; + 4'd2: begin + rtc_stopped <= rx_byte_data[2:1]; + if (rx_byte_data[2:1] == 2'b00) begin + n64_scb.rtc_pending <= 1'b1; + end + end + endcase + end + if ((joybus_address[1:0] == 2'd2) && !rtc_time_wp) begin + case (rx_byte_counter) + 4'd1: rtc_time_second <= rx_byte_data[6:0]; + 4'd2: rtc_time_minute <= rx_byte_data[6:0]; + 4'd3: rtc_time_hour <= rx_byte_data[5:0]; + 4'd4: rtc_time_day <= rx_byte_data[5:0]; + 4'd5: rtc_time_weekday <= rx_byte_data[2:0]; + 4'd6: rtc_time_month <= rx_byte_data[4:0]; + 4'd7: rtc_time_year <= rx_byte_data; + endcase + end + end + end + + always_comb begin + n64_scb.rtc_rdata = { + rtc_time_year, + rtc_time_month, + rtc_time_weekday, + rtc_time_day, + rtc_time_hour, + rtc_time_minute, + rtc_time_second + }; + end + + + // TX data multiplexer + + always_comb begin + tx_length = 4'd0; + tx_byte_data = 8'h00; + case (cmd) + CMD_EEPROM_STATUS: begin + tx_length = 4'd2; + case (tx_byte_counter) + 4'd1: tx_byte_data = {1'b1, n64_scb.eeprom_16k_mode, 6'd0}; + endcase + end + CMD_EEPROM_READ: begin + tx_length = 4'd7; + tx_byte_data = n64_scb.eeprom_rdata; + end + CMD_EEPROM_WRITE: begin + tx_length = 4'd0; + end + CMD_RTC_STATUS: begin + tx_length = 4'd2; + case (tx_byte_counter) + 4'd1: tx_byte_data = 8'h10; + 4'd2: tx_byte_data = {(|rtc_stopped), 7'd0}; + endcase + end + CMD_RTC_READ: begin + tx_length = 4'd8; + if (joybus_address[1:0] == 2'd0) begin + case (tx_byte_counter) + 4'd0: tx_byte_data = {6'd0, rtc_time_wp, rtc_backup_wp}; + 4'd1: tx_byte_data = {5'd0, rtc_stopped, 1'b0}; + 4'd8: tx_byte_data = {(|rtc_stopped), 7'd0}; + endcase + end else if (joybus_address[1:0] == 2'd2) begin + case (tx_byte_counter) + 4'd0: tx_byte_data = {1'd0, rtc_time_second}; + 4'd1: tx_byte_data = {1'd0, rtc_time_minute}; + 4'd2: tx_byte_data = {2'b10, rtc_time_hour}; + 4'd3: tx_byte_data = {2'd0, rtc_time_day}; + 4'd4: tx_byte_data = {5'd0, rtc_time_weekday}; + 4'd5: tx_byte_data = {3'd0, rtc_time_month}; + 4'd6: tx_byte_data = rtc_time_year; + 4'd7: tx_byte_data = 8'h01; + 4'd8: tx_byte_data = {(|rtc_stopped), 7'd0}; + endcase + end + end + CMD_RTC_WRITE: begin + tx_length = 4'd0; + tx_byte_data = {(|rtc_stopped), 7'd0}; + end + endcase + end + endmodule diff --git a/fw/rtl/n64/n64_soc.sv b/fw/rtl/n64/n64_soc.sv deleted file mode 100644 index 2f1a1a4..0000000 --- a/fw/rtl/n64/n64_soc.sv +++ /dev/null @@ -1,96 +0,0 @@ -module n64_soc ( - if_system sys, - if_config cfg, - if_dma.memory dma, - if_sdram.memory sdram, - if_flashram.flashram flashram, - if_si.si si, - if_flash.memory flash, - if_dd dd, - - input n64_pi_alel, - input n64_pi_aleh, - input n64_pi_read, - input n64_pi_write, - inout [15:0] n64_pi_ad, - - input n64_si_clk, - inout n64_si_dq, - - output sdram_cs, - output sdram_ras, - output sdram_cas, - output sdram_we, - output [1:0] sdram_ba, - output [12:0] sdram_a, - inout [15:0] sdram_dq -); - - if_n64_bus bus (); - - n64_pi n64_pi_inst ( - .sys(sys), - .cfg(cfg), - .bus(bus), - - .n64_pi_alel(n64_pi_alel), - .n64_pi_aleh(n64_pi_aleh), - .n64_pi_read(n64_pi_read), - .n64_pi_write(n64_pi_write), - .n64_pi_ad(n64_pi_ad) - ); - - n64_si n64_si_inst ( - .sys(sys), - .si(si), - - .n64_si_clk(n64_si_clk), - .n64_si_dq(n64_si_dq) - ); - - n64_sdram n64_sdram_inst ( - .sys(sys), - .bus(bus.at[sc64::ID_N64_SDRAM].device), - .dma(dma), - .sdram(sdram), - - .sdram_cs(sdram_cs), - .sdram_ras(sdram_ras), - .sdram_cas(sdram_cas), - .sdram_we(sdram_we), - .sdram_ba(sdram_ba), - .sdram_a(sdram_a), - .sdram_dq(sdram_dq) - ); - - n64_bootloader n64_bootloader_inst ( - .sys(sys), - .bus(bus.at[sc64::ID_N64_BOOTLOADER].device), - .flash(flash) - ); - - n64_flashram n64_flashram_inst ( - .sys(sys), - .bus(bus.at[sc64::ID_N64_FLASHRAM].device), - .cfg(cfg), - .flashram(flashram) - ); - - n64_dd n64_dd_inst ( - .sys(sys), - .bus(bus.at[sc64::ID_N64_DD].device), - .dd(dd) - ); - - n64_dd_sector_buffer n64_dd_sector_buffer_inst ( - .sys(sys), - .dd(dd) - ); - - n64_cfg n64_cfg_inst ( - .sys(sys), - .bus(bus.at[sc64::ID_N64_CFG].device), - .cfg(cfg) - ); - -endmodule diff --git a/fw/rtl/n64/n64_top.sv b/fw/rtl/n64/n64_top.sv new file mode 100644 index 0000000..0191115 --- /dev/null +++ b/fw/rtl/n64/n64_top.sv @@ -0,0 +1,97 @@ +module n64_top ( + input clk, + input reset, + + n64_scb n64_scb, + dd_scb.dd dd_scb, + + mem_bus.controller mem_bus, + + input n64_reset, + input n64_nmi, + output n64_irq, + + input n64_pi_alel, + input n64_pi_aleh, + input n64_pi_read, + input n64_pi_write, + inout [15:0] n64_pi_ad, + + input n64_si_clk, + inout n64_si_dq +); + + logic n64_dd_irq; + logic n64_cfg_irq; + logic n64_irq_oe; + + always @(posedge clk) begin + n64_irq_oe <= (n64_dd_irq || n64_cfg_irq); + end + + assign n64_irq = n64_irq_oe ? 1'b0 : 1'bZ; + + n64_reg_bus reg_bus (); + + n64_pi n64_pi_inst ( + .clk(clk), + .reset(reset), + + .mem_bus(mem_bus), + .reg_bus(reg_bus), + + .n64_scb(n64_scb), + + .n64_reset(n64_reset), + .n64_nmi(n64_nmi), + .n64_pi_alel(n64_pi_alel), + .n64_pi_aleh(n64_pi_aleh), + .n64_pi_read(n64_pi_read), + .n64_pi_write(n64_pi_write), + .n64_pi_ad(n64_pi_ad) + ); + + n64_dd n64_dd_inst ( + .clk(clk), + .reset(reset), + + .reg_bus(reg_bus), + + .n64_scb(n64_scb), + .dd_scb(dd_scb), + + .irq(n64_dd_irq) + ); + + n64_flashram n64_flashram_inst ( + .clk(clk), + .reset(reset), + + .reg_bus(reg_bus), + + .n64_scb(n64_scb) + ); + + n64_cfg n64_cfg_inst ( + .clk(clk), + .reset(reset), + + .reg_bus(reg_bus), + + .n64_scb(n64_scb), + + .irq(n64_cfg_irq) + ); + + n64_si n64_si_inst ( + .clk(clk), + .reset(reset), + + .n64_scb(n64_scb), + + .n64_reset(n64_reset), + .n64_si_clk(n64_si_clk), + .n64_si_dq(n64_si_dq) + ); + +endmodule diff --git a/fw/rtl/sd/sd_clk.sv b/fw/rtl/sd/sd_clk.sv new file mode 100644 index 0000000..7ceceef --- /dev/null +++ b/fw/rtl/sd/sd_clk.sv @@ -0,0 +1,48 @@ +module sd_clk ( + input clk, + input reset, + + sd_scb.clk sd_scb, + + output logic sd_clk_rising, + output logic sd_clk_falling, + + output logic sd_clk +); + + logic [7:0] clock_divider; + + always_ff @(posedge clk) begin + if (!sd_scb.clock_stop) begin + clock_divider <= clock_divider + 1'd1; + end + end + + logic selected_clock; + + always_comb begin + selected_clock = 1'b0; + case (sd_scb.clock_mode) + 2'd0: selected_clock = 1'b0; + 2'd1: selected_clock = clock_divider[7]; + 2'd2: selected_clock = clock_divider[1]; + 2'd3: selected_clock = clock_divider[0]; + endcase + end + + logic last_selected_clock; + + always_ff @(posedge clk) begin + last_selected_clock <= selected_clock; + end + + always_comb begin + sd_clk_rising = !last_selected_clock && selected_clock; + sd_clk_falling = last_selected_clock && !selected_clock; + end + + always_ff @(posedge clk) begin + sd_clk <= last_selected_clock; + end + +endmodule diff --git a/fw/rtl/sd/sd_cmd.sv b/fw/rtl/sd/sd_cmd.sv new file mode 100644 index 0000000..e668c5c --- /dev/null +++ b/fw/rtl/sd/sd_cmd.sv @@ -0,0 +1,231 @@ +module sd_cmd ( + input clk, + input reset, + + sd_scb.cmd sd_scb, + + input sd_clk_rising, + input sd_clk_falling, + + inout sd_cmd +); + + // Input and output data sampling + + logic sd_cmd_oe; + logic sd_cmd_out; + logic sd_cmd_in; + logic sd_cmd_oe_data; + logic sd_cmd_data; + + assign sd_cmd = sd_cmd_oe ? sd_cmd_out : 1'bZ; + + always_ff @(posedge clk) begin + sd_cmd_oe <= sd_cmd_oe_data; + sd_cmd_out <= sd_cmd_data; + sd_cmd_in <= sd_cmd; + end + + + // CMD state + + typedef enum bit [1:0] { + STATE_IDLE, + STATE_TX, + STATE_WAIT, + STATE_RX + } e_state; + + e_state state; + e_state next_state; + + always_ff @(posedge clk) begin + if (reset) begin + state <= STATE_IDLE; + end else begin + state <= next_state; + end + end + + assign sd_scb.cmd_busy = (state != STATE_IDLE); + + logic [7:0] counter; + + always_comb begin + next_state = state; + + case (state) + STATE_IDLE: begin + if (sd_scb.cmd_start) begin + next_state = STATE_TX; + end + end + + STATE_TX: begin + if (sd_clk_falling) begin + if (counter == 8'd48) begin + if (sd_scb.cmd_skip_response) begin + next_state = STATE_IDLE; + end else begin + next_state = STATE_WAIT; + end + end + end + end + + STATE_WAIT: begin + if (sd_clk_rising) begin + if (counter == 8'd64) begin + next_state = STATE_IDLE; + end + if (!sd_cmd_in) begin + next_state = STATE_RX; + end + end + end + + STATE_RX: begin + if (sd_clk_rising) begin + if (sd_scb.cmd_long_response) begin + if (counter == 8'd136) begin + next_state = STATE_IDLE; + end + end else begin + if (counter == 8'd48) begin + next_state = STATE_IDLE; + end + end + end + end + + default: begin + next_state = STATE_IDLE; + end + endcase + end + + + // CRC7 unit + + logic crc_reset; + logic crc_enable; + logic crc_data; + logic [6:0] crc_result; + + sd_crc_7 sd_crc_7_inst ( + .clk(clk), + .reset(crc_reset), + .enable(crc_enable), + .data(crc_data), + .result(crc_result) + ); + + + // Data shifting + + logic [7:0] data_shift; + + assign crc_data = (state == STATE_RX) ? data_shift[0] : data_shift[7]; + + always_ff @(posedge clk) begin + crc_reset <= 1'b0; + crc_enable <= 1'b0; + + if (reset) begin + sd_cmd_oe_data <= 1'b0; + sd_cmd_data <= 1'b1; + end else begin + case (state) + STATE_IDLE: begin + if (sd_scb.cmd_start) begin + sd_scb.cmd_error <= 1'b0; + crc_reset <= 1'b1; + data_shift <= {2'b01, sd_scb.cmd_index}; + counter <= 8'd0; + end + end + + STATE_TX: begin + if (sd_clk_falling) begin + sd_cmd_oe_data <= 1'b1; + sd_cmd_data <= data_shift[7]; + counter <= counter + 1'd1; + crc_enable <= 1'b1; + data_shift <= {data_shift[6:0], 1'bX}; + if (counter == 8'd7) begin + data_shift <= sd_scb.cmd_arg[31:24]; + end + if (counter == 8'd15) begin + data_shift <= sd_scb.cmd_arg[23:16]; + end + if (counter == 8'd23) begin + data_shift <= sd_scb.cmd_arg[15:8]; + end + if (counter == 8'd31) begin + data_shift <= sd_scb.cmd_arg[7:0]; + end + if (counter == 8'd39) begin + data_shift <= {crc_result, 1'b1}; + end + if (counter == 8'd48) begin + sd_cmd_oe_data <= 1'b0; + counter <= 8'd0; + end + end + end + + STATE_WAIT: begin + if (sd_clk_rising) begin + counter <= counter + 1'd1; + if (counter == 8'd64) begin + sd_scb.cmd_error <= 1'b1; + end + if (!sd_cmd_in) begin + counter <= 8'd1; + crc_reset <= 1'b1; + data_shift <= 8'h00; + end + end + end + + STATE_RX: begin + if (sd_clk_rising) begin + counter <= counter + 1'd1; + data_shift <= {data_shift[6:0], sd_cmd_in}; + if (counter == 8'd8) begin + if (data_shift[6:0] != (sd_scb.cmd_reserved_response ? 7'h3F : {1'b0, sd_scb.cmd_index})) begin + sd_scb.cmd_error <= 1'b1; + end + end + if (sd_scb.cmd_long_response) begin + if (counter >= 8'd8 && counter < 8'd128) begin + crc_enable <= 1'b1; + end + if (counter[2:0] == 3'd0) begin + sd_scb.cmd_rsp <= {sd_scb.cmd_rsp[119:0], data_shift}; + end + if (!sd_scb.cmd_ignore_crc && counter == 8'd136) begin + if (data_shift[7:1] != crc_result) begin + sd_scb.cmd_error <= 1'b1; + end + end + end else begin + if (counter < 8'd40) begin + crc_enable <= 1'b1; + end + if (counter <= 8'd40 && counter[2:0] == 3'd0) begin + sd_scb.cmd_rsp <= {sd_scb.cmd_rsp[119:0], data_shift}; + end + if (!sd_scb.cmd_ignore_crc && counter == 8'd48) begin + if (data_shift[7:1] != crc_result) begin + sd_scb.cmd_error <= 1'b1; + end + end + end + end + end + endcase + end + end + +endmodule diff --git a/fw/rtl/sd/sd_crc_16.sv b/fw/rtl/sd/sd_crc_16.sv new file mode 100644 index 0000000..77fe8be --- /dev/null +++ b/fw/rtl/sd/sd_crc_16.sv @@ -0,0 +1,33 @@ +module sd_crc_16 ( + input clk, + input reset, + + input enable, + input shift, + input data, + + output logic [15:0] result +); + + logic crc_inv; + + assign crc_inv = result[15] ^ data; + + always_ff @(posedge clk) begin + if (reset) begin + result <= 16'd0; + end else if (enable) begin + result <= { + result[14:12], + result[11] ^ crc_inv, + result[10:5], + result[4] ^ crc_inv, + result[3:0], + crc_inv + }; + end else if (shift) begin + result <= {result[14:0], 1'b1}; + end + end + +endmodule diff --git a/fw/rtl/sd/sd_crc_7.sv b/fw/rtl/sd/sd_crc_7.sv new file mode 100644 index 0000000..bfee1a8 --- /dev/null +++ b/fw/rtl/sd/sd_crc_7.sv @@ -0,0 +1,28 @@ +module sd_crc_7 ( + input clk, + input reset, + + input enable, + input data, + + output logic [6:0] result +); + + logic crc_inv; + + assign crc_inv = result[6] ^ data; + + always_ff @(posedge clk) begin + if (reset) begin + result <= 7'd0; + end else if (enable) begin + result <= { + result[5:3], + result[2] ^ crc_inv, + result[1:0], + crc_inv + }; + end + end + +endmodule diff --git a/fw/rtl/sd/sd_dat.sv b/fw/rtl/sd/sd_dat.sv new file mode 100644 index 0000000..419efa8 --- /dev/null +++ b/fw/rtl/sd/sd_dat.sv @@ -0,0 +1,373 @@ +module sd_dat ( + input clk, + input reset, + + sd_scb.dat sd_scb, + + fifo_bus.fifo fifo_bus, + + input sd_clk_rising, + input sd_clk_falling, + + inout [3:0] sd_dat +); + + // Input and output data sampling + + logic sd_dat_oe; + logic [3:0] sd_dat_out; + logic [3:0] sd_dat_in; + logic sd_dat_oe_data; + logic [3:0] sd_dat_data; + + assign sd_dat = sd_dat_oe ? sd_dat_out : 4'hZ; + + always_ff @(posedge clk) begin + sd_dat_oe <= sd_dat_oe_data; + sd_dat_out <= sd_dat_data; + sd_dat_in <= sd_dat; + end + + always_ff @(posedge clk) begin + sd_scb.card_busy <= !sd_dat_in[0]; + end + + + // FIFO + + logic rx_full; + logic rx_almost_full; + logic rx_write; + logic [7:0] rx_wdata; + + logic tx_empty; + logic tx_almost_empty; + logic tx_read; + logic [7:0] tx_rdata; + + fifo_8kb fifo_8kb_rx_inst ( + .clk(clk), + .reset(reset || sd_scb.dat_fifo_flush), + + .empty(fifo_bus.rx_empty), + .almost_empty(fifo_bus.rx_almost_empty), + .read(fifo_bus.rx_read), + .rdata(fifo_bus.rx_rdata), + + .full(rx_full), + .almost_full(rx_almost_full), + .write(rx_write), + .wdata(rx_wdata), + + .count(sd_scb.rx_count) + ); + + fifo_8kb fifo_8kb_tx_inst ( + .clk(clk), + .reset(reset || sd_scb.dat_fifo_flush), + + .empty(tx_empty), + .almost_empty(tx_almost_empty), + .read(tx_read), + .rdata(tx_rdata), + + .full(fifo_bus.tx_full), + .almost_full(fifo_bus.tx_almost_full), + .write(fifo_bus.tx_write), + .wdata(fifo_bus.tx_wdata), + + .count(sd_scb.tx_count) + ); + + + // DAT state + + typedef enum bit [2:0] { + STATE_IDLE, + STATE_RX_WAIT, + STATE_RX, + STATE_TX_WAIT, + STATE_TX, + STATE_TX_STATUS_WAIT, + STATE_TX_STATUS + } e_state; + + e_state state; + e_state next_state; + + always_ff @(posedge clk) begin + if (reset || sd_scb.dat_stop) begin + state <= STATE_IDLE; + end else begin + state <= next_state; + end + end + + assign sd_scb.dat_busy = (state != STATE_IDLE); + + logic [10:0] counter; + logic [7:0] blocks_remaining; + + always_comb begin + next_state = state; + + case (state) + STATE_IDLE: begin + if (sd_scb.dat_start_read) begin + next_state = STATE_RX_WAIT; + end + if (sd_scb.dat_start_write) begin + next_state = STATE_TX_WAIT; + end + end + + STATE_RX_WAIT: begin + if (sd_clk_rising) begin + if (!sd_dat_in[0]) begin + next_state = STATE_RX; + end + end + end + + STATE_RX: begin + if (sd_clk_rising) begin + if (counter == 11'd1041) begin + if (blocks_remaining == 8'd0) begin + next_state = STATE_IDLE; + end else begin + next_state = STATE_RX_WAIT; + end + end + end + end + + STATE_TX_WAIT: begin + if (sd_clk_falling) begin + if (sd_scb.tx_count >= 11'd512) begin + next_state = STATE_TX; + end + end + end + + STATE_TX: begin + if (sd_clk_falling) begin + if (counter == 11'd1042) begin + next_state = STATE_TX_STATUS_WAIT; + end + end + end + + STATE_TX_STATUS_WAIT: begin + if (sd_clk_rising) begin + if (counter == 11'd8) begin + next_state = STATE_IDLE; + end else if (!sd_dat_in[0]) begin + next_state = STATE_TX_STATUS; + end + end + end + + STATE_TX_STATUS: begin + if (sd_clk_rising) begin + if (counter == 11'd5) begin + if (sd_dat_in[0]) begin + if (blocks_remaining == 8'd0) begin + next_state = STATE_IDLE; + end else begin + next_state = STATE_TX_WAIT; + end + end + end + end + end + endcase + end + + + // CRC16 units + + logic crc_reset; + logic crc_enable; + logic crc_shift; + logic [3:0] crc_data; + logic [15:0] crc_result [0:3]; + + sd_crc_16 sd_crc_16_inst_0 ( + .clk(clk), + .reset(crc_reset), + .enable(crc_enable), + .shift(crc_shift), + .data(crc_data[0]), + .result(crc_result[0]) + ); + + sd_crc_16 sd_crc_16_inst_1 ( + .clk(clk), + .reset(crc_reset), + .enable(crc_enable), + .shift(crc_shift), + .data(crc_data[1]), + .result(crc_result[1]) + ); + + sd_crc_16 sd_crc_16_inst_2 ( + .clk(clk), + .reset(crc_reset), + .enable(crc_enable), + .shift(crc_shift), + .data(crc_data[2]), + .result(crc_result[2]) + ); + + sd_crc_16 sd_crc_16_inst_3 ( + .clk(clk), + .reset(crc_reset), + .enable(crc_enable), + .shift(crc_shift), + .data(crc_data[3]), + .result(crc_result[3]) + ); + + + // Data shifting + + logic [7:0] data_shift; + logic tx_rdata_valid; + + assign crc_data = (state == STATE_RX) ? rx_wdata[3:0] : sd_dat_data; + + always_comb begin + tx_read = (state == STATE_TX) && sd_clk_falling && (counter < 11'd1024) && (!counter[0]); + end + + always_ff @(posedge clk) begin + rx_write <= 1'b0; + tx_rdata_valid <= tx_read; + crc_reset <= 1'b0; + crc_enable <= 1'b0; + crc_shift <= 1'b0; + + if (reset || sd_scb.dat_stop) begin + sd_scb.clock_stop <= 1'b0; + sd_dat_oe_data <= 1'b0; + sd_dat_data <= 4'hF; + end else begin + case (state) + STATE_IDLE: begin + if (sd_scb.dat_start_read || sd_scb.dat_start_write) begin + sd_scb.dat_error <= 1'b0; + blocks_remaining <= sd_scb.dat_blocks; + end + end + + STATE_RX_WAIT: begin + if (sd_scb.rx_count <= 11'd512) begin + sd_scb.clock_stop <= 1'b0; + end + if (sd_clk_rising) begin + if (!sd_dat_in[0]) begin + counter <= 11'd1; + crc_reset <= 1'b1; + end + end + end + + STATE_RX: begin + if (sd_clk_rising) begin + counter <= counter + 1'd1; + rx_wdata <= {rx_wdata[3:0], sd_dat_in}; + if (counter <= 11'd1024) begin + crc_enable <= 1'b1; + if (!counter[0]) begin + if (rx_full) begin + sd_scb.dat_error <= 1'b1; + end else begin + rx_write <= 1'b1; + end + end + end else begin + crc_shift <= 1'b1; + if ({crc_result[3][15], crc_result[2][15], crc_result[1][15], crc_result[0][15]} != sd_dat_in) begin + sd_scb.dat_error <= 1'b1; + end + end + if (counter == 11'd1041) begin + if ((blocks_remaining > 8'd0) && (sd_scb.rx_count > 11'd512)) begin + sd_scb.clock_stop <= 1'b1; + end + blocks_remaining <= blocks_remaining - 1'd1; + end + end + end + + STATE_TX_WAIT: begin + if (sd_clk_falling) begin + if (sd_scb.tx_count >= 11'd512) begin + counter <= 11'd0; + end + end + end + + STATE_TX: begin + if (sd_clk_falling) begin + counter <= counter + 1'd1; + if (counter == 11'd0) begin + crc_reset <= 1'b1; + sd_dat_oe_data <= 1'b1; + sd_dat_data <= 4'h0; + end else if (counter <= 11'd1024) begin + crc_enable <= 1'b1; + {sd_dat_data, data_shift} <= {data_shift, 4'h0}; + end else begin + crc_shift <= 1'b1; + sd_dat_data <= {crc_result[3][15], crc_result[2][15], crc_result[1][15], crc_result[0][15]}; + end + if (counter == 11'd1042) begin + sd_dat_oe_data <= 1'b0; + counter <= 11'd0; + end + end + end + + STATE_TX_STATUS_WAIT: begin + if (sd_clk_rising) begin + counter <= counter + 1'd1; + if (counter == 11'd8) begin + sd_scb.dat_error <= 1'b1; + end else if (!sd_dat_in[0]) begin + counter <= 11'd1; + end + end + end + + STATE_TX_STATUS: begin + if (sd_clk_rising) begin + if (counter < 11'd5) begin + counter <= counter + 1'd1; + end + if ((counter == 11'd1) && (sd_dat_in[0] != 1'b0)) begin + sd_scb.dat_error <= 1'b1; + end + if ((counter == 11'd2) && (sd_dat_in[0] != 1'b1)) begin + sd_scb.dat_error <= 1'b1; + end + if ((counter == 11'd3) && (sd_dat_in[0] != 1'b0)) begin + sd_scb.dat_error <= 1'b1; + end + if ((counter == 11'd4) && (sd_dat_in[0] != 1'b1)) begin + sd_scb.dat_error <= 1'b1; + end + if ((counter == 11'd5) && (sd_dat_in[0] == 1'b1)) begin + blocks_remaining <= blocks_remaining - 1'd1; + end + end + end + endcase + end + + if (tx_rdata_valid) begin + data_shift <= tx_rdata; + end + end + +endmodule diff --git a/fw/rtl/sd/sd_scb.sv b/fw/rtl/sd/sd_scb.sv new file mode 100644 index 0000000..369bf71 --- /dev/null +++ b/fw/rtl/sd/sd_scb.sv @@ -0,0 +1,93 @@ +interface sd_scb (); + + logic [1:0] clock_mode; + logic clock_stop; + + logic card_busy; + + logic [10:0] rx_count; + logic [10:0] tx_count; + + logic [5:0] cmd_index; + logic [31:0] cmd_arg; + logic [127:0] cmd_rsp; + logic cmd_start; + logic cmd_skip_response; + logic cmd_reserved_response; + logic cmd_long_response; + logic cmd_ignore_crc; + logic cmd_busy; + logic cmd_error; + + logic dat_fifo_flush; + logic dat_start_write; + logic dat_start_read; + logic dat_stop; + logic [7:0] dat_blocks; + logic dat_busy; + logic dat_error; + + modport controller ( + output clock_mode, + + input card_busy, + + input rx_count, + input tx_count, + + output cmd_index, + output cmd_arg, + input cmd_rsp, + output cmd_start, + output cmd_skip_response, + output cmd_reserved_response, + output cmd_long_response, + output cmd_ignore_crc, + input cmd_busy, + input cmd_error, + + output dat_fifo_flush, + output dat_start_write, + output dat_start_read, + output dat_stop, + output dat_blocks, + input dat_busy, + input dat_error + ); + + modport clk ( + input clock_mode, + input clock_stop + ); + + modport cmd ( + input cmd_index, + input cmd_arg, + output cmd_rsp, + input cmd_start, + input cmd_skip_response, + input cmd_reserved_response, + input cmd_long_response, + input cmd_ignore_crc, + output cmd_busy, + output cmd_error + ); + + modport dat ( + output clock_stop, + + output card_busy, + + output rx_count, + output tx_count, + + input dat_fifo_flush, + input dat_start_write, + input dat_start_read, + input dat_stop, + input dat_blocks, + output dat_busy, + output dat_error + ); + +endinterface diff --git a/fw/rtl/sd/sd_top.sv b/fw/rtl/sd/sd_top.sv new file mode 100644 index 0000000..a5bccde --- /dev/null +++ b/fw/rtl/sd/sd_top.sv @@ -0,0 +1,55 @@ +module sd_top ( + input clk, + input reset, + + sd_scb sd_scb, + + fifo_bus.fifo fifo_bus, + + output sd_clk, + inout sd_cmd, + inout [3:0] sd_dat +); + + logic sd_clk_rising; + logic sd_clk_falling; + + sd_clk sd_clk_inst ( + .clk(clk), + .reset(reset), + + .sd_scb(sd_scb), + + .sd_clk_rising(sd_clk_rising), + .sd_clk_falling(sd_clk_falling), + + .sd_clk(sd_clk) + ); + + sd_cmd sd_cmd_inst ( + .clk(clk), + .reset(reset), + + .sd_scb(sd_scb), + + .sd_clk_rising(sd_clk_rising), + .sd_clk_falling(sd_clk_falling), + + .sd_cmd(sd_cmd) + ); + + sd_dat sd_dat_inst ( + .clk(clk), + .reset(reset), + + .sd_scb(sd_scb), + + .fifo_bus(fifo_bus), + + .sd_clk_rising(sd_clk_rising), + .sd_clk_falling(sd_clk_falling), + + .sd_dat(sd_dat) + ); + +endmodule diff --git a/fw/rtl/system/config.sv b/fw/rtl/system/config.sv deleted file mode 100644 index 4d5ddd0..0000000 --- a/fw/rtl/system/config.sv +++ /dev/null @@ -1,67 +0,0 @@ -interface if_config (); - - logic cpu_ready; - logic cpu_busy; - logic cmd_error; - logic cmd_request; - logic [7:0] cmd; - logic [31:0] data [0:1]; - logic [1:0] data_write; - logic [31:0] wdata; - logic sdram_switch; - logic sdram_writable; - logic dd_enabled; - logic sram_enabled; - logic sram_banked; - logic flashram_enabled; - logic flashram_read_mode; - logic [25:0] ddipl_offset; - logic [25:0] save_offset; - - modport pi ( - input sdram_switch, - input sdram_writable, - input dd_enabled, - input sram_enabled, - input sram_banked, - input flashram_enabled, - input flashram_read_mode, - input ddipl_offset, - input save_offset - ); - - modport flashram ( - output flashram_read_mode - ); - - modport n64 ( - input cpu_ready, - input cpu_busy, - input cmd_error, - output cmd_request, - output cmd, - output data, - input data_write, - input wdata - ); - - modport cpu ( - output cpu_ready, - output cpu_busy, - output cmd_error, - input cmd_request, - input cmd, - input data, - output data_write, - output wdata, - output sdram_switch, - output sdram_writable, - output dd_enabled, - output sram_enabled, - output sram_banked, - output flashram_enabled, - output ddipl_offset, - output save_offset - ); - -endinterface diff --git a/fw/rtl/system/sc64.sv b/fw/rtl/system/sc64.sv deleted file mode 100644 index 9facdb1..0000000 --- a/fw/rtl/system/sc64.sv +++ /dev/null @@ -1,45 +0,0 @@ -package sc64; - - typedef enum bit [2:0] { - ID_N64_SDRAM, - ID_N64_BOOTLOADER, - ID_N64_FLASHRAM, - ID_N64_DD, - ID_N64_CFG, - __ID_N64_END - } e_n64_id; - - typedef enum bit [3:0] { - ID_CPU_RAM, - ID_CPU_FLASH, - ID_CPU_GPIO, - ID_CPU_I2C, - ID_CPU_USB, - ID_CPU_UART, - ID_CPU_DMA, - ID_CPU_CFG, - ID_CPU_SDRAM, - ID_CPU_FLASHRAM, - ID_CPU_SI, - ID_CPU_DD, - __ID_CPU_END - } e_cpu_id; - - typedef enum bit [1:0] { - ID_DMA_USB, - ID_DMA_SD, - __ID_DMA_END - } e_dma_id; - - parameter bit [31:0] SC64_VER = 32'h53437632; - parameter int CLOCK_FREQUENCY = 32'd100_000_000; - parameter bit [31:0] CPU_RESET_VECTOR = {4'(ID_CPU_FLASH), 28'h0035800}; - parameter int UART_BAUD_RATE = 32'd1_000_000; - -`ifdef DEBUG - parameter bit CPU_HAS_UART = 1'b1; -`else - parameter bit CPU_HAS_UART = 1'b0; -`endif - -endpackage diff --git a/fw/rtl/system/system.sv b/fw/rtl/system/system.sv deleted file mode 100644 index a439629..0000000 --- a/fw/rtl/system/system.sv +++ /dev/null @@ -1,62 +0,0 @@ -interface if_system ( - input in_clk, - input n64_reset, - input n64_nmi -); - - logic clk; - logic sdram_clk; - logic reset; - logic n64_soft_reset; - logic n64_hard_reset; - - modport internal ( - input in_clk, - input n64_reset, - input n64_nmi, - output clk, - output sdram_clk, - output reset, - output n64_soft_reset, - output n64_hard_reset - ); - - modport sys ( - input clk, - input reset, - input n64_soft_reset, - input n64_hard_reset - ); - - modport sdram ( - input sdram_clk - ); - -endinterface - - -module system (if_system.internal sys); - - logic locked; - logic [1:0] n64_reset_ff; - logic [1:0] n64_nmi_ff; - - intel_pll intel_pll_inst ( - .inclk0(sys.in_clk), - .c0(sys.clk), - .c1(sys.sdram_clk), - .locked(locked) - ); - - always_ff @(posedge sys.clk) begin - n64_reset_ff <= {n64_reset_ff[0], sys.n64_reset}; - n64_nmi_ff <= {n64_nmi_ff[0], sys.n64_nmi}; - end - - always_comb begin - sys.reset = ~locked; - sys.n64_hard_reset = ~n64_reset_ff[1]; - sys.n64_soft_reset = ~n64_nmi_ff[1]; - end - -endmodule diff --git a/fw/rtl/top.sv b/fw/rtl/top.sv new file mode 100644 index 0000000..293dd9b --- /dev/null +++ b/fw/rtl/top.sv @@ -0,0 +1,267 @@ +module top ( + input inclk, + + input n64_reset, + input n64_nmi, + output n64_irq, + + input n64_pi_alel, + input n64_pi_aleh, + input n64_pi_read, + input n64_pi_write, + inout [15:0] n64_pi_ad, + + input n64_si_clk, + inout n64_si_dq, + + input usb_pwrsav, + output usb_clk, + output usb_cs, + input usb_miso, + inout [7:0] usb_miosi, + + input sd_det, + output sd_clk, + inout sd_cmd, + inout [3:0] sd_dat, + + output sdram_clk, + output sdram_cs, + output sdram_ras, + output sdram_cas, + output sdram_we, + output [1:0] sdram_ba, + output [12:0] sdram_a, + output [1:0] sdram_dqm, + inout [15:0] sdram_dq, + + output flash_clk, + output flash_cs, + inout [3:0] flash_dq, + + input button, + + output mcu_int, + input mcu_clk, + input mcu_cs, + input mcu_mosi, + output mcu_miso +); + + logic clk; + logic reset; + + n64_scb n64_scb (); + dd_scb dd_scb (); + usb_scb usb_scb (); + dma_scb usb_dma_scb (); + sd_scb sd_scb (); + dma_scb sd_dma_scb (); + flash_scb flash_scb (); + vendor_scb vendor_scb (); + + fifo_bus usb_cfg_fifo_bus (); + fifo_bus usb_dma_fifo_bus (); + fifo_bus usb_fifo_bus (); + fifo_bus sd_fifo_bus (); + + mem_bus n64_mem_bus (); + mem_bus cfg_mem_bus (); + mem_bus usb_dma_mem_bus (); + mem_bus sd_dma_mem_bus (); + mem_bus sdram_mem_bus (); + mem_bus flash_mem_bus (); + mem_bus bram_mem_bus (); + + pll pll_inst ( + .inclk(inclk), + .clk(clk), + .sdram_clk(sdram_clk), + .reset(reset) + ); + + + // MCU controller + + mcu_top mcu_top_inst ( + .clk(clk), + .reset(reset), + + .n64_scb(n64_scb), + .dd_scb(dd_scb), + .usb_scb(usb_scb), + .usb_dma_scb(usb_dma_scb), + .sd_scb(sd_scb), + .sd_dma_scb(sd_dma_scb), + .flash_scb(flash_scb), + .vendor_scb(vendor_scb), + + .fifo_bus(usb_cfg_fifo_bus), + .mem_bus(cfg_mem_bus), + + .sd_det(sd_det), + .button(button), + + .mcu_int(mcu_int), + .mcu_clk(mcu_clk), + .mcu_cs(mcu_cs), + .mcu_mosi(mcu_mosi), + .mcu_miso(mcu_miso) + ); + + + // N64 controller + + n64_top n64_top_inst ( + .clk(clk), + .reset(reset), + + .n64_scb(n64_scb), + .dd_scb(dd_scb), + + .mem_bus(n64_mem_bus), + + .n64_reset(n64_reset), + .n64_nmi(n64_nmi), + .n64_irq(n64_irq), + + .n64_pi_alel(n64_pi_alel), + .n64_pi_aleh(n64_pi_aleh), + .n64_pi_read(n64_pi_read), + .n64_pi_write(n64_pi_write), + .n64_pi_ad(n64_pi_ad), + + .n64_si_clk(n64_si_clk), + .n64_si_dq(n64_si_dq) + ); + + + // USB + + usb_ft1248 usb_ft1248_inst ( + .clk(clk), + .reset(reset), + + .usb_scb(usb_scb), + + .fifo_bus(usb_fifo_bus), + + .usb_pwrsav(usb_pwrsav), + .usb_clk(usb_clk), + .usb_cs(usb_cs), + .usb_miso(usb_miso), + .usb_miosi(usb_miosi) + ); + + memory_dma memory_usb_dma_inst ( + .clk(clk), + .reset(reset), + + .dma_scb(usb_dma_scb), + + .fifo_bus(usb_dma_fifo_bus), + .mem_bus(usb_dma_mem_bus) + ); + + fifo_junction usb_fifo_junction_inst ( + .cfg_bus(usb_cfg_fifo_bus), + .dma_bus(usb_dma_fifo_bus), + .dev_bus(usb_fifo_bus) + ); + + + // SD card + + sd_top sd_top_inst ( + .clk(clk), + .reset(reset), + + .sd_scb(sd_scb), + + .fifo_bus(sd_fifo_bus), + + .sd_clk(sd_clk), + .sd_cmd(sd_cmd), + .sd_dat(sd_dat) + ); + + memory_dma memory_sd_dma_inst ( + .clk(clk), + .reset(reset), + + .dma_scb(sd_dma_scb), + + .fifo_bus(sd_fifo_bus), + .mem_bus(sd_dma_mem_bus) + ); + + + // Memory bus arbiter + + memory_arbiter memory_arbiter_inst ( + .clk(clk), + .reset(reset), + + .n64_scb(n64_scb), + + .n64_bus(n64_mem_bus), + .cfg_bus(cfg_mem_bus), + .usb_dma_bus(usb_dma_mem_bus), + .sd_dma_bus(sd_dma_mem_bus), + + .sdram_mem_bus(sdram_mem_bus), + .flash_mem_bus(flash_mem_bus), + .bram_mem_bus(bram_mem_bus) + ); + + + // Memory controllers + + memory_sdram memory_sdram_inst ( + .clk(clk), + .reset(reset), + + .mem_bus(sdram_mem_bus), + + .sdram_cs(sdram_cs), + .sdram_ras(sdram_ras), + .sdram_cas(sdram_cas), + .sdram_we(sdram_we), + .sdram_ba(sdram_ba), + .sdram_a(sdram_a), + .sdram_dqm(sdram_dqm), + .sdram_dq(sdram_dq) + ); + + memory_flash memory_flash_inst ( + .clk(clk), + .reset(reset), + + .flash_scb(flash_scb), + + .mem_bus(flash_mem_bus), + + .flash_clk(flash_clk), + .flash_cs(flash_cs), + .flash_dq(flash_dq) + ); + + memory_bram memory_bram_inst ( + .clk(clk), + + .n64_scb(n64_scb), + + .mem_bus(bram_mem_bus) + ); + + + // Vendor specific control + + vendor vendor_inst ( + .clk(clk), + .reset(reset), + + .vendor_scb(vendor_scb) + ); + +endmodule diff --git a/fw/rtl/usb/usb_ft1248.sv b/fw/rtl/usb/usb_ft1248.sv index 325991e..9b2153b 100644 --- a/fw/rtl/usb/usb_ft1248.sv +++ b/fw/rtl/usb/usb_ft1248.sv @@ -1,261 +1,356 @@ +interface usb_scb (); + + logic fifo_flush; + logic reset_pending; + logic reset_ack; + logic write_buffer_flush; + logic [10:0] rx_count; + logic [10:0] tx_count; + logic pwrsav; + logic reset_state; + + modport controller ( + output fifo_flush, + input reset_pending, + output reset_ack, + output write_buffer_flush, + input rx_count, + input tx_count, + input pwrsav, + input reset_state + ); + + modport usb ( + input fifo_flush, + output reset_pending, + input reset_ack, + input write_buffer_flush, + output rx_count, + output tx_count, + output pwrsav, + output reset_state + ); + +endinterface + + module usb_ft1248 ( - if_system.sys sys, + input clk, + input reset, - input usb_enabled, + usb_scb.usb usb_scb, - output usb_clk, - output usb_cs, + fifo_bus.fifo fifo_bus, + + input usb_pwrsav, + output logic usb_clk, + output logic usb_cs, input usb_miso, - inout [3:0] usb_miosi, - - input rx_flush, - output rx_empty, - input rx_read, - output [7:0] rx_rdata, - - input tx_flush, - output tx_full, - input tx_write, - input [7:0] tx_wdata, - - output rx_escape_valid, - input rx_escape_ack, - output [7:0] rx_escape + inout [7:0] usb_miosi ); - parameter bit [7:0] ESCAPE_CHARACTER = 8'h1B; - - // FIFOs - logic rx_full; + logic rx_almost_full; logic rx_write; logic [7:0] rx_wdata; logic tx_empty; + logic tx_almost_empty; logic tx_read; logic [7:0] tx_rdata; - logic rx_wdata_valid; - logic rx_escape_active; + fifo_8kb fifo_8kb_rx_inst ( + .clk(clk), + .reset(reset || usb_scb.fifo_flush), - intel_fifo_8 fifo_8_rx_inst ( - .clock(sys.clk), - .sclr(rx_flush || !usb_enabled), - - .empty(rx_empty), - .rdreq(rx_read), - .q(rx_rdata), + .empty(fifo_bus.rx_empty), + .almost_empty(fifo_bus.rx_almost_empty), + .read(fifo_bus.rx_read), + .rdata(fifo_bus.rx_rdata), .full(rx_full), - .wrreq(rx_write), - .data(rx_wdata) + .almost_full(rx_almost_full), + .write(rx_write), + .wdata(rx_wdata), + + .count(usb_scb.rx_count) ); - intel_fifo_8 fifo_8_tx_inst ( - .clock(sys.clk), - .sclr(tx_flush || !usb_enabled), + fifo_8kb fifo_8kb_tx_inst ( + .clk(clk), + .reset(reset || usb_scb.fifo_flush), .empty(tx_empty), - .rdreq(tx_read), - .q(tx_rdata), + .almost_empty(tx_almost_empty), + .read(tx_read), + .rdata(tx_rdata), - .full(tx_full), - .wrreq(tx_write), - .data(tx_wdata) + .full(fifo_bus.tx_full), + .almost_full(fifo_bus.tx_almost_full), + .write(fifo_bus.tx_write), + .wdata(fifo_bus.tx_wdata), + + .count(usb_scb.tx_count) ); + logic [1:0] usb_pwrsav_ff; + logic [7:0] usb_miosi_out; + logic usb_oe; - // Escape character detection + logic ft_pwrsav; + logic ft_clk; + logic ft_cs; + logic ft_miso; + logic [7:0] ft_miosi_in; + logic [7:0] ft_miosi_out; + logic ft_oe; - always_comb begin - rx_write = 1'b0; - if (rx_wdata_valid) begin - rx_write = rx_escape_active ? rx_wdata == ESCAPE_CHARACTER : rx_wdata != ESCAPE_CHARACTER; - end + always_ff @(posedge clk) begin + usb_pwrsav_ff <= {usb_pwrsav_ff[0], usb_pwrsav}; + ft_pwrsav <= usb_pwrsav_ff[1]; + usb_clk <= ft_clk; + usb_cs <= ft_cs; + ft_miso <= usb_miso; + ft_miosi_in <= usb_miosi; + usb_miosi_out <= ft_miosi_out; + usb_oe <= ft_oe; end - always_ff @(posedge sys.clk) begin - if (sys.reset || !usb_enabled) begin - rx_escape_valid <= 1'b0; - rx_escape_active <= 1'b0; - end else begin - if (rx_escape_ack) begin - rx_escape_valid <= 1'b0; - end + assign usb_miosi = usb_oe ? usb_miosi_out : 8'hZZ; - if (rx_wdata_valid) begin - if (!rx_escape_active) begin - if (rx_wdata == ESCAPE_CHARACTER) begin - rx_escape_active <= 1'b1; - end - end else begin - rx_escape_active <= 1'b0; - rx_escape <= rx_wdata; - if (rx_wdata != ESCAPE_CHARACTER) begin - rx_escape_valid <= 1'b1; - end - end - end - end - end - - - // FT1248 interface controller - - typedef enum bit [1:0] { - S_TRY_RX, - S_TRY_TX, - S_COMMAND, - S_DATA + typedef enum bit [2:0] { + STATE_IDLE, + STATE_SELECT, + STATE_COMMAND, + STATE_STATUS, + STATE_DATA, + STATE_DESELECT } e_state; typedef enum bit [7:0] { - C_WRITE = 8'h00, - C_READ = 8'h04 - } e_command; - - typedef enum bit [1:0] { - P_PRE_RISING, - P_RISING, - P_PRE_FALLING, - P_FALLING - } e_clock_phase; + CMD_WRITE = 8'h00, + CMD_READ = 8'h40, + CMD_READ_MODEM_STATUS = 8'h20, + CMD_WRITE_MODEM_STATUS = 8'h60, + CMD_WRITE_BUFFER_FLUSH = 8'h08 + } e_cmd; e_state state; + e_state next_state; + e_cmd cmd; + e_cmd next_cmd; + logic [3:0] phase; + logic last_tx_failed; + logic reset_reply; + logic last_reset_status; + logic [4:0] modem_status_counter; + logic write_modem_status_pending; + logic write_buffer_flush_pending; - logic [3:0] clock_phase; + always_ff @(posedge clk) begin + state <= next_state; + cmd <= next_cmd; - logic usb_clk_output; - logic usb_cs_output; - logic [3:0] usb_miosi_input; - logic [3:0] usb_miosi_output; - logic [3:0] usb_miosi_output_data; - logic usb_miosi_output_enable; - logic usb_miosi_output_enable_data; - logic usb_miso_input; + usb_scb.pwrsav <= !ft_pwrsav; + usb_scb.reset_state <= last_reset_status; - logic is_cmd_write; - logic [1:0] nibble_counter; - logic [7:0] tx_buffer; + phase <= {phase[2:0], phase[3]}; + if (state == STATE_IDLE) begin + phase <= 4'b0100; + end - always_ff @(posedge sys.clk) begin - if (sys.reset || state == S_TRY_RX || state == S_TRY_TX) begin - clock_phase <= 4'b0001; + if (reset) begin + last_tx_failed <= 1'b0; + usb_scb.reset_pending <= 1'b0; + last_reset_status <= 1'b0; + modem_status_counter <= 5'd0; + write_modem_status_pending <= 1'b0; + write_buffer_flush_pending <= 1'b0; end else begin - clock_phase <= {clock_phase[2:0], clock_phase[3]}; - end - end + if (usb_scb.reset_ack) begin + usb_scb.reset_pending <= 1'b0; + reset_reply <= 1'b1; + write_modem_status_pending <= 1'b1; + end - always_ff @(posedge sys.clk) begin - usb_clk <= usb_clk_output; - usb_cs <= usb_cs_output; + if (usb_scb.write_buffer_flush) begin + write_buffer_flush_pending <= 1'b1; + end - usb_miosi_input <= usb_miosi; - usb_miosi_output <= usb_miosi_output_data; - usb_miosi_output_enable <= usb_miosi_output_enable_data; - - usb_miso_input <= usb_miso; + if (state == STATE_IDLE) begin + modem_status_counter <= modem_status_counter + 1'd1; + end - tx_buffer <= tx_rdata; - end + if ((state == STATE_DATA) && (cmd == CMD_WRITE) && phase[3]) begin + last_tx_failed <= ft_miso; + end - always_comb begin - usb_miosi = usb_miosi_output_enable ? usb_miosi_output : 4'bZZZZ; - end - - always_comb begin - case (state) - S_COMMAND: begin - usb_clk_output = clock_phase[P_PRE_FALLING] || clock_phase[P_FALLING]; - usb_cs_output = 1'b0; - if (is_cmd_write) begin - usb_miosi_output_data = nibble_counter[0] ? C_WRITE[3:0] : C_WRITE[7:4]; - end else begin - usb_miosi_output_data = nibble_counter[0] ? C_READ[3:0] : C_READ[7:4]; + if (!ft_miso && (state == STATE_DATA) && phase[3]) begin + if (cmd == CMD_READ_MODEM_STATUS) begin + last_reset_status <= ft_miosi_in[0]; + if (!last_reset_status && ft_miosi_in[0]) begin + usb_scb.reset_pending <= 1'b1; + end + if (last_reset_status && !ft_miosi_in[0]) begin + reset_reply <= 1'b0; + write_modem_status_pending <= 1'b1; + end + end + if (cmd == CMD_WRITE_MODEM_STATUS) begin + write_modem_status_pending <= 1'b0; + end + if (cmd == CMD_WRITE_BUFFER_FLUSH) begin + write_buffer_flush_pending <= 1'b0; end - usb_miosi_output_enable_data = nibble_counter < 2'd2; end - - S_DATA: begin - usb_clk_output = clock_phase[P_PRE_FALLING] || clock_phase[P_FALLING]; - usb_cs_output = 1'b0; - usb_miosi_output_data = nibble_counter[0] ? tx_buffer[7:4] : tx_buffer[3:0]; - usb_miosi_output_enable_data = is_cmd_write; - end - - default: begin - usb_clk_output = 1'b0; - usb_cs_output = 1'b1; - usb_miosi_output_data = 4'hF; - usb_miosi_output_enable_data = 1'b0; - end - endcase + end end - always_ff @(posedge sys.clk) begin - rx_wdata_valid <= 1'b0; - tx_read <= 1'b0; + always_comb begin + ft_clk = 1'b0; + ft_cs = 1'b1; + ft_miosi_out = 8'hFF; + ft_oe = 1'b0; - if (clock_phase[P_RISING]) begin - nibble_counter <= nibble_counter + 1'd1; + if (state == STATE_SELECT) begin + ft_cs = 1'b0; end - if (sys.reset || !usb_enabled) begin - state <= S_TRY_RX; + if (state == STATE_COMMAND) begin + if (phase[0] || phase[1]) begin + ft_clk = 1'b1; + end + ft_cs = 1'b0; + ft_miosi_out = cmd; + ft_oe = 1'b1; + end + + if (state == STATE_STATUS) begin + if (phase[0] || phase[1]) begin + ft_clk = 1'b1; + end + ft_cs = 1'b0; + end + + if (state == STATE_DATA) begin + if (phase[0] || phase[1]) begin + ft_clk = 1'b1; + end + ft_cs = 1'b0; + if (cmd == CMD_WRITE) begin + ft_miosi_out = tx_rdata; + ft_oe = 1'b1; + end + if (cmd == CMD_WRITE_MODEM_STATUS) begin + ft_miosi_out = {2'b00, reset_reply, 5'b00000}; + ft_oe = 1'b1; + end + end + end + + always_comb begin + rx_write = 1'b0; + tx_read = 1'b0; + + rx_wdata = ft_miosi_in; + + if (!ft_miso && phase[3]) begin + case (state) + STATE_STATUS: begin + if (cmd == CMD_WRITE && !last_tx_failed) begin + tx_read = 1'b1; + end + end + + STATE_DATA: begin + if (cmd == CMD_READ) begin + rx_write = 1'b1; + end + if (cmd == CMD_WRITE && !tx_empty) begin + tx_read = 1'b1; + end + end + endcase + end + end + + always_comb begin + next_state = state; + next_cmd = cmd; + + if (reset) begin + next_state = STATE_IDLE; end else begin case (state) - S_TRY_RX: begin - if (!rx_full && !rx_escape_valid) begin - state <= S_COMMAND; - is_cmd_write <= 1'b0; - nibble_counter <= 2'b11; - end else begin - state <= S_TRY_TX; + STATE_IDLE: begin + if (ft_pwrsav) begin + if (write_modem_status_pending) begin + next_state = STATE_SELECT; + next_cmd = CMD_WRITE_MODEM_STATUS; + end else if (&modem_status_counter) begin + next_state = STATE_SELECT; + next_cmd = CMD_READ_MODEM_STATUS; + end else if (!tx_empty || last_tx_failed) begin + next_state = STATE_SELECT; + next_cmd = CMD_WRITE; + end else if (write_buffer_flush_pending) begin + next_state = STATE_SELECT; + next_cmd = CMD_WRITE_BUFFER_FLUSH; + end else if (!rx_full) begin + next_state = STATE_SELECT; + next_cmd = CMD_READ; + end end end - S_TRY_TX: begin - if (!tx_empty) begin - state <= S_COMMAND; - is_cmd_write <= 1'b1; - nibble_counter <= 2'b11; - end else begin - state <= S_TRY_RX; + STATE_SELECT: begin + if (phase[3]) begin + next_state = STATE_COMMAND; end end - S_COMMAND: begin - if (clock_phase[P_RISING]) begin - if (nibble_counter == 2'd2) begin - if (usb_miso_input) begin - state <= is_cmd_write ? S_TRY_RX : S_TRY_TX; - end else begin - state <= S_DATA; - nibble_counter <= 2'd0; + STATE_COMMAND: begin + if (phase[3]) begin + next_state = STATE_STATUS; + end + end + + STATE_STATUS: begin + if (phase[3]) begin + if (ft_miso) begin + next_state = STATE_DESELECT; + end else begin + next_state = STATE_DATA; + end + end + end + + STATE_DATA: begin + if (phase[3]) begin + if (ft_miso) begin + next_state = STATE_DESELECT; + end else if (cmd == CMD_READ) begin + if (rx_almost_full) begin + next_state = STATE_DESELECT; end + end else if (cmd == CMD_WRITE) begin + if (tx_empty) begin + next_state = STATE_DESELECT; + end + end else begin + next_state = STATE_DESELECT; end end end - S_DATA: begin - if (clock_phase[P_FALLING]) begin - if (nibble_counter[0]) begin - tx_read <= is_cmd_write; - end - end - if (clock_phase[P_RISING]) begin - rx_wdata <= {usb_miosi_input, rx_wdata[7:4]}; - if (nibble_counter[0]) begin - rx_wdata_valid <= !is_cmd_write; - end - if (usb_miso_input || (!is_cmd_write && (rx_full || rx_escape_valid)) || (is_cmd_write && tx_empty)) begin - state <= is_cmd_write ? S_TRY_RX : S_TRY_TX; - end + STATE_DESELECT: begin + if (phase[1]) begin + next_state = STATE_IDLE; end end default: begin - state <= S_TRY_RX; + next_state = STATE_IDLE; end endcase end diff --git a/fw/rtl/vendor/lcmxo2/fifo_8kb.sv b/fw/rtl/vendor/lcmxo2/fifo_8kb.sv new file mode 100644 index 0000000..db02ad2 --- /dev/null +++ b/fw/rtl/vendor/lcmxo2/fifo_8kb.sv @@ -0,0 +1,47 @@ +module fifo_8kb ( + input clk, + input reset, + + output empty, + output almost_empty, + input read, + output [7:0] rdata, + + output full, + output almost_full, + input write, + input [7:0] wdata, + + output logic [10:0] count +); + + fifo_8kb_lattice_generated fifo_8kb_lattice_generated_inst ( + .Data(wdata), + .WrClock(clk), + .RdClock(clk), + .WrEn(write), + .RdEn(read), + .Reset(reset), + .RPReset(reset), + .Q(rdata), + .Empty(empty), + .Full(full), + .AlmostEmpty(almost_empty), + .AlmostFull(almost_full) + ); + + always_ff @(posedge clk) begin + if (reset) begin + count <= 11'd0; + end else begin + if (write && read) begin + count <= count; + end else if (write) begin + count <= count + 1'd1; + end else if (read) begin + count <= count - 1'd1; + end + end + end + +endmodule diff --git a/fw/rtl/vendor/lcmxo2/generated/efb_lattice_generated.v b/fw/rtl/vendor/lcmxo2/generated/efb_lattice_generated.v new file mode 100644 index 0000000..17d16e8 --- /dev/null +++ b/fw/rtl/vendor/lcmxo2/generated/efb_lattice_generated.v @@ -0,0 +1,113 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */ +/* Module Version: 1.2 */ +/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n efb_lattice_generated -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 100 -ufm -ufm_ebr 2038 -mem_size 8 -ufm_0 -wb -dev 7000 */ +/* Sun Jul 31 17:59:17 2022 */ + + +`timescale 1 ns / 1 ps +module efb_lattice_generated (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, + wb_we_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_ack_o, wbc_ufm_irq)/* synthesis NGD_DRC_MASK=1 */; + input wire wb_clk_i; + input wire wb_rst_i; + input wire wb_cyc_i; + input wire wb_stb_i; + input wire wb_we_i; + input wire [7:0] wb_adr_i; + input wire [7:0] wb_dat_i; + output wire [7:0] wb_dat_o; + output wire wb_ack_o; + output wire wbc_ufm_irq; + + wire scuba_vhi; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ; + defparam EFBInst_0.UFM_INIT_FILE_NAME = "NONE" ; + defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "ENABLED" ; + defparam EFBInst_0.UFM_INIT_START_PAGE = 2038 ; + defparam EFBInst_0.UFM_INIT_PAGES = 8 ; + defparam EFBInst_0.DEV_DENSITY = "7000L" ; + defparam EFBInst_0.EFB_UFM = "ENABLED" ; + defparam EFBInst_0.TC_ICAPTURE = "DISABLED" ; + defparam EFBInst_0.TC_OVERFLOW = "DISABLED" ; + defparam EFBInst_0.TC_ICR_INT = "OFF" ; + defparam EFBInst_0.TC_OCR_INT = "OFF" ; + defparam EFBInst_0.TC_OV_INT = "OFF" ; + defparam EFBInst_0.TC_TOP_SEL = "OFF" ; + defparam EFBInst_0.TC_RESETN = "ENABLED" ; + defparam EFBInst_0.TC_OC_MODE = "TOGGLE" ; + defparam EFBInst_0.TC_OCR_SET = 32767 ; + defparam EFBInst_0.TC_TOP_SET = 65535 ; + defparam EFBInst_0.GSR = "ENABLED" ; + defparam EFBInst_0.TC_CCLK_SEL = 1 ; + defparam EFBInst_0.TC_MODE = "CTCM" ; + defparam EFBInst_0.TC_SCLK_SEL = "PCLOCK" ; + defparam EFBInst_0.EFB_TC_PORTMODE = "WB" ; + defparam EFBInst_0.EFB_TC = "DISABLED" ; + defparam EFBInst_0.SPI_WAKEUP = "DISABLED" ; + defparam EFBInst_0.SPI_INTR_RXOVR = "DISABLED" ; + defparam EFBInst_0.SPI_INTR_TXOVR = "DISABLED" ; + defparam EFBInst_0.SPI_INTR_RXRDY = "DISABLED" ; + defparam EFBInst_0.SPI_INTR_TXRDY = "DISABLED" ; + defparam EFBInst_0.SPI_SLAVE_HANDSHAKE = "DISABLED" ; + defparam EFBInst_0.SPI_PHASE_ADJ = "DISABLED" ; + defparam EFBInst_0.SPI_CLK_INV = "DISABLED" ; + defparam EFBInst_0.SPI_LSB_FIRST = "DISABLED" ; + defparam EFBInst_0.SPI_CLK_DIVIDER = 2 ; + defparam EFBInst_0.SPI_MODE = "MASTER" ; + defparam EFBInst_0.EFB_SPI = "DISABLED" ; + defparam EFBInst_0.I2C2_WAKEUP = "DISABLED" ; + defparam EFBInst_0.I2C2_GEN_CALL = "DISABLED" ; + defparam EFBInst_0.I2C2_CLK_DIVIDER = 1 ; + defparam EFBInst_0.I2C2_BUS_PERF = "100kHz" ; + defparam EFBInst_0.I2C2_SLAVE_ADDR = "0b1000010" ; + defparam EFBInst_0.I2C2_ADDRESSING = "7BIT" ; + defparam EFBInst_0.EFB_I2C2 = "DISABLED" ; + defparam EFBInst_0.I2C1_WAKEUP = "DISABLED" ; + defparam EFBInst_0.I2C1_GEN_CALL = "DISABLED" ; + defparam EFBInst_0.I2C1_CLK_DIVIDER = 1 ; + defparam EFBInst_0.I2C1_BUS_PERF = "100kHz" ; + defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ; + defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ; + defparam EFBInst_0.EFB_I2C1 = "DISABLED" ; + defparam EFBInst_0.EFB_WB_CLK_FREQ = "100.0" ; + EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i), + .WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]), + .WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]), + .WBADRI2(wb_adr_i[2]), .WBADRI1(wb_adr_i[1]), .WBADRI0(wb_adr_i[0]), + .WBDATI7(wb_dat_i[7]), .WBDATI6(wb_dat_i[6]), .WBDATI5(wb_dat_i[5]), + .WBDATI4(wb_dat_i[4]), .WBDATI3(wb_dat_i[3]), .WBDATI2(wb_dat_i[2]), + .WBDATI1(wb_dat_i[1]), .WBDATI0(wb_dat_i[0]), .PLL0DATI7(scuba_vlo), + .PLL0DATI6(scuba_vlo), .PLL0DATI5(scuba_vlo), .PLL0DATI4(scuba_vlo), + .PLL0DATI3(scuba_vlo), .PLL0DATI2(scuba_vlo), .PLL0DATI1(scuba_vlo), + .PLL0DATI0(scuba_vlo), .PLL0ACKI(scuba_vlo), .PLL1DATI7(scuba_vlo), + .PLL1DATI6(scuba_vlo), .PLL1DATI5(scuba_vlo), .PLL1DATI4(scuba_vlo), + .PLL1DATI3(scuba_vlo), .PLL1DATI2(scuba_vlo), .PLL1DATI1(scuba_vlo), + .PLL1DATI0(scuba_vlo), .PLL1ACKI(scuba_vlo), .I2C1SCLI(scuba_vlo), + .I2C1SDAI(scuba_vlo), .I2C2SCLI(scuba_vlo), .I2C2SDAI(scuba_vlo), + .SPISCKI(scuba_vlo), .SPIMISOI(scuba_vlo), .SPIMOSII(scuba_vlo), + .SPISCSN(scuba_vlo), .TCCLKI(scuba_vlo), .TCRSTN(scuba_vlo), .TCIC(scuba_vlo), + .UFMSN(scuba_vhi), .WBDATO7(wb_dat_o[7]), .WBDATO6(wb_dat_o[6]), + .WBDATO5(wb_dat_o[5]), .WBDATO4(wb_dat_o[4]), .WBDATO3(wb_dat_o[3]), + .WBDATO2(wb_dat_o[2]), .WBDATO1(wb_dat_o[1]), .WBDATO0(wb_dat_o[0]), + .WBACKO(wb_ack_o), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(), + .PLLWEO(), .PLLADRO4(), .PLLADRO3(), .PLLADRO2(), .PLLADRO1(), .PLLADRO0(), + .PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(), + .PLLDATO2(), .PLLDATO1(), .PLLDATO0(), .I2C1SCLO(), .I2C1SCLOEN(), + .I2C1SDAO(), .I2C1SDAOEN(), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAO(), + .I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKO(), .SPISCKEN(), + .SPIMISOO(), .SPIMISOEN(), .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN7(), + .SPIMCSN6(), .SPIMCSN5(), .SPIMCSN4(), .SPIMCSN3(), .SPIMCSN2(), + .SPIMCSN1(), .SPIMCSN0(), .SPICSNEN(), .SPIIRQO(), .TCINT(), .TCOC(), + .WBCUFMIRQ(wbc_ufm_irq), .CFGWAKE(), .CFGSTDBY()); + + + + // exemplar begin + // exemplar end + +endmodule diff --git a/fw/rtl/vendor/lcmxo2/generated/fifo_8kb_lattice_generated.v b/fw/rtl/vendor/lcmxo2/generated/fifo_8kb_lattice_generated.v new file mode 100644 index 0000000..dcf16bd --- /dev/null +++ b/fw/rtl/vendor/lcmxo2/generated/fifo_8kb_lattice_generated.v @@ -0,0 +1,66 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */ +/* Module Version: 5.8 */ +/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n fifo_8kb_lattice_generated -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ebfifo -depth 1024 -width 8 -rwidth 8 -no_enable -pe 1 -pf 1023 */ +/* Sat Mar 19 13:53:20 2022 */ + + +`timescale 1 ns / 1 ps +module fifo_8kb_lattice_generated (Data, WrClock, RdClock, WrEn, RdEn, + Reset, RPReset, Q, Empty, Full, AlmostEmpty, AlmostFull)/* synthesis NGD_DRC_MASK=1 */; + input wire [7:0] Data; + input wire WrClock; + input wire RdClock; + input wire WrEn; + input wire RdEn; + input wire Reset; + input wire RPReset; + output wire [7:0] Q; + output wire Empty; + output wire Full; + output wire AlmostEmpty; + output wire AlmostFull; + + wire scuba_vhi; + wire Empty_int; + wire Full_int; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam fifo_8kb_lattice_generated_0_0.FULLPOINTER1 = "0b01111111111000" ; + defparam fifo_8kb_lattice_generated_0_0.FULLPOINTER = "0b10000000000000" ; + defparam fifo_8kb_lattice_generated_0_0.AFPOINTER1 = "0b01111111110000" ; + defparam fifo_8kb_lattice_generated_0_0.AFPOINTER = "0b01111111111000" ; + defparam fifo_8kb_lattice_generated_0_0.AEPOINTER1 = "0b00000000010000" ; + defparam fifo_8kb_lattice_generated_0_0.AEPOINTER = "0b00000000001000" ; + defparam fifo_8kb_lattice_generated_0_0.ASYNC_RESET_RELEASE = "SYNC" ; + defparam fifo_8kb_lattice_generated_0_0.GSR = "DISABLED" ; + defparam fifo_8kb_lattice_generated_0_0.RESETMODE = "ASYNC" ; + defparam fifo_8kb_lattice_generated_0_0.REGMODE = "NOREG" ; + defparam fifo_8kb_lattice_generated_0_0.CSDECODE_R = "0b11" ; + defparam fifo_8kb_lattice_generated_0_0.CSDECODE_W = "0b11" ; + defparam fifo_8kb_lattice_generated_0_0.DATA_WIDTH_R = 9 ; + defparam fifo_8kb_lattice_generated_0_0.DATA_WIDTH_W = 9 ; + FIFO8KB fifo_8kb_lattice_generated_0_0 (.DI0(Data[0]), .DI1(Data[1]), + .DI2(Data[2]), .DI3(Data[3]), .DI4(Data[4]), .DI5(Data[5]), .DI6(Data[6]), + .DI7(Data[7]), .DI8(scuba_vlo), .DI9(scuba_vlo), .DI10(scuba_vlo), + .DI11(scuba_vlo), .DI12(scuba_vlo), .DI13(scuba_vlo), .DI14(scuba_vlo), + .DI15(scuba_vlo), .DI16(scuba_vlo), .DI17(scuba_vlo), .CSW0(scuba_vhi), + .CSW1(scuba_vhi), .CSR0(scuba_vhi), .CSR1(scuba_vhi), .FULLI(Full_int), + .EMPTYI(Empty_int), .WE(WrEn), .RE(RdEn), .ORE(RdEn), .CLKW(WrClock), + .CLKR(RdClock), .RST(Reset), .RPRST(RPReset), .DO0(Q[0]), .DO1(Q[1]), + .DO2(Q[2]), .DO3(Q[3]), .DO4(Q[4]), .DO5(Q[5]), .DO6(Q[6]), .DO7(Q[7]), + .DO8(), .DO9(), .DO10(), .DO11(), .DO12(), .DO13(), .DO14(), .DO15(), + .DO16(), .DO17(), .EF(Empty_int), .AEF(AlmostEmpty), .AFF(AlmostFull), + .FF(Full_int)); + + assign Empty = Empty_int; + assign Full = Full_int; + + + // exemplar begin + // exemplar end + +endmodule diff --git a/fw/rtl/vendor/lcmxo2/generated/pll_lattice_generated.v b/fw/rtl/vendor/lcmxo2/generated/pll_lattice_generated.v new file mode 100644 index 0000000..5f3ad98 --- /dev/null +++ b/fw/rtl/vendor/lcmxo2/generated/pll_lattice_generated.v @@ -0,0 +1,98 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */ +/* Module Version: 5.7 */ +/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll_lattice_generated -lang verilog -synth synplify -arch xo2c00 -type pll -fin 50 -fclkop 100 -fclkop_tol 0.0 -fclkos 100 -fclkos_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 90 -trims_r -phase_cntl STATIC -fb_mode 1 -lock */ +/* Sat Mar 19 17:10:12 2022 */ + + +`timescale 1 ns / 1 ps +module pll_lattice_generated (CLKI, CLKOP, CLKOS, LOCK)/* synthesis NGD_DRC_MASK=1 */; + input wire CLKI; + output wire CLKOP; + output wire CLKOS; + output wire LOCK; + + wire CLKOS_t; + wire CLKOP_t; + wire scuba_vlo; + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam PLLInst_0.DDRST_ENA = "DISABLED" ; + defparam PLLInst_0.DCRST_ENA = "DISABLED" ; + defparam PLLInst_0.MRST_ENA = "DISABLED" ; + defparam PLLInst_0.PLLRST_ENA = "DISABLED" ; + defparam PLLInst_0.INTFB_WAKE = "DISABLED" ; + defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ; + defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ; + defparam PLLInst_0.PLL_USE_WB = "DISABLED" ; + defparam PLLInst_0.CLKOS3_FPHASE = 0 ; + defparam PLLInst_0.CLKOS3_CPHASE = 0 ; + defparam PLLInst_0.CLKOS2_FPHASE = 0 ; + defparam PLLInst_0.CLKOS2_CPHASE = 0 ; + defparam PLLInst_0.CLKOS_FPHASE = 2 ; + defparam PLLInst_0.CLKOS_CPHASE = 5 ; + defparam PLLInst_0.CLKOP_FPHASE = 0 ; + defparam PLLInst_0.CLKOP_CPHASE = 4 ; + defparam PLLInst_0.PLL_LOCK_MODE = 0 ; + defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOS_TRIM_POL = "RISING" ; + defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOP_TRIM_POL = "RISING" ; + defparam PLLInst_0.FRACN_DIV = 0 ; + defparam PLLInst_0.FRACN_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXD2 = "DIVD" ; + defparam PLLInst_0.PREDIVIDER_MUXD1 = 0 ; + defparam PLLInst_0.VCO_BYPASS_D0 = "DISABLED" ; + defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXC2 = "DIVC" ; + defparam PLLInst_0.PREDIVIDER_MUXC1 = 0 ; + defparam PLLInst_0.VCO_BYPASS_C0 = "DISABLED" ; + defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXB2 = "DIVB" ; + defparam PLLInst_0.PREDIVIDER_MUXB1 = 0 ; + defparam PLLInst_0.VCO_BYPASS_B0 = "DISABLED" ; + defparam PLLInst_0.CLKOS_ENABLE = "ENABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXA2 = "DIVA" ; + defparam PLLInst_0.PREDIVIDER_MUXA1 = 0 ; + defparam PLLInst_0.VCO_BYPASS_A0 = "DISABLED" ; + defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ; + defparam PLLInst_0.CLKOS3_DIV = 1 ; + defparam PLLInst_0.CLKOS2_DIV = 1 ; + defparam PLLInst_0.CLKOS_DIV = 5 ; + defparam PLLInst_0.CLKOP_DIV = 5 ; + defparam PLLInst_0.CLKFB_DIV = 2 ; + defparam PLLInst_0.CLKI_DIV = 1 ; + defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ; + EHXPLLJ PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), + .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), + .LOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), + .RST(scuba_vlo), .RESETM(scuba_vlo), .RESETC(scuba_vlo), .RESETD(scuba_vlo), + .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), + .ENCLKOS3(scuba_vlo), .PLLCLK(scuba_vlo), .PLLRST(scuba_vlo), .PLLSTB(scuba_vlo), + .PLLWE(scuba_vlo), .PLLADDR4(scuba_vlo), .PLLADDR3(scuba_vlo), .PLLADDR2(scuba_vlo), + .PLLADDR1(scuba_vlo), .PLLADDR0(scuba_vlo), .PLLDATI7(scuba_vlo), + .PLLDATI6(scuba_vlo), .PLLDATI5(scuba_vlo), .PLLDATI4(scuba_vlo), + .PLLDATI3(scuba_vlo), .PLLDATI2(scuba_vlo), .PLLDATI1(scuba_vlo), + .PLLDATI0(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(CLKOS_t), .CLKOS2(), + .CLKOS3(), .LOCK(LOCK), .INTLOCK(), .REFCLK(), .CLKINTFB(), .DPHSRC(), + .PLLACK(), .PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(), + .PLLDATO2(), .PLLDATO1(), .PLLDATO0()) + /* synthesis FREQUENCY_PIN_CLKOS="100.000000" */ + /* synthesis FREQUENCY_PIN_CLKOP="100.000000" */ + /* synthesis FREQUENCY_PIN_CLKI="50.000000" */ + /* synthesis ICP_CURRENT="9" */ + /* synthesis LPF_RESISTOR="72" */; + + assign CLKOS = CLKOS_t; + assign CLKOP = CLKOP_t; + + + // exemplar begin + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS 100.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 100.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 50.000000 + // exemplar attribute PLLInst_0 ICP_CURRENT 9 + // exemplar attribute PLLInst_0 LPF_RESISTOR 72 + // exemplar end + +endmodule diff --git a/fw/rtl/vendor/lcmxo2/pll.sv b/fw/rtl/vendor/lcmxo2/pll.sv new file mode 100644 index 0000000..30c63d4 --- /dev/null +++ b/fw/rtl/vendor/lcmxo2/pll.sv @@ -0,0 +1,36 @@ +module pll ( + input inclk, + output logic reset, + output clk, + output sdram_clk +); + + logic pll_sdram_clk; + logic buf_sdram_clk; + logic pll_lock; + + pll_lattice_generated pll_lattice_generated_inst ( + .CLKI(inclk), + .CLKOP(clk), + .CLKOS(pll_sdram_clk), + .LOCK(pll_lock) + ); + + ODDRXE oddrxe_sdram_clk_inst ( + .D0(1'b0), + .D1(1'b1), + .SCLK(pll_sdram_clk), + .RST(1'b0), + .Q(buf_sdram_clk) + ); + + OB ob_sdram_clk_inst ( + .I(buf_sdram_clk), + .O(sdram_clk) + ) /* synthesis IO_TYPE="LVCMOS33" */; + + always_ff @(posedge clk) begin + reset <= ~pll_lock; + end + +endmodule diff --git a/fw/rtl/vendor/lcmxo2/vendor.sv b/fw/rtl/vendor/lcmxo2/vendor.sv new file mode 100644 index 0000000..bf2ec4b --- /dev/null +++ b/fw/rtl/vendor/lcmxo2/vendor.sv @@ -0,0 +1,127 @@ +module vendor ( + input clk, + input reset, + + vendor_scb.vendor vendor_scb +); + + logic start; + logic busy; + logic [1:0] length; + logic [5:0] delay; + + logic request; + logic write; + logic ack; + logic [7:0] address; + logic [7:0] rdata; + logic [7:0] wdata; + + logic [23:0] wdata_buffer; + + logic ufm_irq; + + always_comb begin + start = vendor_scb.control_valid && vendor_scb.control_wdata[0] && !busy; + vendor_scb.control_rdata = { + 16'd0, + address, + 4'b0000, + length, + write, + busy + }; + end + + always_ff @(posedge clk) begin + if (reset) begin + busy <= 1'b0; + end else begin + if (start) begin + busy <= 1'b1; + end + if (length == 2'd0 && ack) begin + busy <= 1'b0; + end + end + end + + always_ff @(posedge clk) begin + if (start) begin + length <= vendor_scb.control_wdata[3:2]; + end + if (ack && length > 2'd0) begin + length <= length - 1'd1; + end + end + + always_ff @(posedge clk) begin + if (reset) begin + delay <= 6'd0; + end else begin + if (start && vendor_scb.control_wdata[4]) begin + delay <= 6'd35; + end + if (delay > 6'd0) begin + delay <= delay - 1'd1; + end + end + end + + always_ff @(posedge clk) begin + if (reset) begin + request <= 1'b0; + end else begin + if (start) begin + request <= 1'b1; + end + if (busy && !request && delay == 6'd0) begin + request <= 1'b1; + end + if (ack) begin + request <= 1'b0; + end + end + end + + always_ff @(posedge clk) begin + if (start) begin + write <= vendor_scb.control_wdata[1]; + end + end + + always_ff @(posedge clk) begin + if (start) begin + address <= vendor_scb.control_wdata[15:8]; + end + end + + always_ff @(posedge clk) begin + if (ack) begin + vendor_scb.data_rdata <= {vendor_scb.data_rdata[23:0], rdata}; + end + end + + always_ff @(posedge clk) begin + if (start) begin + {wdata, wdata_buffer} <= vendor_scb.data_wdata; + end + if (ack) begin + {wdata, wdata_buffer} <= {wdata_buffer, 8'h00}; + end + end + + efb_lattice_generated efb_lattice_generated_inst ( + .wb_clk_i(clk), + .wb_rst_i(reset), + .wb_cyc_i(request), + .wb_stb_i(request), + .wb_we_i(write), + .wb_adr_i(address), + .wb_dat_i(wdata), + .wb_dat_o(rdata), + .wb_ack_o(ack), + .wbc_ufm_irq(ufm_irq) + ); + +endmodule diff --git a/fw/rtl/vendor/vendor_scb.sv b/fw/rtl/vendor/vendor_scb.sv new file mode 100644 index 0000000..9c25b83 --- /dev/null +++ b/fw/rtl/vendor/vendor_scb.sv @@ -0,0 +1,25 @@ +interface vendor_scb (); + + logic control_valid; + logic [31:0] control_rdata; + logic [31:0] control_wdata; + logic [31:0] data_rdata; + logic [31:0] data_wdata; + + modport controller ( + output control_valid, + input control_rdata, + output control_wdata, + input data_rdata, + output data_wdata + ); + + modport vendor ( + input control_valid, + output control_rdata, + input control_wdata, + output data_rdata, + input data_wdata + ); + +endinterface diff --git a/fw/scripts/post_module.tcl b/fw/scripts/post_module.tcl deleted file mode 100644 index ed19714..0000000 --- a/fw/scripts/post_module.tcl +++ /dev/null @@ -1,6 +0,0 @@ -set flow [lindex $quartus(args) 0] - -if [string match "quartus_asm" $flow] { - post_message "Generating final programming file" - qexec "quartus_cpf -c SummerCart64.cof" -} diff --git a/hw/.gitignore b/hw/.gitignore deleted file mode 100644 index 110ec6d..0000000 --- a/hw/.gitignore +++ /dev/null @@ -1,7 +0,0 @@ -/CAMOutputs -*.b#* -*.l#* -*.s#* -*.pdf -*.zip -eagle.epf diff --git a/hw/README.md b/hw/README.md deleted file mode 100644 index 4960309..0000000 --- a/hw/README.md +++ /dev/null @@ -1,7 +0,0 @@ -# SummerCart64 Hardware - -Schematics and PCB design for SummerCart64 done in Autodesk Eagle software. - -## TODO - -- Expand documentation diff --git a/hw/SummerCart64.brd b/hw/SummerCart64.brd deleted file mode 100644 index 9366456..0000000 --- a/hw/SummerCart64.brd +++ /dev/null @@ -1,5643 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -SummerCart64 -N64 FlashCart/DevKit -SummerCart64 -N64 FlashCart/DevKit -HW version: 1.0a -Designed by Polprzewodnikowy - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - -Footprint for Nintendo 64 cartridge edge connector. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -26 -30 -35 -40 -45 -50 -1 -5 -10 -15 -20 -25 -BACK -FRONT - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - -<b>MICRON Flash Memory</b><p> -www.micron.com<br> -<author>Created by librarian@cadsoft.de</author><p> - - -<b>54-Pin Plastic TSOP</b> (400 mil)<p> -Source: http://download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -54-Pin Plastic TSOP (400 mil) -Source: http://download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf - - - - - - - -<b>Resistors in DIL Packages</b><p> -<author>Created by librarian@cadsoft.de</author> - - -<b>BOURNS</b> Chip Resistor Array<p> -Source: RS Component / BUORNS - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - -BOURNS Chip Resistor Array -Source: RS Component / BUORNS - - - - - - - -<b>Resistors, Capacitors, Inductors</b><p> -Based on the previous libraries: -<ul> -<li>r.lbr -<li>cap.lbr -<li>cap-fe.lbr -<li>captant.lbr -<li>polcap.lbr -<li>ipc-smd.lbr -</ul> -All SMD packages are defined according to the IPC specifications and CECC<p> -<author>Created by librarian@cadsoft.de</author><p> -<p> -for Electrolyt Capacitors see also :<p> -www.bccomponents.com <p> -www.panasonic.com<p> -www.kemet.com<p> -http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b> -<p> -for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p> - -<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0> -<tr valign="top"> - -<! <td width="10">&nbsp;</td> -<td width="90%"> - -<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b> -<P> -<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2> - <TR> - <TD COLSPAN=8> - <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT> - </TD> - </TR> - <TR> - <TD ALIGN=CENTER> - <B> - <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT> - </B> - </TD> - <TD ALIGN=CENTER> - <B> - <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI&nbsp;TECH</FONT> - </B> - </TD> - <TD ALIGN=CENTER> - <B> - <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT> - </B> - </TD> - <TD ALIGN=CENTER> - <B> - <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT> - </B> - </TD> - <TD ALIGN=CENTER> - <B> - <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT> - </B> - </TD> - <TD ALIGN=CENTER> - <B> - <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT> - </B> - </TD> - <TD ALIGN=CENTER> - <B> - <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT> - </B> - </TD> - <TD ALIGN=CENTER> - <B> - <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT> - </B> - </TD><TD>&nbsp;</TD> - </TR> - <TR> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 > - 3005P<BR> - 3006P<BR> - 3006W<BR> - 3006Y<BR> - 3009P<BR> - 3009W<BR> - 3009Y<BR> - 3057J<BR> - 3057L<BR> - 3057P<BR> - 3057Y<BR> - 3059J<BR> - 3059L<BR> - 3059P<BR> - 3059Y<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - 89P<BR> - 89W<BR> - 89X<BR> - 89PH<BR> - 76P<BR> - 89XH<BR> - 78SLT<BR> - 78L&nbsp;ALT<BR> - 56P&nbsp;ALT<BR> - 78P&nbsp;ALT<BR> - T8S<BR> - 78L<BR> - 56P<BR> - 78P<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - T18/784<BR> - 783<BR> - 781<BR> - -<BR> - -<BR> - -<BR> - 2199<BR> - 1697/1897<BR> - 1680/1880<BR> - 2187<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - 8035EKP/CT20/RJ-20P<BR> - -<BR> - RJ-20X<BR> - -<BR> - -<BR> - -<BR> - 1211L<BR> - 8012EKQ&nbsp;ALT<BR> - 8012EKR&nbsp;ALT<BR> - 1211P<BR> - 8012EKJ<BR> - 8012EKL<BR> - 8012EKQ<BR> - 8012EKR<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - 2101P<BR> - 2101W<BR> - 2101Y<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - 2102L<BR> - 2102S<BR> - 2102Y<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - EVMCOG<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - 43P<BR> - 43W<BR> - 43Y<BR> - -<BR> - -<BR> - -<BR> - -<BR> - 40L<BR> - 40P<BR> - 40Y<BR> - 70Y-T602<BR> - 70L<BR> - 70P<BR> - 70Y<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - RT/RTR12<BR> - RT/RTR12<BR> - RT/RTR12<BR> - -<BR> - RJ/RJR12<BR> - RJ/RJR12<BR> - RJ/RJR12<BR></FONT> - </TD> - </TR> - <TR> - <TD COLSPAN=8>&nbsp; - </TD> - </TR> - <TR> - <TD COLSPAN=8> - <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT> - </TD> - </TR> - <TR> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT> - </TD> - </TR> - <TR> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - 3250L<BR> - 3250P<BR> - 3250W<BR> - 3250X<BR> - 3252P<BR> - 3252W<BR> - 3252X<BR> - 3260P<BR> - 3260W<BR> - 3260X<BR> - 3262P<BR> - 3262W<BR> - 3262X<BR> - 3266P<BR> - 3266W<BR> - 3266X<BR> - 3290H<BR> - 3290P<BR> - 3290W<BR> - 3292P<BR> - 3292W<BR> - 3292X<BR> - 3296P<BR> - 3296W<BR> - 3296X<BR> - 3296Y<BR> - 3296Z<BR> - 3299P<BR> - 3299W<BR> - 3299X<BR> - 3299Y<BR> - 3299Z<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - 66P&nbsp;ALT<BR> - 66W&nbsp;ALT<BR> - 66X&nbsp;ALT<BR> - 66P&nbsp;ALT<BR> - 66W&nbsp;ALT<BR> - 66X&nbsp;ALT<BR> - -<BR> - 64W&nbsp;ALT<BR> - -<BR> - 64P&nbsp;ALT<BR> - 64W&nbsp;ALT<BR> - 64X&nbsp;ALT<BR> - 64P<BR> - 64W<BR> - 64X<BR> - 66X&nbsp;ALT<BR> - 66P&nbsp;ALT<BR> - 66W&nbsp;ALT<BR> - 66P<BR> - 66W<BR> - 66X<BR> - 67P<BR> - 67W<BR> - 67X<BR> - 67Y<BR> - 67Z<BR> - 68P<BR> - 68W<BR> - 68X<BR> - 67Y&nbsp;ALT<BR> - 67Z&nbsp;ALT<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - 5050<BR> - 5091<BR> - 5080<BR> - 5087<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - T63YB<BR> - T63XB<BR> - -<BR> - -<BR> - -<BR> - 5887<BR> - 5891<BR> - 5880<BR> - -<BR> - -<BR> - -<BR> - T93Z<BR> - T93YA<BR> - T93XA<BR> - T93YB<BR> - T93XB<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - 8026EKP<BR> - 8026EKW<BR> - 8026EKM<BR> - 8026EKP<BR> - 8026EKB<BR> - 8026EKM<BR> - 1309X<BR> - 1309P<BR> - 1309W<BR> - 8024EKP<BR> - 8024EKW<BR> - 8024EKN<BR> - RJ-9P/CT9P<BR> - RJ-9W<BR> - RJ-9X<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - 3103P<BR> - 3103Y<BR> - 3103Z<BR> - 3103P<BR> - 3103Y<BR> - 3103Z<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - 3105P/3106P<BR> - 3105W/3106W<BR> - 3105X/3106X<BR> - 3105Y/3106Y<BR> - 3105Z/3105Z<BR> - 3102P<BR> - 3102W<BR> - 3102X<BR> - 3102Y<BR> - 3102Z<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - EVMCBG<BR> - EVMCCG<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - 55-1-X<BR> - 55-4-X<BR> - 55-3-X<BR> - 55-2-X<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - 50-2-X<BR> - 50-4-X<BR> - 50-3-X<BR> - -<BR> - -<BR> - -<BR> - 64P<BR> - 64W<BR> - 64X<BR> - 64Y<BR> - 64Z<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - RT/RTR22<BR> - RT/RTR22<BR> - RT/RTR22<BR> - RT/RTR22<BR> - RJ/RJR22<BR> - RJ/RJR22<BR> - RJ/RJR22<BR> - RT/RTR26<BR> - RT/RTR26<BR> - RT/RTR26<BR> - RJ/RJR26<BR> - RJ/RJR26<BR> - RJ/RJR26<BR> - RJ/RJR26<BR> - RJ/RJR26<BR> - RJ/RJR26<BR> - RT/RTR24<BR> - RT/RTR24<BR> - RT/RTR24<BR> - RJ/RJR24<BR> - RJ/RJR24<BR> - RJ/RJR24<BR> - RJ/RJR24<BR> - RJ/RJR24<BR> - RJ/RJR24<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - </TR> - <TR> - <TD COLSPAN=8>&nbsp; - </TD> - </TR> - <TR> - <TD COLSPAN=8> - <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT> - </TD> - </TR> - <TR> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT> - </TD> - </TR> - <TR> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - 3323P<BR> - 3323S<BR> - 3323W<BR> - 3329H<BR> - 3329P<BR> - 3329W<BR> - 3339H<BR> - 3339P<BR> - 3339W<BR> - 3352E<BR> - 3352H<BR> - 3352K<BR> - 3352P<BR> - 3352T<BR> - 3352V<BR> - 3352W<BR> - 3362H<BR> - 3362M<BR> - 3362P<BR> - 3362R<BR> - 3362S<BR> - 3362U<BR> - 3362W<BR> - 3362X<BR> - 3386B<BR> - 3386C<BR> - 3386F<BR> - 3386H<BR> - 3386K<BR> - 3386M<BR> - 3386P<BR> - 3386S<BR> - 3386W<BR> - 3386X<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - 25P<BR> - 25S<BR> - 25RX<BR> - 82P<BR> - 82M<BR> - 82PA<BR> - -<BR> - -<BR> - -<BR> - 91E<BR> - 91X<BR> - 91T<BR> - 91B<BR> - 91A<BR> - 91V<BR> - 91W<BR> - 25W<BR> - 25V<BR> - 25P<BR> - -<BR> - 25S<BR> - 25U<BR> - 25RX<BR> - 25X<BR> - 72XW<BR> - 72XL<BR> - 72PM<BR> - 72RX<BR> - -<BR> - 72PX<BR> - 72P<BR> - 72RXW<BR> - 72RXL<BR> - 72X<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - T7YB<BR> - T7YA<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - TXD<BR> - TYA<BR> - TYP<BR> - -<BR> - TYD<BR> - TX<BR> - -<BR> - 150SX<BR> - 100SX<BR> - 102T<BR> - 101S<BR> - 190T<BR> - 150TX<BR> - 101<BR> - -<BR> - -<BR> - 101SX<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - ET6P<BR> - ET6S<BR> - ET6X<BR> - RJ-6W/8014EMW<BR> - RJ-6P/8014EMP<BR> - RJ-6X/8014EMX<BR> - TM7W<BR> - TM7P<BR> - TM7X<BR> - -<BR> - 8017SMS<BR> - -<BR> - 8017SMB<BR> - 8017SMA<BR> - -<BR> - -<BR> - CT-6W<BR> - CT-6H<BR> - CT-6P<BR> - CT-6R<BR> - -<BR> - CT-6V<BR> - CT-6X<BR> - -<BR> - -<BR> - 8038EKV<BR> - -<BR> - 8038EKX<BR> - -<BR> - -<BR> - 8038EKP<BR> - 8038EKZ<BR> - 8038EKW<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - 3321H<BR> - 3321P<BR> - 3321N<BR> - 1102H<BR> - 1102P<BR> - 1102T<BR> - RVA0911V304A<BR> - -<BR> - RVA0911H413A<BR> - RVG0707V100A<BR> - RVA0607V(H)306A<BR> - RVA1214H213A<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - 3104B<BR> - 3104C<BR> - 3104F<BR> - 3104H<BR> - -<BR> - 3104M<BR> - 3104P<BR> - 3104S<BR> - 3104W<BR> - 3104X<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - EVMQ0G<BR> - EVMQIG<BR> - EVMQ3G<BR> - EVMS0G<BR> - EVMQ0G<BR> - EVMG0G<BR> - -<BR> - -<BR> - -<BR> - EVMK4GA00B<BR> - EVM30GA00B<BR> - EVMK0GA00B<BR> - EVM38GA00B<BR> - EVMB6<BR> - EVLQ0<BR> - -<BR> - EVMMSG<BR> - EVMMBG<BR> - EVMMAG<BR> - -<BR> - -<BR> - EVMMCS<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - EVMM1<BR> - -<BR> - -<BR> - EVMM0<BR> - -<BR> - -<BR> - EVMM3<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - 62-3-1<BR> - 62-1-2<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - 67R<BR> - -<BR> - 67P<BR> - -<BR> - -<BR> - -<BR> - -<BR> - 67X<BR> - 63V<BR> - 63S<BR> - 63M<BR> - -<BR> - -<BR> - 63H<BR> - 63P<BR> - -<BR> - -<BR> - 63X<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - RJ/RJR50<BR> - RJ/RJR50<BR> - RJ/RJR50<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - </TR> -</TABLE> -<P>&nbsp;<P> -<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3> - <TR> - <TD COLSPAN=7> - <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT> - <P> - <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT> - </TD> - </TR> - <TR> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT> - </TD> - </TR> - <TR> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - 3224G<BR> - 3224J<BR> - 3224W<BR> - 3269P<BR> - 3269W<BR> - 3269X<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - 44G<BR> - 44J<BR> - 44W<BR> - 84P<BR> - 84W<BR> - 84X<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - ST63Z<BR> - ST63Y<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - ST5P<BR> - ST5W<BR> - ST5X<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - </TR> - <TR> - <TD COLSPAN=7>&nbsp; - </TD> - </TR> - <TR> - <TD COLSPAN=7> - <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT> - </TD> - </TR> - <TR> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT> - </TD> - </TR> - <TR> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - 3314G<BR> - 3314J<BR> - 3364A/B<BR> - 3364C/D<BR> - 3364W/X<BR> - 3313G<BR> - 3313J<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - 23B<BR> - 23A<BR> - 21X<BR> - 21W<BR> - -<BR> - 22B<BR> - 22A<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - ST5YL/ST53YL<BR> - ST5YJ/5T53YJ<BR> - ST-23A<BR> - ST-22B<BR> - ST-22<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - ST-4B<BR> - ST-4A<BR> - -<BR> - -<BR> - -<BR> - ST-3B<BR> - ST-3A<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - EVM-6YS<BR> - EVM-1E<BR> - EVM-1G<BR> - EVM-1D<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - G4B<BR> - G4A<BR> - TR04-3S1<BR> - TRG04-2S1<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - DVR-43A<BR> - CVR-42C<BR> - CVR-42A/C<BR> - -<BR> - -<BR></FONT> - </TD> - </TR> -</TABLE> -<P> -<FONT SIZE=4 FACE=ARIAL><B>ALT =&nbsp;ALTERNATE</B></FONT> -<P> - -&nbsp; -<P> -</td> -</tr> -</table> - - -<b>RESISTOR</b> - - - - - - - - ->NAME ->VALUE - - - - - -<b>CAPACITOR</b> - - - - - - - - ->NAME ->VALUE - - - - - -<b>CAPACITOR</b><p> - - - - - - - - ->NAME ->VALUE - - - - - - - -RESISTOR - - - - - -CAPACITOR - - - - - -CAPACITOR - - - - - - - -<b>TTL Devices, 74xx Series with European Symbols</b><p> -Based on the following sources: -<ul> -<li>Texas Instruments <i>TTL Data Book</i>&nbsp;&nbsp;&nbsp;Volume 1, 1996. -<li>TTL Data Book, Volume 2 , 1993 -<li>National Seminconductor Databook 1990, ALS/LS Logic -<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0 -<li>http://icmaster.com/ViewCompare.asp -</ul> -<author>Created by librarian@cadsoft.de</author> - - -<b>plastic thin shrink small outline package; 14 leads; body width 4.4 mm</b><p> -SOT402-1<br> -Source: http://www.nxp.com/documents/data_sheet/74ABT125.pdf - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -plastic thin shrink small outline package; 14 leads; body width 4.4 mm -SOT402-1 -Source: http://www.nxp.com/documents/data_sheet/74ABT125.pdf - - - - - - - -<b>Crystals and Crystal Resonators</b><p> -<author>Created by librarian@cadsoft.de</author> - - -<b>kHz RANGE CRYSTAL UNIT</b><p> -LOW PROFILE SMD<b> -Source: Epson Toyocom FC-12M.pdf - - - - - - - ->NAME ->VALUE - - - - -kHz RANGE CRYSTAL UNIT -LOW PROFILE SMD -Source: Epson Toyocom FC-12M.pdf - - - - - - - -<b>Lithium Batteries and NC Accus</b><p> -<author>Created by librarian@cadsoft.de</author> - - -<b>Battery Holder, SMT, 12mm</b><p> -multicomp PART NO. CH291-1220LF<br> -Source: <a href="http://www.farnell.com/datasheets/1505860.pdf"> Data sheet </a> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - -Battery Holder, SMT, 12mm -multicomp PART NO. CH291-1220LF -Source: Data sheet - - - - - - - -<b>Diodes</b><p> -Based on the following sources: -<ul> -<li>Motorola : www.onsemi.com -<li>Fairchild : www.fairchildsemi.com -<li>Philips : www.semiconductors.com -<li>Vishay : www.vishay.de -</ul> -<author>Created by librarian@cadsoft.de</author> - - -<b>SOD-323</b><p> -Source: www.st.com, BAT60J.pdf - - - - - - ->NAME ->VALUE - - - - - - - - -SOD-323 -Source: www.st.com, BAT60J.pdf - - - - - - - -<b>Samtec Connectors</b><p> -<author>Created by librarian@cadsoft.de</author> - - -<b>THROUGH-HOLE .025" SQ POST SOCKET</b><p> -Source: Samtec SSW.pdf - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -1 -2 ->NAME ->VALUE - - - - -<b>LEDs</b><p> -<author>Created by librarian@cadsoft.de</author><br> -Extended by Federico Battaglin <author>&lt;federico.rd@fdpinternational.com&gt;</author> with DUOLED - - -<b>SML0603-XXX (HIGH INTENSITY) LED</b><p> -<table> -<tr><td>AG3K</td><td>AQUA GREEN</td></tr> -<tr><td>B1K</td><td>SUPER BLUE</td></tr> -<tr><td>R1K</td><td>SUPER RED</td></tr> -<tr><td>R3K</td><td>ULTRA RED</td></tr> -<tr><td>O3K</td><td>SUPER ORANGE</td></tr> -<tr><td>O3KH</td><td>SOFT ORANGE</td></tr> -<tr><td>Y3KH</td><td>SUPER YELLOW</td></tr> -<tr><td>Y3K</td><td>SUPER YELLOW</td></tr> -<tr><td>2CW</td><td>WHITE</td></tr> -</table> -Source: http://www.ledtronics.com/ds/smd-0603/Dstr0092.pdf - - - - - - - - - - ->NAME ->VALUE - - - - - - -SML0603-XXX (HIGH INTENSITY) LED - -AG3KAQUA GREEN -B1KSUPER BLUE -R1KSUPER RED -R3KULTRA RED -O3KSUPER ORANGE -O3KHSOFT ORANGE -Y3KHSUPER YELLOW -Y3KSUPER YELLOW -2CWWHITE - -Source: http://www.ledtronics.com/ds/smd-0603/Dstr0092.pdf - - - - - - - -<b>Voltage Regulators</b><p> -<author>Created by librarian@cadsoft.de</author> - - -<b>Small Outline Transistor 223</b><p> -PLASTIC PACKAGE CASE 318E-04<br> -Source: http://www.onsemi.co.jp .. LM137M-D.PDF - - - - - - - - - - - - - - - ->NAME ->VALUE -direction of pcb -transportation for -wavesoldering - - - - - - - - - - - - -Small Outline Transistor 223 -PLASTIC PACKAGE CASE 318E-04 -Source: http://www.onsemi.co.jp .. LM137M-D.PDF - - - - - - - - - - - - - - - - -<b>EAGLE Design Rules</b> -<p> -Die Standard-Design-Rules sind so gewählt, dass sie für -die meisten Anwendungen passen. Sollte ihre Platine -besondere Anforderungen haben, treffen Sie die erforderlichen -Einstellungen hier und speichern die Design Rules unter -einem neuen Namen ab. -<b>EAGLE Design Rules</b> -<p> -The default Design Rules have been set to cover -a wide range of applications. Your particular design -may have different requirements, so please make the -necessary adjustments and save your customized -design rules under a new name. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -Since Version 6.2.2 text objects can contain more than one line, -which will not be processed correctly with this version. - - -Since Version 8.2, EAGLE supports online libraries. The ids -of those online libraries will not be understood (or retained) -with this version. - - -Since Version 8.3, EAGLE supports URNs for individual library -assets (packages, symbols, and devices). The URNs of those assets -will not be understood (or retained) with this version. - - -Since Version 8.3, EAGLE supports the association of 3D packages -with devices in libraries, schematics, and board files. Those 3D -packages will not be understood (or retained) with this version. - - - diff --git a/hw/SummerCart64.cam b/hw/SummerCart64.cam deleted file mode 100644 index 3c5f3aa..0000000 --- a/hw/SummerCart64.cam +++ /dev/null @@ -1,276 +0,0 @@ -{ - "author": { - "email": "sc@mateuszfaderewski.pl", - "name": "Polprzewodnikowy" - }, - "description": { - "EN": "SummerCart64 CAM job." - }, - "output_type": "zip", - "outputs": [ - { - "filename_prefix": "CAMOutputs/GerberFiles", - "format_specifier": { - "decimal": 4, - "integer": 3 - }, - "generate_job_file": true, - "output_type": "gerber", - "outputs": [ - { - "advanced_options": { - "mirror": false, - "offset_x": 0, - "offset_y": 0, - "rotate": false, - "upside_down": false - }, - "board_outline": false, - "config": { - "file_function": "Copper", - "layer": 1, - "layer_details": "mixed", - "layer_type": "top" - }, - "filename_format": "%PREFIX/copper_top.gbr", - "layers": [ - 1, - 17, - 18 - ], - "name": "Top Copper", - "polarity": "positive", - "type": "gerber_layer" - }, - { - "advanced_options": { - "mirror": false, - "offset_x": 0, - "offset_y": 0, - "rotate": false, - "upside_down": false - }, - "board_outline": false, - "config": { - "file_function": "Copper", - "layer": 2, - "layer_details": "mixed", - "layer_type": "bottom" - }, - "filename_format": "%PREFIX/copper_bottom.gbr", - "layers": [ - 16, - 17, - 18 - ], - "name": "Bottom Copper", - "polarity": "positive", - "type": "gerber_layer" - }, - { - "advanced_options": { - "mirror": false, - "offset_x": 0, - "offset_y": 0, - "rotate": false, - "upside_down": false - }, - "board_outline": true, - "config": { - "file_function": "Profile", - "plating": "non-plated" - }, - "filename_format": "%PREFIX/profile.gbr", - "layers": [ - ], - "milling": true, - "polarity": "positive", - "type": "gerber_layer" - }, - { - "advanced_options": { - "mirror": false, - "offset_x": 0, - "offset_y": 0, - "rotate": false, - "upside_down": false - }, - "board_outline": false, - "config": { - "file_function": "Soldermask", - "index": 1, - "layer_type": "top" - }, - "filename_format": "%PREFIX/soldermask_top.gbr", - "layers": [ - 29 - ], - "name": "Soldermask Top", - "polarity": "positive", - "type": "gerber_layer" - }, - { - "advanced_options": { - "mirror": false, - "offset_x": 0, - "offset_y": 0, - "rotate": false, - "upside_down": false - }, - "board_outline": false, - "config": { - "file_function": "Soldermask", - "index": 1, - "layer_type": "bottom" - }, - "filename_format": "%PREFIX/soldermask_bottom.gbr", - "layers": [ - 30 - ], - "name": "Soldermask Bottom", - "polarity": "positive", - "type": "gerber_layer" - }, - { - "advanced_options": { - "mirror": false, - "offset_x": 0, - "offset_y": 0, - "rotate": false, - "upside_down": false - }, - "board_outline": false, - "config": { - "file_function": "Paste", - "layer_type": "top" - }, - "filename_format": "%PREFIX/solderpaste_top.gbr", - "layers": [ - 31 - ], - "milling": false, - "name": "Solderpaste Top", - "polarity": "positive", - "type": "gerber_layer" - }, - { - "advanced_options": { - "mirror": false, - "offset_x": 0, - "offset_y": 0, - "rotate": false, - "upside_down": false - }, - "board_outline": false, - "config": { - "file_function": "Paste", - "layer_type": "bottom" - }, - "filename_format": "%PREFIX/solderpaste_bottom.gbr", - "layers": [ - 32 - ], - "milling": false, - "name": "Solderpaste Bottom", - "polarity": "positive", - "type": "gerber_layer" - }, - { - "advanced_options": { - "mirror": false, - "offset_x": 0, - "offset_y": 0, - "rotate": false, - "upside_down": false - }, - "board_outline": false, - "config": { - "file_function": "Legend", - "index": 1, - "layer_type": "top" - }, - "filename_format": "%PREFIX/silkscreen_top.gbr", - "layers": [ - 21, - 25 - ], - "milling": false, - "name": "Silkscreen Top", - "polarity": "positive", - "type": "gerber_layer" - }, - { - "advanced_options": { - "mirror": false, - "offset_x": 0, - "offset_y": 0, - "rotate": false, - "upside_down": false - }, - "board_outline": false, - "config": { - "file_function": "Legend", - "index": 1, - "layer_type": "bottom" - }, - "filename_format": "%PREFIX/silkscreen_bottom.gbr", - "layers": [ - 22, - 26 - ], - "milling": false, - "name": "Silkscreen Bottom", - "polarity": "positive", - "type": "gerber_layer" - } - ], - "version": "RS274X" - }, - { - "filename_prefix": "CAMOutputs/DrillFiles", - "format_specifier": { - "decimal": 3, - "integer": 3 - }, - "output_type": "drill", - "outputs": [ - { - "advanced_options": { - "mirror": false, - "offset_x": 0, - "offset_y": 0, - "rotate": false, - "upside_down": false - }, - "filename_format": "%DRILLPREFIX/drill_%FROM_%TO.xln", - "name": "Auto Drill", - "type": "autodrills" - } - ] - }, - { - "filename_prefix": "CAMOutputs/Assembly", - "output_type": "assembly", - "outputs": [ - { - "filename_format": "%ASSEMBLYPREFIX/%N", - "list_attribute": true, - "list_type": "values", - "name": "Bill of Material", - "output_format": "txt", - "type": "bom" - } - ] - }, - { - "filename_prefix": "CAMOutputs/DrawingFiles", - "output_type": "drawing", - "outputs": [ - ] - } - ], - "timestamp": "2020-10-25T01:41:35", - "type": "EAGLE CAM job", - "units": "metric", - "version": "9.2.0" -} diff --git a/hw/SummerCart64.lbr b/hw/SummerCart64.lbr deleted file mode 100644 index f2284ad..0000000 --- a/hw/SummerCart64.lbr +++ /dev/null @@ -1,1532 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -Collection of parts used in SummerCart64 design - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - -Footprint for Nintendo 64 cartridge edge connector. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -26 -30 -35 -40 -45 -50 -1 -5 -10 -15 -20 -25 -BACK -FRONT - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - -Symbol for Nintendo 64 cartridge edge connector. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -Nintendo 64 cartridge edge connector. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/hw/SummerCart64.sch b/hw/SummerCart64.sch deleted file mode 100644 index ccde1f7..0000000 --- a/hw/SummerCart64.sch +++ /dev/null @@ -1,17889 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - -Footprint for Nintendo 64 cartridge edge connector. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -26 -30 -35 -40 -45 -50 -1 -5 -10 -15 -20 -25 -BACK -FRONT - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - -Symbol for Nintendo 64 cartridge edge connector. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -Nintendo 64 cartridge edge connector. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -<b>Supply Symbols</b><p> - GND, VCC, 0V, +5V, -5V, etc.<p> - Please keep in mind, that these devices are necessary for the - automatic wiring of the supply signals.<p> - The pin name defined in the symbol is identical to the net which is to be wired automatically.<p> - In this library the device names are the same as the pin names of the symbols, therefore the correct signal names appear next to the supply symbols in the schematic.<p> - <author>Created by librarian@cadsoft.de</author> - - - - - ->VALUE - - - - - ->VALUE - - - - - -<b>SUPPLY SYMBOL</b> - - - - - - - - - - - - -<b>SUPPLY SYMBOL</b> - - - - - - - - - - - - - - -<b>MICRON Flash Memory</b><p> -www.micron.com<br> -<author>Created by librarian@cadsoft.de</author><p> - - -<b>54-Pin Plastic TSOP</b> (400 mil)<p> -Source: http://download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -54-Pin Plastic TSOP (400 mil) -Source: http://download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -<b>256Mb: x16 SDRAM</b> MT48LC16M16A2 - 4 Meg x 16 x 4 banks<p> -Source: http://download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -<b>Resistors in DIL Packages</b><p> -<author>Created by librarian@cadsoft.de</author> - - -<b>Chip Resistor Array</b> size 4 × 0603<p> -concave termination - Phycomp Components<br> -Source: RS Components - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - -<b>Chip Resistor Array</b> size 4 × 0603<p> -convex termination - Phycomp Components<br> -Source: RS Components - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - -<b>BOURNS</b> Chip Resistor Array<p> -Source: RS Component / BUORNS - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - -<b>BOURNS</b> Chip Resistor Array<p> -Source: RS Component / BUORNS - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - -<b>ARRAY CHIP RESISTOR</b> Size 4 x 0402<p> -Source: www.yageo.com .. Pu-YC124_51_PbFree_L_1.pdf - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - -<b>Array chip resistor</b> size 4 × 0402<p> -Source: http://docs-europe.electrocomponents.com/webdocs/0114/0900766b80114d99.pdf - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - -<b>Chip Resistor Array 0201x4</b> 4 resistors in 1.4 mm x 0.6 mm size<p> -Source: PANASONIC .. aoc0000ce1.pdf - - - - - - - - - - - - - - ->NAME ->VALUE - - -<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p> -Source: PANASONIC .. aoc0000ce1.pdf - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - -<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.2 mm x 1.6 mm size (EXB38V, V8V)<p> -Source: PANASONIC .. aoc0000ce1.pdf - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - -<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p> -Source: PANASONIC .. aoc0000ce1.pdf - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - -<b>Chip Resistor Array 0805x4</b> 4 resistors in 5.08 mm x 2.20 mm size<p> -Source: PANASONIC .. aoc0000ce1.pdf - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - -<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p> -Source: PANASONIC .. aoc0000ce1.pdf - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - -Chip Resistor Array size 4 × 0603 -concave termination - Phycomp Components -Source: RS Components - - - - - -Chip Resistor Array size 4 × 0603 -convex termination - Phycomp Components -Source: RS Components - - - - - -BOURNS Chip Resistor Array -Source: RS Component / BUORNS - - - - - -BOURNS Chip Resistor Array -Source: RS Component / BUORNS - - - - - -ARRAY CHIP RESISTOR Size 4 x 0402 -Source: www.yageo.com .. Pu-YC124_51_PbFree_L_1.pdf - - - - - -Array chip resistor size 4 × 0402 -Source: http://docs-europe.electrocomponents.com/webdocs/0114/0900766b80114d99.pdf - - - - - -Chip Resistor Array 0201x4 4 resistors in 1.4 mm x 0.6 mm size -Source: PANASONIC .. aoc0000ce1.pdf - - - - - -Chip Resistor Array 0402x4 4 resistors in 2.0 mm x 1.0 mm size -Source: PANASONIC .. aoc0000ce1.pdf - - - - - -Chip Resistor Array 0603x4 4 resistors in 3.2 mm x 1.6 mm size (EXB38V, V8V) -Source: PANASONIC .. aoc0000ce1.pdf - - - - - -Chip Resistor Array 0402x4 4 resistors in 2.0 mm x 1.0 mm size -Source: PANASONIC .. aoc0000ce1.pdf - - - - - -Chip Resistor Array 0805x4 4 resistors in 5.08 mm x 2.20 mm size -Source: PANASONIC .. aoc0000ce1.pdf - - - - - -Chip Resistor Array 0603x4 4 resistors in 3.20 mm x 1.60 mm size -Source: PANASONIC .. aoc0000ce1.pdf - - - - - - - - - - - ->VALUE ->NAME - - - - - - -<b>Array Chip Resistor</b><p> -Source: RS Component / Phycomp - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -<b>Resistors, Capacitors, Inductors</b><p> -Based on the previous libraries: -<ul> -<li>r.lbr -<li>cap.lbr -<li>cap-fe.lbr -<li>captant.lbr -<li>polcap.lbr -<li>ipc-smd.lbr -</ul> -All SMD packages are defined according to the IPC specifications and CECC<p> -<author>Created by librarian@cadsoft.de</author><p> -<p> -for Electrolyt Capacitors see also :<p> -www.bccomponents.com <p> -www.panasonic.com<p> -www.kemet.com<p> -http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b> -<p> -for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p> - -<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0> -<tr valign="top"> - -<! <td width="10">&nbsp;</td> -<td width="90%"> - -<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b> -<P> -<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2> - <TR> - <TD COLSPAN=8> - <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT> - </TD> - </TR> - <TR> - <TD ALIGN=CENTER> - <B> - <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT> - </B> - </TD> - <TD ALIGN=CENTER> - <B> - <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI&nbsp;TECH</FONT> - </B> - </TD> - <TD ALIGN=CENTER> - <B> - <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT> - </B> - </TD> - <TD ALIGN=CENTER> - <B> - <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT> - </B> - </TD> - <TD ALIGN=CENTER> - <B> - <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT> - </B> - </TD> - <TD ALIGN=CENTER> - <B> - <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT> - </B> - </TD> - <TD ALIGN=CENTER> - <B> - <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT> - </B> - </TD> - <TD ALIGN=CENTER> - <B> - <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT> - </B> - </TD><TD>&nbsp;</TD> - </TR> - <TR> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 > - 3005P<BR> - 3006P<BR> - 3006W<BR> - 3006Y<BR> - 3009P<BR> - 3009W<BR> - 3009Y<BR> - 3057J<BR> - 3057L<BR> - 3057P<BR> - 3057Y<BR> - 3059J<BR> - 3059L<BR> - 3059P<BR> - 3059Y<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - 89P<BR> - 89W<BR> - 89X<BR> - 89PH<BR> - 76P<BR> - 89XH<BR> - 78SLT<BR> - 78L&nbsp;ALT<BR> - 56P&nbsp;ALT<BR> - 78P&nbsp;ALT<BR> - T8S<BR> - 78L<BR> - 56P<BR> - 78P<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - T18/784<BR> - 783<BR> - 781<BR> - -<BR> - -<BR> - -<BR> - 2199<BR> - 1697/1897<BR> - 1680/1880<BR> - 2187<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - 8035EKP/CT20/RJ-20P<BR> - -<BR> - RJ-20X<BR> - -<BR> - -<BR> - -<BR> - 1211L<BR> - 8012EKQ&nbsp;ALT<BR> - 8012EKR&nbsp;ALT<BR> - 1211P<BR> - 8012EKJ<BR> - 8012EKL<BR> - 8012EKQ<BR> - 8012EKR<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - 2101P<BR> - 2101W<BR> - 2101Y<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - 2102L<BR> - 2102S<BR> - 2102Y<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - EVMCOG<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - 43P<BR> - 43W<BR> - 43Y<BR> - -<BR> - -<BR> - -<BR> - -<BR> - 40L<BR> - 40P<BR> - 40Y<BR> - 70Y-T602<BR> - 70L<BR> - 70P<BR> - 70Y<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - RT/RTR12<BR> - RT/RTR12<BR> - RT/RTR12<BR> - -<BR> - RJ/RJR12<BR> - RJ/RJR12<BR> - RJ/RJR12<BR></FONT> - </TD> - </TR> - <TR> - <TD COLSPAN=8>&nbsp; - </TD> - </TR> - <TR> - <TD COLSPAN=8> - <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT> - </TD> - </TR> - <TR> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT> - </TD> - </TR> - <TR> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - 3250L<BR> - 3250P<BR> - 3250W<BR> - 3250X<BR> - 3252P<BR> - 3252W<BR> - 3252X<BR> - 3260P<BR> - 3260W<BR> - 3260X<BR> - 3262P<BR> - 3262W<BR> - 3262X<BR> - 3266P<BR> - 3266W<BR> - 3266X<BR> - 3290H<BR> - 3290P<BR> - 3290W<BR> - 3292P<BR> - 3292W<BR> - 3292X<BR> - 3296P<BR> - 3296W<BR> - 3296X<BR> - 3296Y<BR> - 3296Z<BR> - 3299P<BR> - 3299W<BR> - 3299X<BR> - 3299Y<BR> - 3299Z<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - 66P&nbsp;ALT<BR> - 66W&nbsp;ALT<BR> - 66X&nbsp;ALT<BR> - 66P&nbsp;ALT<BR> - 66W&nbsp;ALT<BR> - 66X&nbsp;ALT<BR> - -<BR> - 64W&nbsp;ALT<BR> - -<BR> - 64P&nbsp;ALT<BR> - 64W&nbsp;ALT<BR> - 64X&nbsp;ALT<BR> - 64P<BR> - 64W<BR> - 64X<BR> - 66X&nbsp;ALT<BR> - 66P&nbsp;ALT<BR> - 66W&nbsp;ALT<BR> - 66P<BR> - 66W<BR> - 66X<BR> - 67P<BR> - 67W<BR> - 67X<BR> - 67Y<BR> - 67Z<BR> - 68P<BR> - 68W<BR> - 68X<BR> - 67Y&nbsp;ALT<BR> - 67Z&nbsp;ALT<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - 5050<BR> - 5091<BR> - 5080<BR> - 5087<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - T63YB<BR> - T63XB<BR> - -<BR> - -<BR> - -<BR> - 5887<BR> - 5891<BR> - 5880<BR> - -<BR> - -<BR> - -<BR> - T93Z<BR> - T93YA<BR> - T93XA<BR> - T93YB<BR> - T93XB<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - 8026EKP<BR> - 8026EKW<BR> - 8026EKM<BR> - 8026EKP<BR> - 8026EKB<BR> - 8026EKM<BR> - 1309X<BR> - 1309P<BR> - 1309W<BR> - 8024EKP<BR> - 8024EKW<BR> - 8024EKN<BR> - RJ-9P/CT9P<BR> - RJ-9W<BR> - RJ-9X<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - 3103P<BR> - 3103Y<BR> - 3103Z<BR> - 3103P<BR> - 3103Y<BR> - 3103Z<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - 3105P/3106P<BR> - 3105W/3106W<BR> - 3105X/3106X<BR> - 3105Y/3106Y<BR> - 3105Z/3105Z<BR> - 3102P<BR> - 3102W<BR> - 3102X<BR> - 3102Y<BR> - 3102Z<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - EVMCBG<BR> - EVMCCG<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - 55-1-X<BR> - 55-4-X<BR> - 55-3-X<BR> - 55-2-X<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - 50-2-X<BR> - 50-4-X<BR> - 50-3-X<BR> - -<BR> - -<BR> - -<BR> - 64P<BR> - 64W<BR> - 64X<BR> - 64Y<BR> - 64Z<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - RT/RTR22<BR> - RT/RTR22<BR> - RT/RTR22<BR> - RT/RTR22<BR> - RJ/RJR22<BR> - RJ/RJR22<BR> - RJ/RJR22<BR> - RT/RTR26<BR> - RT/RTR26<BR> - RT/RTR26<BR> - RJ/RJR26<BR> - RJ/RJR26<BR> - RJ/RJR26<BR> - RJ/RJR26<BR> - RJ/RJR26<BR> - RJ/RJR26<BR> - RT/RTR24<BR> - RT/RTR24<BR> - RT/RTR24<BR> - RJ/RJR24<BR> - RJ/RJR24<BR> - RJ/RJR24<BR> - RJ/RJR24<BR> - RJ/RJR24<BR> - RJ/RJR24<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - </TR> - <TR> - <TD COLSPAN=8>&nbsp; - </TD> - </TR> - <TR> - <TD COLSPAN=8> - <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT> - </TD> - </TR> - <TR> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT> - </TD> - <TD ALIGN=CENTER> - <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT> - </TD> - </TR> - <TR> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - 3323P<BR> - 3323S<BR> - 3323W<BR> - 3329H<BR> - 3329P<BR> - 3329W<BR> - 3339H<BR> - 3339P<BR> - 3339W<BR> - 3352E<BR> - 3352H<BR> - 3352K<BR> - 3352P<BR> - 3352T<BR> - 3352V<BR> - 3352W<BR> - 3362H<BR> - 3362M<BR> - 3362P<BR> - 3362R<BR> - 3362S<BR> - 3362U<BR> - 3362W<BR> - 3362X<BR> - 3386B<BR> - 3386C<BR> - 3386F<BR> - 3386H<BR> - 3386K<BR> - 3386M<BR> - 3386P<BR> - 3386S<BR> - 3386W<BR> - 3386X<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - 25P<BR> - 25S<BR> - 25RX<BR> - 82P<BR> - 82M<BR> - 82PA<BR> - -<BR> - -<BR> - -<BR> - 91E<BR> - 91X<BR> - 91T<BR> - 91B<BR> - 91A<BR> - 91V<BR> - 91W<BR> - 25W<BR> - 25V<BR> - 25P<BR> - -<BR> - 25S<BR> - 25U<BR> - 25RX<BR> - 25X<BR> - 72XW<BR> - 72XL<BR> - 72PM<BR> - 72RX<BR> - -<BR> - 72PX<BR> - 72P<BR> - 72RXW<BR> - 72RXL<BR> - 72X<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - T7YB<BR> - T7YA<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - TXD<BR> - TYA<BR> - TYP<BR> - -<BR> - TYD<BR> - TX<BR> - -<BR> - 150SX<BR> - 100SX<BR> - 102T<BR> - 101S<BR> - 190T<BR> - 150TX<BR> - 101<BR> - -<BR> - -<BR> - 101SX<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - ET6P<BR> - ET6S<BR> - ET6X<BR> - RJ-6W/8014EMW<BR> - RJ-6P/8014EMP<BR> - RJ-6X/8014EMX<BR> - TM7W<BR> - TM7P<BR> - TM7X<BR> - -<BR> - 8017SMS<BR> - -<BR> - 8017SMB<BR> - 8017SMA<BR> - -<BR> - -<BR> - CT-6W<BR> - CT-6H<BR> - CT-6P<BR> - CT-6R<BR> - -<BR> - CT-6V<BR> - CT-6X<BR> - -<BR> - -<BR> - 8038EKV<BR> - -<BR> - 8038EKX<BR> - -<BR> - -<BR> - 8038EKP<BR> - 8038EKZ<BR> - 8038EKW<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - 3321H<BR> - 3321P<BR> - 3321N<BR> - 1102H<BR> - 1102P<BR> - 1102T<BR> - RVA0911V304A<BR> - -<BR> - RVA0911H413A<BR> - RVG0707V100A<BR> - RVA0607V(H)306A<BR> - RVA1214H213A<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - 3104B<BR> - 3104C<BR> - 3104F<BR> - 3104H<BR> - -<BR> - 3104M<BR> - 3104P<BR> - 3104S<BR> - 3104W<BR> - 3104X<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - EVMQ0G<BR> - EVMQIG<BR> - EVMQ3G<BR> - EVMS0G<BR> - EVMQ0G<BR> - EVMG0G<BR> - -<BR> - -<BR> - -<BR> - EVMK4GA00B<BR> - EVM30GA00B<BR> - EVMK0GA00B<BR> - EVM38GA00B<BR> - EVMB6<BR> - EVLQ0<BR> - -<BR> - EVMMSG<BR> - EVMMBG<BR> - EVMMAG<BR> - -<BR> - -<BR> - EVMMCS<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - EVMM1<BR> - -<BR> - -<BR> - EVMM0<BR> - -<BR> - -<BR> - EVMM3<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - 62-3-1<BR> - 62-1-2<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - 67R<BR> - -<BR> - 67P<BR> - -<BR> - -<BR> - -<BR> - -<BR> - 67X<BR> - 63V<BR> - 63S<BR> - 63M<BR> - -<BR> - -<BR> - 63H<BR> - 63P<BR> - -<BR> - -<BR> - 63X<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - RJ/RJR50<BR> - RJ/RJR50<BR> - RJ/RJR50<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - </TR> -</TABLE> -<P>&nbsp;<P> -<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3> - <TR> - <TD COLSPAN=7> - <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT> - <P> - <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT> - </TD> - </TR> - <TR> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT> - </TD> - </TR> - <TR> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - 3224G<BR> - 3224J<BR> - 3224W<BR> - 3269P<BR> - 3269W<BR> - 3269X<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - 44G<BR> - 44J<BR> - 44W<BR> - 84P<BR> - 84W<BR> - 84X<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - ST63Z<BR> - ST63Y<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - ST5P<BR> - ST5W<BR> - ST5X<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - </TR> - <TR> - <TD COLSPAN=7>&nbsp; - </TD> - </TR> - <TR> - <TD COLSPAN=7> - <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT> - </TD> - </TR> - <TR> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT> - </TD> - <TD> - <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT> - </TD> - </TR> - <TR> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - 3314G<BR> - 3314J<BR> - 3364A/B<BR> - 3364C/D<BR> - 3364W/X<BR> - 3313G<BR> - 3313J<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - 23B<BR> - 23A<BR> - 21X<BR> - 21W<BR> - -<BR> - 22B<BR> - 22A<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - ST5YL/ST53YL<BR> - ST5YJ/5T53YJ<BR> - ST-23A<BR> - ST-22B<BR> - ST-22<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - ST-4B<BR> - ST-4A<BR> - -<BR> - -<BR> - -<BR> - ST-3B<BR> - ST-3A<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - EVM-6YS<BR> - EVM-1E<BR> - EVM-1G<BR> - EVM-1D<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - G4B<BR> - G4A<BR> - TR04-3S1<BR> - TRG04-2S1<BR> - -<BR> - -<BR> - -<BR></FONT> - </TD> - <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> - -<BR> - -<BR> - DVR-43A<BR> - CVR-42C<BR> - CVR-42A/C<BR> - -<BR> - -<BR></FONT> - </TD> - </TR> -</TABLE> -<P> -<FONT SIZE=4 FACE=ARIAL><B>ALT =&nbsp;ALTERNATE</B></FONT> -<P> - -&nbsp; -<P> -</td> -</tr> -</table> - - -<b>Chip RESISTOR 0402 EIA (1005 Metric)</b> - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b> - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b> wave soldering<p> - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b> - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> -wave soldering - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b> - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> -wave soldering - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b> - - - - - - - - ->NAME ->VALUE - - - - -<b>RESISTOR</b><p> -wave soldering - - - - - - - - ->NAME ->VALUE - - - - -<b>RESISTOR</b> - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> -wave soldering - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b> - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> -wave soldering - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b> - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> -wave soldering - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b> - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> -wave soldering - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b> - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> -wave soldering - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> -Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b> wave soldering<p> -Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> -MELF 0.10 W - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> -MELF 0.25 W - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> -MELF 0.12 W - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> -MELF 0.10 W - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> -MELF 0.25 W - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> -MELF 0.25 W - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> -MELF 0.12 W - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> -MELF 0.25 W - - - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> -type 0204, grid 5 mm - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - -<b>RESISTOR</b><p> -type 0204, grid 7.5 mm - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - -<b>RESISTOR</b><p> -type 0204, grid 2.5 mm - - - - - - ->NAME ->VALUE - - -<b>RESISTOR</b><p> -type 0207, grid 10 mm - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - -<b>RESISTOR</b><p> -type 0207, grid 12 mm - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - -<b>RESISTOR</b><p> -type 0207, grid 15mm - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - -<b>RESISTOR</b><p> -type 0207, grid 2.5 mm - - - - - - - ->NAME ->VALUE - - -<b>RESISTOR</b><p> -type 0207, grid 5 mm - - - - - - - ->NAME ->VALUE - - -<b>RESISTOR</b><p> -type 0207, grid 7.5 mm - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - -<b>RESISTOR</b><p> -type 0309, grid 10mm - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - -<b>RESISTOR</b><p> -type 0309, grid 12.5 mm - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - -<b>RESISTOR</b><p> -type 0309, grid 2.5 mm - - - - - - ->NAME ->VALUE - - - - - -<b>RESISTOR</b><p> -type 0411, grid 12.5 mm - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - -<b>RESISTOR</b><p> -type 0411, grid 15 mm - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - -<b>RESISTOR</b><p> -type 0411, grid 3.81 mm - - - - - - ->NAME ->VALUE - - - -<b>RESISTOR</b><p> -type 0414, grid 15 mm - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - -<b>RESISTOR</b><p> -type 0414, grid 5 mm - - - - - - ->NAME ->VALUE - - - -<b>RESISTOR</b><p> -type 0617, grid 17.5 mm - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - -<b>RESISTOR</b><p> -type 0617, grid 22.5 mm - - - - - - - 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- - - - -RESISTOR -type 0817, grid 22.5 mm - - - - - -RESISTOR -type 0817, grid 6.35 mm - - - - - -RESISTOR -type V234, grid 12.5 mm - - - - - -RESISTOR -type V235, grid 17.78 mm - - - - - -RESISTOR -type V526-0, grid 2.5 mm - - - - - -CECC Size RC2211 Reflow Soldering -source Beyschlag - - - - - -CECC Size RC2211 Wave Soldering -source Beyschlag - - - - - -CECC Size RC3715 Reflow Soldering -source Beyschlag - - - - - -CECC Size RC3715 Wave Soldering -source Beyschlag - - - - - -CECC Size RC6123 Reflow Soldering -source Beyschlag - - - - - -CECC Size RC6123 Wave Soldering -source Beyschlag - - - - - -RESISTOR -type 0922, grid 7.5 mm - - - - - -RESISTOR -type RDH, grid 15 mm - - - - - -Mini MELF 0102 Axial - - - - - -RESISTOR chip -Source: http://www.vishay.com/docs/20008/dcrcw.pdf - - - - - -Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements -MIL SIZE RBR52 -Source: VISHAY .. vta56.pdf - - - - - -Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements -MIL SIZE RBR53 -Source: VISHAY .. vta56.pdf - - - - - -Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements -MIL SIZE RBR54 -Source: VISHAY .. vta56.pdf - - - - - -Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements -MIL SIZE RBR55 -Source: VISHAY .. vta56.pdf - - - - - -Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements -MIL SIZE RBR56 -Source: VISHAY .. vta56.pdf - - - - - -Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements -MIL SIZE RNC55 -Source: VISHAY .. vta56.pdf - - - - - -Bulk Metal® Foil Technology, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements -MIL SIZE RNC60 -Source: VISHAY .. vta56.pdf - - - - - -Package 4527 -Source: http://www.vishay.com/docs/31059/wsrhigh.pdf - - - - - -Wirewound Resistors, Precision Power -Source: VISHAY wscwsn.pdf - - - - - -Wirewound Resistors, Precision Power -Source: VISHAY wscwsn.pdf - - - - - -Wirewound Resistors, Precision Power -Source: VISHAY wscwsn.pdf - - - - - -Wirewound Resistors, Precision Power -Source: VISHAY wscwsn.pdf - - - - - -Wirewound Resistors, Precision Power -Source: VISHAY wscwsn.pdf - - - - - -Wirewound Resistors, Precision Power -Source: VISHAY wscwsn.pdf - - - - - -CRCW1218 Thick Film, Rectangular Chip Resistors -Source: http://www.vishay.com .. dcrcw.pdf - - - - - -Chip Monolithic Ceramic Capacitors Medium Voltage High Capacitance for General Use -Source: http://www.murata.com .. GRM43DR72E224KW01.pdf - - - - - -PRL1632 are realized as 1W for 3.2 × 1.6mm(1206) -Source: http://www.mouser.com/ds/2/392/products_18-2245.pdf - - - - - -Chip, 0.40 X 0.20 X 0.16 mm body -<p>Chip package with body size 0.40 X 0.20 X 0.16 mm</p> - - - - - -Chip, 1.00 X 0.50 X 0.60 mm body -<p>Chip package with body size 1.00 X 0.50 X 0.60 mm</p> - - - - - -CAPACITOR - - - - - -CAPACITOR - - - - - -CAPACITOR - - - - - -CAPACITOR - - - - - -CAPACITOR - - - - - -CAPACITOR - - - - - -CAPACITOR - - - - - -CAPACITOR - - - - - -CAPACITOR - - - - - -CAPACITOR - - - - - -CAPACITOR - - - - - -CAPACITOR - - - - - -CAPACITOR - - - - - -CAPACITOR - - - - - -CAPACITOR -grid 2.5 mm, outline 2.4 x 4.4 mm - - - - - -CAPACITOR -grid 2.5 mm, outline 2.5 x 5 mm - - - - - -CAPACITOR -grid 2.5 mm, outline 3 x 5 mm - - - - - -CAPACITOR -grid 2.5 mm, outline 4 x 5 mm - - - - - -CAPACITOR -grid 2.5 mm, outline 5 x 5 mm - - - - - -CAPACITOR -grid 2.5 mm, outline 6 x 5 mm - - - - - -CAPACITOR -grid 2.5 mm + 5 mm, outline 2.4 x 7 mm - - - - - -CAPACITOR -grid 2.5 + 5 mm, outline 2.5 x 7.5 mm - - - - - -CAPACITOR -grid 2.5 + 5 mm, outline 3.5 x 7.5 mm - - - - - -CAPACITOR -grid 2.5 + 5 mm, outline 4.5 x 7.5 mm - - - - - -CAPACITOR -grid 2.5 + 5 mm, outline 5.5 x 7.5 mm - - - - - -CAPACITOR -grid 5 mm, outline 2.4 x 4.4 mm - - - - - -CAPACITOR -grid 5 mm, outline 2.5 x 7.5 mm - - - - - -CAPACITOR -grid 5 mm, outline 4.5 x 7.5 mm - - - - - -CAPACITOR -grid 5 mm, outline 3 x 7.5 mm - - - - - -CAPACITOR -grid 5 mm, outline 5 x 7.5 mm - - - - - -CAPACITOR -grid 5 mm, outline 5.5 x 7.5 mm - - - - - -CAPACITOR -grid 5 mm, outline 7.5 x 7.5 mm - - - - - -CAPACITOR -Horizontal, grid 5 mm, outline 7.5 x 7.5 mm - - - - - -CAPACITOR -grid 7.5 mm, outline 3.2 x 10.3 mm - - - - - -CAPACITOR -grid 7.5 mm, outline 4.2 x 10.3 mm - - - - - -CAPACITOR -grid 7.5 mm, outline 5.2 x 10.6 mm - - - - - -CAPACITOR -grid 10.2 mm, outline 4.3 x 13.3 mm - - - - - -CAPACITOR -grid 10.2 mm, outline 5.4 x 13.3 mm - - - - - -CAPACITOR -grid 10.2 mm, outline 6.4 x 13.3 mm - - - - - -CAPACITOR -grid 10.2 mm + 15.2 mm, outline 6.2 x 18.4 mm - - - - - -CAPACITOR -grid 15 mm, outline 5.4 x 18.3 mm - - - - - -CAPACITOR -grid 15 mm, outline 6.4 x 18.3 mm - - - - - -CAPACITOR -grid 15 mm, outline 7.2 x 18.3 mm - - - - - -CAPACITOR -grid 15 mm, outline 8.4 x 18.3 mm - - - - - -CAPACITOR -grid 15 mm, outline 9.1 x 18.2 mm - - - - - -CAPACITOR -grid 22.5 mm, outline 6.2 x 26.8 mm - - - - - -CAPACITOR -grid 22.5 mm, outline 7.4 x 26.8 mm - - - - - -CAPACITOR -grid 22.5 mm, outline 8.7 x 26.8 mm - - - - - -CAPACITOR -grid 22.5 mm, outline 10.8 x 26.8 mm - - - - - -CAPACITOR -grid 22.5 mm, outline 11.3 x 26.8 mm - - - - - -CAPACITOR -grid 27.5 mm, outline 9.3 x 31.6 mm - - - - - -CAPACITOR -grid 27.5 mm, outline 11.3 x 31.6 mm - - - - - -CAPACITOR -grid 27.5 mm, outline 13.4 x 31.6 mm - - - - - -CAPACITOR -grid 27.5 mm, outline 20.5 x 31.6 mm - - - - - -CAPACITOR -grid 32.5 mm, outline 13.7 x 37.4 mm - - - - - -CAPACITOR -grid 32.5 mm, outline 16.2 x 37.4 mm - - - - - -CAPACITOR -grid 32.5 mm, outline 18.2 x 37.4 mm - - - - - -CAPACITOR -grid 37.5 mm, outline 19.2 x 41.8 mm - - - - - -CAPACITOR -grid 37.5 mm, outline 20.3 x 41.8 mm - - - - - -CAPACITOR -grid 5 mm, outline 3.5 x 7.5 mm - - - - - -CAPACITOR -grid 37.5 mm, outline 15.5 x 41.8 mm - - - - - -CAPACITOR -grid 7.5 mm, outline 6.3 x 10.6 mm - - - - - -CAPACITOR -grid 27.5 mm, outline 15.4 x 31.6 mm - - - - - -CAPACITOR -grid 27.5 mm, outline 17.3 x 31.6 mm - - - - - -Ceramic Chip Capacitor KEMET 0204 reflow solder -Metric Code Size 1005 - - - - - -Ceramic Chip Capacitor KEMET 0603 reflow solder -Metric Code Size 1608 - - - - - -Ceramic Chip Capacitor KEMET 0805 reflow solder -Metric Code Size 2012 - - - - - -Ceramic Chip Capacitor KEMET 1206 reflow solder -Metric Code Size 3216 - - - - - -Ceramic Chip Capacitor KEMET 1210 reflow solder -Metric Code Size 3225 - - - - - -Ceramic Chip Capacitor KEMET 1812 reflow solder -Metric Code Size 4532 - - - - - -Ceramic Chip Capacitor KEMET 1825 reflow solder -Metric Code Size 4564 - - - - - -Ceramic Chip Capacitor KEMET 2220 reflow solderMetric Code Size 5650 - - - - - -Ceramic Chip Capacitor KEMET 2225 reflow solderMetric Code Size 5664 - - - - - - -Source: http://www.vishay.com/docs/10129/hpc0201a.pdf - - - - - -Source: http://www.avxcorp.com/docs/catalogs/cx5r.pdf - - - - - -CAPACITOR -Source: AVX .. aphvc.pdf - - - - - -CAPACITOR -Source: AVX .. aphvc.pdf - - - - - -CAPACITOR - - - - - - - - - - - ->NAME ->VALUE - - - - - - ->NAME ->VALUE - - - - - - - - -<B>RESISTOR</B>, European symbol - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -<B>CAPACITOR</B>, European symbol - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -<b>TTL Devices, 74xx Series with European Symbols</b><p> -Based on the following sources: -<ul> -<li>Texas Instruments <i>TTL Data Book</i>&nbsp;&nbsp;&nbsp;Volume 1, 1996. -<li>TTL Data Book, Volume 2 , 1993 -<li>National Seminconductor Databook 1990, ALS/LS Logic -<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0 -<li>http://icmaster.com/ViewCompare.asp -</ul> -<author>Created by librarian@cadsoft.de</author> - - -<b>Dual In Line Package</b> - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - -<b>Small Outline package</b> 150 mil - - - - - - - - - - - - - - - - - - - - - - - - - - ->VALUE ->NAME - - - - - - - - - - - - - - - - -<b>plastic shrink small outline package; 14 leads; body width 5.3 mm</b><p> -SOT337-1<br> -Source: http://www.nxp.com/documents/data_sheet/74ABT125.pdf - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -<b>plastic thin shrink small outline package; 14 leads; body width 4.4 mm</b><p> -SOT402-1<br> -Source: http://www.nxp.com/documents/data_sheet/74ABT125.pdf - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -<b>plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm</b><p> -Source: http://www.nxp.com/documents/data_sheet/74ABT125.pdf - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - -Dual In Line Package - - - - - -Small Outline package 150 mil - - - - - -plastic shrink small outline package; 14 leads; body width 5.3 mm -SOT337-1 -Source: http://www.nxp.com/documents/data_sheet/74ABT125.pdf - - - - - -plastic thin shrink small outline package; 14 leads; body width 4.4 mm -SOT402-1 -Source: http://www.nxp.com/documents/data_sheet/74ABT125.pdf - - - - - -plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm -Source: http://www.nxp.com/documents/data_sheet/74ABT125.pdf - - - - - - - - - - - - ->NAME ->VALUE - - - - - ->NAME -GND -VCC - - - - - - -Quad bus <b>BUFFER</b>, 3-state - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -<b>Crystals and Crystal Resonators</b><p> -<author>Created by librarian@cadsoft.de</author> - - -<b>kHz RANGE CRYSTAL UNIT</b><p> -LOW PROFILE SMD<b> -Source: Epson Toyocom FC-12M.pdf - - - - - - - ->NAME ->VALUE - - - - -kHz RANGE CRYSTAL UNIT -LOW PROFILE SMD -Source: Epson Toyocom FC-12M.pdf - - - - - - - - - - - - - - - ->NAME ->VALUE -1 -2 - - - - - - -<b>kHz RANGE CRYSTAL UNIT</b><p> -LOW PROFILE SMD<b> -Source: Epson Toyocom FC-12M.pdf - - - - - - - - - - - - - - - - - - - - - - - -<b>Lithium Batteries and NC Accus</b><p> -<author>Created by librarian@cadsoft.de</author> - - -<b>Battery Holder, SMT, 12mm</b><p> -multicomp PART NO. CH291-1220LF<br> -Source: <a href="http://www.farnell.com/datasheets/1505860.pdf"> Data sheet </a> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - -Battery Holder, SMT, 12mm -multicomp PART NO. CH291-1220LF -Source: Data sheet - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - -<b>Battery Holder, SMT, 12mm</b><p> -multicomp PART NO. CH291-1220LF<br> -Source: <a href="http://www.farnell.com/datasheets/1505860.pdf"> Data sheet </a> - - - - - - - - - - - - - - - - - - - - - - - -<b>Diodes</b><p> -Based on the following sources: -<ul> -<li>Motorola : www.onsemi.com -<li>Fairchild : www.fairchildsemi.com -<li>Philips : www.semiconductors.com -<li>Vishay : www.vishay.de -</ul> -<author>Created by librarian@cadsoft.de</author> - - -<b>SOD-323</b><p> -Source: www.st.com, BAT60J.pdf - - - - - - ->NAME ->VALUE - - - - - - - - -SOD-323 -Source: www.st.com, BAT60J.pdf - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - -<b>Schottky barrier diode</b><p> -Source: www.st.com, BAT60J.pdf - - - - - - - - - - - - - - - - - - - - - - - -<b>Samtec Connectors</b><p> -<author>Created by librarian@cadsoft.de</author> - - -<b>THROUGH-HOLE .025" SQ POST SOCKET</b><p> -Source: Samtec SSW.pdf - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -1 -2 ->NAME ->VALUE - - -<b>THROUGH-HOLE .025" SQ POST SOCKET</b><p> -Source: Samtec SSW.pdf - - - - - - - - - - - - - - - - -1 -2 ->NAME ->VALUE - - - - - - - - -<b>THROUGH-HOLE .025" SQ POST SOCKET</b><p> -Source: Samtec SSW.pdf - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -1 -2 ->NAME ->VALUE - - -<b>THROUGH-HOLE .025" SQ POST SOCKET</b><p> -Source: Samtec SSW.pdf - - - - - - - - - - - - - - - - -1 -2 ->NAME ->VALUE - - - - - - - - - - - - - ->VALUE ->NAME - - - - - - ->NAME - - - - - -<b>THROUGH-HOLE .025" SQ POST SOCKET</b><p> -Source: Samtec SSW.pdf - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -<b>LEDs</b><p> -<author>Created by librarian@cadsoft.de</author><br> -Extended by Federico Battaglin <author>&lt;federico.rd@fdpinternational.com&gt;</author> with DUOLED - - -<b>CHICAGO MINIATURE LAMP, INC.</b><p> -7022X Series SMT LEDs 1206 Package Size - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - -<B>LED</B><p> -5 mm, square, Siemens - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - -<B>LED</B><p> -2 x 5 mm, rectangle - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - -<B>LED</B><p> -3 mm, round - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - -<B>LED</B><p> -5 mm, round - - - - - - - - - - - ->NAME ->VALUE - - -<B>LED</B><p> -1 mm, round, Siemens - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - -<B>LED BLOCK</B><p> -1 LED, Siemens - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - -<b>LED HOLDER</b><p> -Siemens - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - -<b>LED HOLDER</b><p> -Siemens - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - -<b>LED HOLDER</b><p> -Siemens - - - - - - - - - - - - - - - - - -A+ -K- ->NAME ->VALUE - - - - - -<b>LED HOLDER</b><p> -Siemens - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE -+ -- - - -<B>IR LED</B><p> -infrared emitting diode, Infineon -TO-18, lead spacing 2.54 mm, cathode marking<p> -Inifineon - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - -<B>IR LED</B><p> -infrared emitting diode, Infineon -TO-18, lead spacing 2.54 mm, cathode marking<p> -Inifineon - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - -<B>LED</B><p> -rectangle, 5.7 x 3.2 mm - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - -<B>IR LED</B><p> -IR transmitter Siemens - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - -<b>TOPLED® High-optical Power LED (HOP)</b><p> -Source: http://www.osram.convergy.de/ ... ls_t675.pdf - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE -A -C - - - - - - - -<b>BLUE LINETM Hyper Mini TOPLED® Hyper-Bright LED</b><p> -Source: http://www.osram.convergy.de/ ... LB M676.pdf - - - - - - - - - - - - - - -A -C ->NAME ->VALUE - - - - - - - -<b>Super SIDELED® High-Current LED</b><p> -LG A672, LP A672 <br> -Source: http://www.osram.convergy.de/ ... LG_LP_A672.pdf (2004.05.13) - - - - - - - - - - - - - - - - - - - -C -A ->NAME ->VALUE - - - - - - - -<b>SmartLEDTM Hyper-Bright LED</b><p> -Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY L896.pdf - - - - - - - - ->NAME ->VALUE - - - - - -<b>Hyper TOPLED® RG Hyper-Bright LED</b><p> -Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY T776.pdf - - - - - - - - - - - - - - - - - - ->NAME ->VALUE -A -C - - - - - - - - - - -<b>Hyper Micro SIDELED®</b><p> -Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY Y876.pdf - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - -<b>Power TOPLED®</b><p> -Source: http://www.osram.convergy.de/ ... LA_LO_LA_LY E67B.pdf - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE -C -A -C -C - - - - - - - - - - - -<b>Hyper CHIPLED Hyper-Bright LED</b><p> -LB Q993<br> -Source: http://www.osram.convergy.de/ ... Lb_q993.pdf - - - - ->NAME ->VALUE - - - - - - - -<b>Hyper CHIPLED Hyper-Bright LED</b><p> -LB R99A<br> -Source: http://www.osram.convergy.de/ ... lb_r99a.pdf - - - - ->NAME ->VALUE - - - - - - - -<b>Mini TOPLED Santana®</b><p> -Source: http://www.osram.convergy.de/ ... LG M470.pdf - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - -<b>CHIPLED</b><p> -Source: http://www.osram.convergy.de/ ... LG_R971.pdf - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - -<b>CHIPLED</b><p> -Source: http://www.osram.convergy.de/ ... LG_LY N971.pdf - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - -<b>CHIPLED</b><p> -Source: http://www.osram.convergy.de/ ... LG_LY Q971.pdf - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - -<b>CHIPLED-0603</b><p> -Recommended Solder Pad useable for SmartLEDTM and Chipled - Package 0603<br> -Package able to withstand TTW-soldering heat<br> -Package suitable for TTW-soldering<br> -Source: http://www.osram.convergy.de/ ... LO_LS_LY L89K.pdf - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - -<b>SmartLED TTW</b><p> -Recommended Solder Pad useable for SmartLEDTM and Chipled - Package 0603<br> -Package able to withstand TTW-soldering heat<br> -Package suitable for TTW-soldering<br> -Source: http://www.osram.convergy.de/ ... LO_LS_LY L89K.pdf - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - -<b>Lumileds Lighting. LUXEON®</b> with cool pad<p> -Source: K2.pdf - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -<b>Lumileds Lighting. LUXEON®</b> without cool pad<p> -Source: K2.pdf - - - - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - - - - - - -<B>LED</B><p> -10 mm, round - - - - - - - - - - - - - ->NAME ->VALUE - - -<b>SURFACE MOUNT LED LAMP</b> 3.5x2.8mm<p> -Source: http://www.kingbright.com/manager/upload/pdf/KA-3528ASYC(Ver1189474662.1) - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - - -<b>SML0805-2CW-TR (0805 PROFILE)</b> COOL WHITE<p> -Source: http://www.ledtronics.com/ds/smd-0603/Dstr0093.pdf - - - - - - - - - - - ->NAME ->VALUE - - -<b>SML10XXKH-TR (HIGH INTENSITY) LED</b><p> -<table> -<tr><td>SML10R3KH-TR</td><td>ULTRA RED</td></tr> -<tr><td>SML10E3KH-TR</td><td>SUPER REDSUPER BLUE</td></tr> -<tr><td>SML10O3KH-TR</td><td>SUPER ORANGE</td></tr> -<tr><td>SML10PY3KH-TR</td><td>PURE YELLOW</td></tr> -<tr><td>SML10OY3KH-TR</td><td>ULTRA YELLOW</td></tr> -<tr><td>SML10AG3KH-TR</td><td>AQUA GREEN</td></tr> -<tr><td>SML10BG3KH-TR</td><td>BLUE GREEN</td></tr> -<tr><td>SML10PB1KH-TR</td><td>SUPER BLUE</td></tr> -<tr><td>SML10CW1KH-TR</td><td>WHITE</td></tr> -</table> - -Source: http://www.ledtronics.com/ds/smd-1206/dstr0094.PDF - - - - - - - ->NAME ->VALUE - - - - - - - - - -<b>SML0603-XXX (HIGH INTENSITY) LED</b><p> -<table> -<tr><td>AG3K</td><td>AQUA GREEN</td></tr> -<tr><td>B1K</td><td>SUPER BLUE</td></tr> -<tr><td>R1K</td><td>SUPER RED</td></tr> -<tr><td>R3K</td><td>ULTRA RED</td></tr> -<tr><td>O3K</td><td>SUPER ORANGE</td></tr> -<tr><td>O3KH</td><td>SOFT ORANGE</td></tr> -<tr><td>Y3KH</td><td>SUPER YELLOW</td></tr> -<tr><td>Y3K</td><td>SUPER YELLOW</td></tr> -<tr><td>2CW</td><td>WHITE</td></tr> -</table> -Source: http://www.ledtronics.com/ds/smd-0603/Dstr0092.pdf - - - - - - - - - - ->NAME ->VALUE - - - - - - -CHICAGO MINIATURE LAMP, INC. -7022X Series SMT LEDs 1206 Package Size - - - - - -LED -5 mm, square, Siemens - - - - - -LED -2 x 5 mm, rectangle - - - - - -LED -3 mm, round - - - - - -LED -5 mm, round - - - - - -LED -1 mm, round, Siemens - - - - - -LED BLOCK -1 LED, Siemens - - - - - -LED HOLDER -Siemens - - - - - -LED HOLDER -Siemens - - - - - -LED HOLDER -Siemens - - - - - -LED HOLDER -Siemens - - - - - -IR LED -infrared emitting diode, Infineon -TO-18, lead spacing 2.54 mm, cathode marking -Inifineon - - - - - -IR LED -infrared emitting diode, Infineon -TO-18, lead spacing 2.54 mm, cathode marking -Inifineon - - - - - -LED -rectangle, 5.7 x 3.2 mm - - - - - -IR LED -IR transmitter Siemens - - - - - -TOPLED® High-optical Power LED (HOP) -Source: http://www.osram.convergy.de/ ... ls_t675.pdf - - - - - -BLUE LINETM Hyper Mini TOPLED® Hyper-Bright LED -Source: http://www.osram.convergy.de/ ... LB M676.pdf - - - - - -Super SIDELED® High-Current LED -LG A672, LP A672 -Source: http://www.osram.convergy.de/ ... LG_LP_A672.pdf (2004.05.13) - - - - - -SmartLEDTM Hyper-Bright LED -Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY L896.pdf - - - - - -Hyper TOPLED® RG Hyper-Bright LED -Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY T776.pdf - - - - - -Hyper Micro SIDELED® -Source: http://www.osram.convergy.de/ ... LA_LO_LS_LY Y876.pdf - - - - - -Power TOPLED® -Source: http://www.osram.convergy.de/ ... LA_LO_LA_LY E67B.pdf - - - - - -Hyper CHIPLED Hyper-Bright LED -LB Q993 -Source: http://www.osram.convergy.de/ ... Lb_q993.pdf - - - - - -Hyper CHIPLED Hyper-Bright LED -LB R99A -Source: http://www.osram.convergy.de/ ... lb_r99a.pdf - - - - - -Mini TOPLED Santana® -Source: http://www.osram.convergy.de/ ... LG M470.pdf - - - - - -CHIPLED -Source: http://www.osram.convergy.de/ ... LG_R971.pdf - - - - - -CHIPLED -Source: http://www.osram.convergy.de/ ... LG_LY N971.pdf - - - - - -CHIPLED -Source: http://www.osram.convergy.de/ ... LG_LY Q971.pdf - - - - - -CHIPLED-0603 -Recommended Solder Pad useable for SmartLEDTM and Chipled - Package 0603 -Package able to withstand TTW-soldering heat -Package suitable for TTW-soldering -Source: http://www.osram.convergy.de/ ... LO_LS_LY L89K.pdf - - - - - -SmartLED TTW -Recommended Solder Pad useable for SmartLEDTM and Chipled - Package 0603 -Package able to withstand TTW-soldering heat -Package suitable for TTW-soldering -Source: http://www.osram.convergy.de/ ... LO_LS_LY L89K.pdf - - - - - -Lumileds Lighting. LUXEON® with cool pad -Source: K2.pdf - - - - - -Lumileds Lighting. LUXEON® without cool pad -Source: K2.pdf - - - - - -LED -10 mm, round - - - - - -SURFACE MOUNT LED LAMP 3.5x2.8mm -Source: http://www.kingbright.com/manager/upload/pdf/KA-3528ASYC(Ver1189474662.1) - - - - - -SML0805-2CW-TR (0805 PROFILE) COOL WHITE -Source: http://www.ledtronics.com/ds/smd-0603/Dstr0093.pdf - - - - - -SML10XXKH-TR (HIGH INTENSITY) LED - -SML10R3KH-TRULTRA RED -SML10E3KH-TRSUPER REDSUPER BLUE -SML10O3KH-TRSUPER ORANGE -SML10PY3KH-TRPURE YELLOW -SML10OY3KH-TRULTRA YELLOW -SML10AG3KH-TRAQUA GREEN -SML10BG3KH-TRBLUE GREEN -SML10PB1KH-TRSUPER BLUE -SML10CW1KH-TRWHITE - - -Source: http://www.ledtronics.com/ds/smd-1206/dstr0094.PDF - - - - - -SML0603-XXX (HIGH INTENSITY) LED - -AG3KAQUA GREEN -B1KSUPER BLUE -R1KSUPER RED -R3KULTRA RED -O3KSUPER ORANGE -O3KHSOFT ORANGE -Y3KHSUPER YELLOW -Y3KSUPER YELLOW -2CWWHITE - -Source: http://www.ledtronics.com/ds/smd-0603/Dstr0092.pdf - - - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - - - - -<b>LED</b><p> -<u>OSRAM</u>:<br> - -- <u>CHIPLED</u><br> -LG R971, LG N971, LY N971, LG Q971, LY Q971, LO R971, LY R971 -LH N974, LH R974<br> -LS Q976, LO Q976, LY Q976<br> -LO Q996<br> - -- <u>Hyper CHIPLED</u><br> -LW Q18S<br> -LB Q993, LB Q99A, LB R99A<br> - -- <u>SideLED</u><br> -LS A670, LO A670, LY A670, LG A670, LP A670<br> -LB A673, LV A673, LT A673, LW A673<br> -LH A674<br> -LY A675<br> -LS A676, LA A676, LO A676, LY A676, LW A676<br> -LS A679, LY A679, LG A679<br> - -- <u>Hyper Micro SIDELED®</u><br> -LS Y876, LA Y876, LO Y876, LY Y876<br> -LT Y87S<br> - -- <u>SmartLED</u><br> -LW L88C, LW L88S<br> -LB L89C, LB L89S, LG L890<br> -LS L89K, LO L89K, LY L89K<br> -LS L896, LA L896, LO L896, LY L896<br> - -- <u>TOPLED</u><br> -LS T670, LO T670, LY T670, LG T670, LP T670<br> -LSG T670, LSP T670, LSY T670, LOP T670, LYG T670<br> -LG T671, LOG T671, LSG T671<br> -LB T673, LV T673, LT T673, LW T673<br> -LH T674<br> -LS T676, LA T676, LO T676, LY T676, LB T676, LH T676, LSB T676, LW T676<br> -LB T67C, LV T67C, LT T67C, LS T67K, LO T67K, LY T67K, LW E67C<br> -LS E67B, LA E67B, LO E67B, LY E67B, LB E67C, LV E67C, LT E67C<br> -LW T67C<br> -LS T679, LY T679, LG T679<br> -LS T770, LO T770, LY T770, LG T770, LP T770<br> -LB T773, LV T773, LT T773, LW T773<br> -LH T774<br> -LS E675, LA E675, LY E675, LS T675<br> -LS T776, LA T776, LO T776, LY T776, LB T776<br> -LHGB T686<br> -LT T68C, LB T68C<br> - -- <u>Hyper Mini TOPLED®</u><br> -LB M676<br> - -- <u>Mini TOPLED Santana®</u><br> -LG M470<br> -LS M47K, LO M47K, LY M47K -<p> -Source: http://www.osram.convergy.de<p> - -<u>LUXEON:</u><br> -- <u>LUMILED®</u><br> -LXK2-PW12-R00, LXK2-PW12-S00, LXK2-PW14-U00, LXK2-PW14-V00<br> -LXK2-PM12-R00, LXK2-PM12-S00, LXK2-PM14-U00<br> -LXK2-PE12-Q00, LXK2-PE12-R00, LXK2-PE12-S00, LXK2-PE14-T00, LXK2-PE14-U00<br> -LXK2-PB12-K00, LXK2-PB12-L00, LXK2-PB12-M00, LXK2-PB14-N00, LXK2-PB14-P00, LXK2-PB14-Q00<br> -LXK2-PR12-L00, LXK2-PR12-M00, LXK2-PR14-Q00, LXK2-PR14-R00<br> -LXK2-PD12-Q00, LXK2-PD12-R00, LXK2-PD12-S00<br> -LXK2-PH12-R00, LXK2-PH12-S00<br> -LXK2-PL12-P00, LXK2-PL12-Q00, LXK2-PL12-R00 -<p> -Source: www.luxeon.com<p> - -<u>KINGBRIGHT:</U><p> -KA-3528ASYC<br> -Source: www.kingbright.com - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -<b>Voltage Regulators</b><p> -<author>Created by librarian@cadsoft.de</author> - - -<b>DPAK</b><p> -PLASTIC PACKAGE CASE 369C-01<br> -Source: http://www.onsemi.co.jp .. LM317M-D.PDF - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - - - -<b>VOLTAGE REGULATOR</b> - - - - - - - - - - - - - - - - - - - - - - ->NAME ->VALUE -A15,2mm -1 -2 -3 - - - - - - - - - -<b>Small Outline Transistor 223</b><p> -PLASTIC PACKAGE CASE 318E-04<br> -Source: http://www.onsemi.co.jp .. LM137M-D.PDF - - - - - - - - - - - - - - - ->NAME ->VALUE -direction of pcb -transportation for -wavesoldering - - - - - - - - - - -<b>D2PACK</b><p> -INTERNATIONAL RECTIFIER, irg4bc15ud-s.pdf - - - - - - - - - - - - - ->NAME ->VALUE - - - - - - - - - - - -DPAK -PLASTIC PACKAGE CASE 369C-01 -Source: http://www.onsemi.co.jp .. LM317M-D.PDF - - - - - -VOLTAGE REGULATOR - - - - - -Small Outline Transistor 223 -PLASTIC PACKAGE CASE 318E-04 -Source: http://www.onsemi.co.jp .. LM137M-D.PDF - - - - - -D2PACK -INTERNATIONAL RECTIFIER, irg4bc15ud-s.pdf - - - - - - - - - - - ->NAME ->VALUE -ADJ -IN -OUT - - - - - - - -<b>Low drop fixed and adjustable positive voltage regulators</b> 1 A<p> -Source: http://www.st.com/stonline/products/literature/ds/7194/ld1117axx.pdf - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -RTC -LED -CIC - - - - -PMOD - - - - - - - - -FLASH -SRAM - - - - -FTDI EEPROM - - - - -N64 <-> FPGA Resistors - - - - -N64 Edge Connector - - - - -Crystal Oscillators - - - - -SDRAM - - - - -FTDI <-> CIC Buffer - - - - -FPGA - - - - -Pull-up Resistors - - - - -SD Card - - - - -FTDI - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -Since Version 8.2, EAGLE supports online libraries. The ids -of those online libraries will not be understood (or retained) -with this version. - - -Since Version 8.3, EAGLE supports URNs for individual library -assets (packages, symbols, and devices). The URNs of those assets -will not be understood (or retained) with this version. - - -Since Version 8.3, EAGLE supports the association of 3D packages -with devices in libraries, schematics, and board files. Those 3D -packages will not be understood (or retained) with this version. - - -Since Version 8.4, EAGLE supports properties for SPICE simulation. -Probes in schematics and SPICE mapping objects found in parts and library devices -will not be understood with this version. Update EAGLE to the latest version -for full support of SPICE simulation. - - - diff --git a/hw/pcb/.gitignore b/hw/pcb/.gitignore new file mode 100644 index 0000000..0e773db --- /dev/null +++ b/hw/pcb/.gitignore @@ -0,0 +1,7 @@ +**/*-backups +**/*-bak +**/*.csv +**/*.gerbers +**/*.kicad_prl +**/*.zip +**/fp-info-cache diff --git a/hw/pcb/sc64v2.kicad_pcb b/hw/pcb/sc64v2.kicad_pcb new file mode 100644 index 0000000..00367d9 --- /dev/null +++ b/hw/pcb/sc64v2.kicad_pcb @@ -0,0 +1,62349 @@ +(kicad_pcb (version 20211014) (generator pcbnew) + + (general + (thickness 1.2) + ) + + (paper "A4") + (title_block + (title "SC64") + (date "2022-05-15") + (rev "2.0") + (company "Polprzewodnikowy") + ) + + (layers + (0 "F.Cu" signal) + (31 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "F.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (40 "Dwgs.User" user "User.Drawings") + (41 "Cmts.User" user "User.Comments") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + (50 "User.1" user) + (51 "User.2" user) + (52 "User.3" user) + (53 "User.4" user) + (54 "User.5" user) + (55 "User.6" user) + (56 "User.7" user) + (57 "User.8" user) + (58 "User.9" user) + ) + + (setup + (stackup + (layer "F.SilkS" (type "Top Silk Screen") (color "White")) + (layer "F.Paste" (type "Top Solder Paste")) + (layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01)) + (layer "F.Cu" (type "copper") (thickness 0.035)) + (layer "dielectric 1" (type "core") (thickness 1.11) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02)) + (layer "B.Cu" (type "copper") (thickness 0.035)) + (layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01)) + (layer "B.Paste" (type "Bottom Solder Paste")) + (layer "B.SilkS" (type "Bottom Silk Screen") (color "White")) + (copper_finish "ENIG") + (dielectric_constraints no) + (edge_connector bevelled) + ) + (pad_to_mask_clearance 0) + (pcbplotparams + (layerselection 0x00010fc_ffffffff) + (disableapertmacros false) + (usegerberextensions true) + (usegerberattributes false) + (usegerberadvancedattributes false) + (creategerberjobfile false) + (svguseinch false) + (svgprecision 6) + (excludeedgelayer true) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (dxfpolygonmode true) + (dxfimperialunits true) + (dxfusepcbnewfont true) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue false) + (plotinvisibletext false) + (sketchpadsonfab false) + (subtractmaskfromsilk true) + (outputformat 1) + (mirror false) + (drillshape 0) + (scaleselection 1) + (outputdirectory "sc64v2.gerbers/") + ) + ) + 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"/1dbbd042-b212-4933-895e-d1a10aa96c60" + (reference "U9") (unit 1) (value "IS42S16320F-7TL") (footprint "Package_SO:TSOP-II-54_22.2x10.16mm_P0.8mm") + ) + (path "/a73f4f5a-6e4d-472e-9b51-954e3d116bd7" + (reference "X1") (unit 1) (value "ECS-3225MV-120-CN") (footprint "Oscillator:Oscillator_SMD_SeikoEpson_SG8002CE-4Pin_3.2x2.5mm") + ) + (path "/fd95e6e1-2b37-4604-8f85-981efac5e15c" + (reference "X2") (unit 1) (value "ECS-3225MV-500-BN") (footprint "Oscillator:Oscillator_SMD_SeikoEpson_SG8002CE-4Pin_3.2x2.5mm") + ) + (path "/c229caf9-bd8e-4df4-8266-2d39e81a3f5d" + (reference "Y1") (unit 1) (value "FC-135") (footprint "Crystal:Crystal_SMD_3215-2Pin_3.2x1.5mm") + ) + ) +) diff --git a/hw/shell/sc64_shell.f3d b/hw/shell/sc64_shell.f3d new file mode 100644 index 0000000..101016a Binary files /dev/null and b/hw/shell/sc64_shell.f3d differ diff --git a/hw/shell/sc64_shell_back.stl b/hw/shell/sc64_shell_back.stl new file mode 100644 index 0000000..6de06c5 Binary files /dev/null and b/hw/shell/sc64_shell_back.stl differ diff --git a/hw/shell/sc64_shell_front.stl b/hw/shell/sc64_shell_front.stl new file mode 100644 index 0000000..7de72e6 Binary files /dev/null and b/hw/shell/sc64_shell_front.stl differ diff --git a/sw/n64/.gitignore b/sw/bootloader/.gitignore similarity index 100% rename from sw/n64/.gitignore rename to sw/bootloader/.gitignore diff --git a/sw/bootloader/Makefile b/sw/bootloader/Makefile new file mode 100644 index 0000000..bdbb28a --- /dev/null +++ b/sw/bootloader/Makefile @@ -0,0 +1,95 @@ +TOOLCHAIN = mips64-elf- +CC = $(TOOLCHAIN)gcc +CXX = $(TOOLCHAIN)g++ +OBJCOPY = $(TOOLCHAIN)objcopy +OBJDUMP = $(TOOLCHAIN)objdump +SIZE = $(TOOLCHAIN)size +PYTHON = python3 + +FLAGS = -march=vr4300 -mtune=vr4300 $(USER_FLAGS) +CFLAGS = -Os -Wall -ffunction-sections -fdata-sections -ffreestanding -MMD -MP +ASFLAGS = -Wa,-I$(N64_INST)/mips64-elf/lib +LDFLAGS = -lc -nostartfiles -Wl,--gc-sections + +SRC_DIR = src +ASSET_DIR = assets +BUILD_DIR = build + +SRC_FILES = \ + startup.S \ + boot.c \ + crc32.c \ + display.c \ + error.c \ + exception.c \ + exception.S \ + font.c \ + init.c \ + interrupt.c \ + io.c \ + ipl2.S \ + main.c \ + menu.c \ + sc64.c \ + syscalls.c \ + test.c \ + version.c \ + fatfs/diskio.c \ + fatfs/ff.c \ + fatfs/ffsystem.c \ + fatfs/ffunicode.c + +ASSET_FILES = \ + sc64_logo_640_240_dimmed.png + +SRCS = $(SRC_FILES) $(ASSET_FILES) +SRC_OBJS = $(patsubst %,%.o,$(SRC_FILES)) +ASSET_OBJS = $(patsubst %,%.asset.o,$(basename $(ASSET_FILES))) +OBJS = $(addprefix $(BUILD_DIR)/,$(notdir $(SRC_OBJS) $(ASSET_OBJS))) +DEPS = $(OBJS:.o=.d) +VPATH = $(SRC_DIR) $(SRC_DIR)/fatfs $(ASSET_DIR) + +$(@info $(shell mkdir -p ./$(BUILD_DIR) &> /dev/null)) + +$(BUILD_DIR)/%.S.o: %.S + $(CC) -x assembler-with-cpp $(FLAGS) $(ASFLAGS) $(CFLAGS) -c $< -o $@ + +$(BUILD_DIR)/%.c.o: %.c + $(CC) $(FLAGS) $(CFLAGS) -c $< -o $@ + +$(BUILD_DIR)/%.asset: $(ASSET_DIR)/%.png + $(PYTHON) tools/asset_converter.py $< $@ + +$(BUILD_DIR)/%.asset.o: $(BUILD_DIR)/%.asset $(ASSET_DIR)/assets.S + @sed -e "s,@sym@,$*,g" -e "s,@file@,$<," < $(ASSET_DIR)/assets.S | $(CC) -x assembler-with-cpp $(FLAGS) $(ASFLAGS) $(CFLAGS) -c - -o $@ + +$(BUILD_DIR)/bootloader.elf: $(OBJS) N64.ld + $(CXX) $(FLAGS) $(LDFLAGS) -TN64.ld $(OBJS) -o $@ + @$(OBJDUMP) -S $@ > $(BUILD_DIR)/bootloader.lst + +$(BUILD_DIR)/bootloader.bin: $(BUILD_DIR)/bootloader.elf + @$(OBJCOPY) -O binary $< $@ + @chksum64 $@ > /dev/null + @truncate --size=1028k $@ + +$(BUILD_DIR)/bootloader.hex: $(BUILD_DIR)/bootloader.bin + @$(OBJCOPY) -I binary -O ihex $< $@ + +print_size: $(BUILD_DIR)/bootloader.elf + @echo 'Size of modules:' + @$(SIZE) -B -d -t --common $(OBJS) + @echo 'Size of bootloader:' + @$(SIZE) -B -d $< + +all: $(BUILD_DIR)/bootloader.hex print_size + +clean: + @rm -rf ./$(BUILD_DIR)/* + +$(BUILD_DIR)/version.c.o: .FORCE + +.FORCE: + +.PHONY: .FORCE all clean print_size + +-include $(DEPS) diff --git a/sw/bootloader/N64.ld b/sw/bootloader/N64.ld new file mode 100644 index 0000000..1707375 --- /dev/null +++ b/sw/bootloader/N64.ld @@ -0,0 +1,57 @@ +MEMORY { + framebuffer (rw) : org = 0x8026A000, len = 600k + ram (rwx) : org = 0x80300000, len = 1M + rom (r) : org = 0xB0000000, len = 1028k +} + +ENTRY(entry_handler) + +__exception_stack_size = 8k; +__stack_size = 16k; + +SECTIONS { + .boot : { + KEEP(*(.text.rom_header)); + KEEP(*(.text.ipl3)); + } > rom + + .framebuffer (NOLOAD) : SUBALIGN(64) { + *(.framebuffer .framebuffer.*) + } > framebuffer + + .text : SUBALIGN(4) { + *(.text.entry_handler) + *(.text .text.* .gnu.linkonce.t.*) + *(.assets .assets.*) + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.data .data.* .gnu.linkonce.d.*) + _gp = . + 0x8000; + *(.sdata .sdata.* .gnu.linkonce.s.*) + *(.lit8 .lit4) + } > ram AT > rom + + .bss : { + . = ALIGN(8); + _sbss = .; + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon .scommon.*) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = .; + } > ram + + _sheap = .; + . = ORIGIN(ram) + LENGTH(ram) - __exception_stack_size - __stack_size; + _eheap = .; + + . += __exception_stack_size; + _esp = .; + + . += __stack_size; + _sp = .; + + /DISCARD/ : { + *(.MIPS.*) + } +} diff --git a/sw/bootloader/assets/assets.S b/sw/bootloader/assets/assets.S new file mode 100644 index 0000000..8c43d78 --- /dev/null +++ b/sw/bootloader/assets/assets.S @@ -0,0 +1,4 @@ +.section .assets.@sym@ +.global assets_@sym@ +assets_@sym@: + .incbin "@file@" diff --git a/sw/bootloader/assets/assets.h b/sw/bootloader/assets/assets.h new file mode 100644 index 0000000..d87d654 --- /dev/null +++ b/sw/bootloader/assets/assets.h @@ -0,0 +1,11 @@ +#ifndef ASSETS_H__ +#define ASSETS_H__ + + +#include + + +extern const uint32_t assets_sc64_logo_640_240_dimmed __attribute__((section(".assets"))); + + +#endif diff --git a/sw/bootloader/assets/sc64_logo_640_240_dimmed.png b/sw/bootloader/assets/sc64_logo_640_240_dimmed.png new file mode 100644 index 0000000..e31e936 Binary files /dev/null and b/sw/bootloader/assets/sc64_logo_640_240_dimmed.png differ diff --git a/sw/n64/src/boot.c b/sw/bootloader/src/boot.c similarity index 88% rename from sw/n64/src/boot.c rename to sw/bootloader/src/boot.c index 756aa93..0b540d4 100644 --- a/sw/n64/src/boot.c +++ b/sw/bootloader/src/boot.c @@ -1,7 +1,6 @@ #include "boot.h" #include "crc32.h" -#include "sc64.h" -#include "sys.h" +#include "io.h" extern uint32_t ipl2 __attribute__((section(".data"))); @@ -21,6 +20,7 @@ static const ipl3_crc32_t ipl3_crc32[] = { { .crc32 = 0x0B050EE0, .seed = 0x78, .version = 0 }, // x103 { .crc32 = 0x98BC2C86, .seed = 0x91, .version = 0 }, // x105 { .crc32 = 0xACC8580A, .seed = 0x85, .version = 0 }, // x106 + { .crc32 = 0x0E018159, .seed = 0xDD, .version = 0 }, // 5167 { .crc32 = 0x10C68B18, .seed = 0xDD, .version = 0 }, // NDXJ0 { .crc32 = 0xBC605D0A, .seed = 0xDD, .version = 0 }, // NDDJ0 { .crc32 = 0x502C4466, .seed = 0xDD, .version = 0 }, // NDDJ1 @@ -58,7 +58,6 @@ bool boot_get_tv_type (boot_info_t *info) { break; default: - LOG_E("Unknown region: [0x%02X]\r\n", region); return false; } @@ -68,14 +67,9 @@ bool boot_get_tv_type (boot_info_t *info) { bool boot_get_cic_seed_version (boot_info_t *info) { io32_t *base = boot_get_device_base(info); - uint32_t ipl3[1008]; + uint32_t ipl3[1008] __attribute__((aligned(8))); - io32_t *ipl3_src = &base[16]; - uint32_t *ipl3_dst = ipl3; - - for (int i = 0; i < sizeof(ipl3); i += sizeof(uint32_t)) { - *ipl3_dst++ = pi_io_read(ipl3_src++); - } + pi_dma_read(&base[16], ipl3, sizeof(ipl3)); uint32_t crc32 = crc32_calculate(ipl3, sizeof(ipl3)); @@ -87,14 +81,10 @@ bool boot_get_cic_seed_version (boot_info_t *info) { } } - LOG_E("Unknown IPL3 CRC32: [0x%08lX]\r\n", crc32); - return false; } void boot (boot_info_t *info) { - c0_set_status(C0_SR_CU1 | C0_SR_CU0 | C0_SR_FR); - OS_INFO->mem_size_6105 = OS_INFO->mem_size; while (!(io_read(&SP->SR) & SP_SR_HALT)); diff --git a/sw/n64/src/boot.h b/sw/bootloader/src/boot.h similarity index 60% rename from sw/n64/src/boot.h rename to sw/bootloader/src/boot.h index 09e3e1c..504e379 100644 --- a/sw/n64/src/boot.h +++ b/sw/bootloader/src/boot.h @@ -32,23 +32,6 @@ typedef struct { } boot_info_t; -typedef struct { - uint32_t tv_type; - uint32_t device_type; - uint32_t device_base; - uint32_t reset_type; - uint32_t cic_id; - uint32_t version; - uint32_t mem_size; - uint8_t app_nmi_buffer[64]; - uint32_t __reserved_1[37]; - uint32_t mem_size_6105; -} os_info_t; - -#define OS_INFO_BASE (0x80000300UL) -#define OS_INFO ((os_info_t *) OS_INFO_BASE) - - bool boot_get_tv_type (boot_info_t *info); bool boot_get_cic_seed_version (boot_info_t *info); void boot (boot_info_t *info); diff --git a/sw/n64/src/crc32.c b/sw/bootloader/src/crc32.c similarity index 100% rename from sw/n64/src/crc32.c rename to sw/bootloader/src/crc32.c diff --git a/sw/n64/src/crc32.h b/sw/bootloader/src/crc32.h similarity index 100% rename from sw/n64/src/crc32.h rename to sw/bootloader/src/crc32.h diff --git a/sw/bootloader/src/display.c b/sw/bootloader/src/display.c new file mode 100644 index 0000000..2288d58 --- /dev/null +++ b/sw/bootloader/src/display.c @@ -0,0 +1,148 @@ +#include +#include "display.h" +#include "font.h" +#include "io.h" + + +#define SCREEN_WIDTH (640) +#define SCREEN_HEIGHT (240) +#define BORDER_WIDTH (64) +#define BORDER_HEIGHT (24) + +#define BACKGROUND_COLOR (0x00000000UL) +#define TEXT_COLOR (0xFFFFFFFFUL) +#define LINE_SPACING (2) + + +static io32_t display_framebuffer[SCREEN_WIDTH * SCREEN_HEIGHT] __attribute__((section(".framebuffer"))); +static int char_x; +static int char_y; +static const vi_regs_t vi_config[] = {{ + .CR = ( + VI_CR_PIXEL_ADVANCE_1 | + VI_CR_PIXEL_ADVANCE_0 | + VI_CR_ANTIALIAS_1 | + VI_CR_ANTIALIAS_0 | + VI_CR_TYPE_32 + ), + .H_WIDTH = SCREEN_WIDTH, + .V_INTR = 0x000003FF, + .CURR_LINE = 0x00000000, + .TIMING = 0x0404233A, + .V_SYNC = 0x00000271, + .H_SYNC = 0x00150C69, + .H_SYNC_LEAP = 0x0C6F0C6E, + .H_LIMITS = 0x00800300, + .V_LIMITS = 0x005D023D, + .COLOR_BURST = 0x00090268, + .H_SCALE = 0x00000400, + .V_SCALE = 0x00000400, +}, { + .CR = ( + VI_CR_PIXEL_ADVANCE_1 | + VI_CR_PIXEL_ADVANCE_0 | + VI_CR_ANTIALIAS_1 | + VI_CR_ANTIALIAS_0 | + VI_CR_TYPE_32 + ), + .H_WIDTH = SCREEN_WIDTH, + .V_INTR = 0x000003FF, + .CURR_LINE = 0x00000000, + .TIMING = 0x03E52239, + .V_SYNC = 0x0000020D, + .H_SYNC = 0x00000C15, + .H_SYNC_LEAP = 0x0C150C15, + .H_LIMITS = 0x006C02EC, + .V_LIMITS = 0x00230203, + .COLOR_BURST = 0x000E0204, + .H_SCALE = 0x00000400, + .V_SCALE = 0x00000400, +}}; + + +static void display_draw_character (char c) { + if (c == '\n') { + char_x = BORDER_WIDTH; + char_y += FONT_HEIGHT + LINE_SPACING; + return; + } + + if ((char_x + FONT_WIDTH) > (SCREEN_WIDTH - BORDER_WIDTH)) { + char_x = BORDER_WIDTH; + char_y += FONT_HEIGHT + LINE_SPACING; + } + + if ((c < ' ') || (c > '~')) { + c = '\x7F'; + } + + for (int i = 0; i < (FONT_WIDTH * FONT_HEIGHT); i++) { + int c_x = char_x + (i % FONT_WIDTH); + int c_y = char_y + (i / FONT_WIDTH); + + if ((c_x >= (SCREEN_WIDTH - BORDER_WIDTH)) || (c_y >= (SCREEN_HEIGHT - BORDER_HEIGHT))) { + break; + } + + if (font_data[c - ' '][i / 8] & (1 << (i % 8))) { + int screen_offset = c_x + (c_y * SCREEN_WIDTH); + io_write(&display_framebuffer[screen_offset], TEXT_COLOR); + } + } + + char_x += FONT_WIDTH; +} + +static void display_draw_string (const char *s) { + while (*s != '\0') { + display_draw_character(*s++); + } +} + + +void display_init (uint32_t *background) { + const vi_regs_t *cfg = &vi_config[OS_INFO->tv_type]; + + char_x = BORDER_WIDTH; + char_y = BORDER_HEIGHT; + + if (background == NULL) { + for (int i = 0; i < (SCREEN_WIDTH * SCREEN_HEIGHT); i++) { + io_write(&display_framebuffer[i], BACKGROUND_COLOR); + } + } else { + for (int i = 0; i < (SCREEN_WIDTH * SCREEN_HEIGHT); i++) { + io_write(&display_framebuffer[i], *background++); + } + } + + io_write(&VI->MADDR, (uint32_t) (display_framebuffer)); + io_write(&VI->H_WIDTH, cfg->H_WIDTH); + io_write(&VI->V_INTR, cfg->V_INTR); + io_write(&VI->CURR_LINE, cfg->CURR_LINE); + io_write(&VI->TIMING, cfg->TIMING); + io_write(&VI->V_SYNC, cfg->V_SYNC); + io_write(&VI->H_SYNC, cfg->H_SYNC); + io_write(&VI->H_SYNC_LEAP, cfg->H_SYNC_LEAP); + io_write(&VI->H_LIMITS, cfg->H_LIMITS); + io_write(&VI->V_LIMITS, cfg->V_LIMITS); + io_write(&VI->COLOR_BURST, cfg->COLOR_BURST); + io_write(&VI->H_SCALE, cfg->H_SCALE); + io_write(&VI->V_SCALE, cfg->V_SCALE); + io_write(&VI->CR, cfg->CR); +} + +void display_vprintf (const char *fmt, va_list args) { + char line[256]; + + vsniprintf(line, sizeof(line), fmt, args); + display_draw_string(line); +} + +void display_printf (const char* fmt, ...) { + va_list args; + + va_start(args, fmt); + display_vprintf(fmt, args); + va_end(args); +} diff --git a/sw/bootloader/src/display.h b/sw/bootloader/src/display.h new file mode 100644 index 0000000..0ef73e3 --- /dev/null +++ b/sw/bootloader/src/display.h @@ -0,0 +1,14 @@ +#ifndef DISPLAY_H__ +#define DISPLAY_H__ + + +#include +#include + + +void display_init (uint32_t *background); +void display_vprintf (const char *fmt, va_list args); +void display_printf (const char* fmt, ...); + + +#endif diff --git a/sw/bootloader/src/error.c b/sw/bootloader/src/error.c new file mode 100644 index 0000000..c76c080 --- /dev/null +++ b/sw/bootloader/src/error.c @@ -0,0 +1,13 @@ +#include +#include "exception.h" + + +void error_display (const char *fmt, ...) { + va_list args; + + va_start(args, fmt); + EXCEPTION_TRIGGER(TRIGGER_CODE_ERROR); + va_end(args); + + while (1); +} diff --git a/sw/bootloader/src/error.h b/sw/bootloader/src/error.h new file mode 100644 index 0000000..af9a504 --- /dev/null +++ b/sw/bootloader/src/error.h @@ -0,0 +1,8 @@ +#ifndef ERROR_H__ +#define ERROR_H__ + + +void error_display (const char *fmt, ...); + + +#endif diff --git a/sw/bootloader/src/exception.S b/sw/bootloader/src/exception.S new file mode 100644 index 0000000..0919434 --- /dev/null +++ b/sw/bootloader/src/exception.S @@ -0,0 +1,235 @@ +#include "vr4300.h" + + +#define WATCHDOG_TIMEOUT (5 * (93750000UL / 2)) + +#define VECTOR_LOCATION (0xA0000000UL) +#define VECTOR_SIZE (0x80) +#define VECTOR_NUM (4) + +#define AT_OFFSET (8) +#define V0_OFFSET (16) +#define V1_OFFSET (24) +#define A0_OFFSET (32) +#define A1_OFFSET (40) +#define A2_OFFSET (48) +#define A3_OFFSET (56) +#define T0_OFFSET (64) +#define T1_OFFSET (72) +#define T2_OFFSET (80) +#define T3_OFFSET (88) +#define T4_OFFSET (96) +#define T5_OFFSET (104) +#define T6_OFFSET (112) +#define T7_OFFSET (120) +#define S0_OFFSET (128) +#define S1_OFFSET (136) +#define S2_OFFSET (144) +#define S3_OFFSET (152) +#define S4_OFFSET (160) +#define S5_OFFSET (168) +#define S6_OFFSET (176) +#define S7_OFFSET (184) +#define T8_OFFSET (192) +#define T9_OFFSET (200) +#define K0_OFFSET (208) +#define K1_OFFSET (216) +#define GP_OFFSET (224) +#define SP_OFFSET (232) +#define S8_OFFSET (240) +#define RA_OFFSET (248) +#define C0_STATUS_OFFSET (256) +#define C0_CAUSE_OFFSET (260) +#define C0_EPC_OFFSET (264) +#define C0_BADVADDR_OFFSET (272) +#define SAVE_REGISTERS_SIZE (280) + + +.section .text.exception_handler +exception_handler: + .set noat + la $k0, (_esp - SAVE_REGISTERS_SIZE) + sd $at, AT_OFFSET($k0) + sd $v0, V0_OFFSET($k0) + sd $v1, V1_OFFSET($k0) + sd $a0, A0_OFFSET($k0) + sd $a1, A1_OFFSET($k0) + sd $a2, A2_OFFSET($k0) + sd $a3, A3_OFFSET($k0) + sd $t0, T0_OFFSET($k0) + sd $t1, T1_OFFSET($k0) + sd $t2, T2_OFFSET($k0) + sd $t3, T3_OFFSET($k0) + sd $t4, T4_OFFSET($k0) + sd $t5, T5_OFFSET($k0) + sd $t6, T6_OFFSET($k0) + sd $t7, T7_OFFSET($k0) + sd $s0, S0_OFFSET($k0) + sd $s1, S1_OFFSET($k0) + sd $s2, S2_OFFSET($k0) + sd $s3, S3_OFFSET($k0) + sd $s4, S4_OFFSET($k0) + sd $s5, S5_OFFSET($k0) + sd $s6, S6_OFFSET($k0) + sd $s7, S7_OFFSET($k0) + sd $t8, T8_OFFSET($k0) + sd $t9, T9_OFFSET($k0) + sd $gp, GP_OFFSET($k0) + sd $sp, SP_OFFSET($k0) + sd $s8, S8_OFFSET($k0) + sd $ra, RA_OFFSET($k0) + .set at + + move $sp, $k0 + +exception_check_type: + mfc0 $a0, C0_CAUSE + sw $a0, C0_CAUSE_OFFSET($k0) + move $a1, $a0 + move $t0, $a0 + andi $t0, C0_CR_IP7 + andi $a0, C0_CR_EC_MASK + srl $a0, $a0, C0_CR_EC_BIT + andi $a1, C0_CR_IP_MASK + srl $a1, $a1, C0_CR_IP_BIT + bne $t0, $zero, exception_fatal + beq $a0, $zero, exception_interrupt + +exception_fatal: + sd $k0, K0_OFFSET($k0) + sd $k1, K1_OFFSET($k0) + mfc0 $t0, C0_STATUS + sw $t0, C0_STATUS_OFFSET($k0) + dmfc0 $t0, C0_EPC + sd $t0, C0_EPC_OFFSET($k0) + dmfc0 $t0, C0_BADVADDR + sd $t0, C0_BADVADDR_OFFSET($k0) + move $a2, $k0 + la $t1, exception_fatal_handler + jalr $t1 + ld $t0, C0_EPC_OFFSET($k0) + dmtc0 $t0, C0_EPC + j exception_restore + +exception_interrupt: + la $t1, exception_interrupt_handler + jalr $t1 + +exception_restore: + .set noat + ld $at, AT_OFFSET($k0) + ld $v0, V0_OFFSET($k0) + ld $v1, V1_OFFSET($k0) + ld $a0, A0_OFFSET($k0) + ld $a1, A1_OFFSET($k0) + ld $a2, A2_OFFSET($k0) + ld $a3, A3_OFFSET($k0) + ld $t0, T0_OFFSET($k0) + ld $t1, T1_OFFSET($k0) + ld $t2, T2_OFFSET($k0) + ld $t3, T3_OFFSET($k0) + ld $t4, T4_OFFSET($k0) + ld $t5, T5_OFFSET($k0) + ld $t6, T6_OFFSET($k0) + ld $t7, T7_OFFSET($k0) + ld $s0, S0_OFFSET($k0) + ld $s1, S1_OFFSET($k0) + ld $s2, S2_OFFSET($k0) + ld $s3, S3_OFFSET($k0) + ld $s4, S4_OFFSET($k0) + ld $s5, S5_OFFSET($k0) + ld $s6, S6_OFFSET($k0) + ld $s7, S7_OFFSET($k0) + ld $t8, T8_OFFSET($k0) + ld $t9, T9_OFFSET($k0) + ld $gp, GP_OFFSET($k0) + ld $sp, SP_OFFSET($k0) + ld $s8, S8_OFFSET($k0) + ld $ra, RA_OFFSET($k0) + .set at + + eret + + +.section .text.exception_vector +exception_vector: + .set noreorder + la $k0, exception_handler + jalr $k1, $k0 + nop + .equ exception_vector_size, (. - exception_vector) + .set reorder + + +.section .text.exception_install +exception_install: + .global exception_install + la $t0, exception_vector + li $t1, VECTOR_LOCATION + li $t2, (VECTOR_SIZE * VECTOR_NUM) + add $t2, $t2, $t1 +1: + move $t3, $t0 + move $t4, $t1 + li $t5, exception_vector_size + add $t5, $t5, $t4 +2: + lw $t6, 0($t3) + addiu $t3, 4 + sw $t6, 0($t4) + addiu $t4, 4 + bne $t4, $t5, 2b + addiu $t1, VECTOR_SIZE + bne $t1, $t2, 1b + li $t0, VECTOR_LOCATION + li $t1, (VECTOR_SIZE * VECTOR_NUM) + add $t1, $t0, $t1 +3: + cache HIT_INVALIDATE_I, 0($t0) + addiu $t0, CACHE_LINE_SIZE_I + bne $t0, $t1, 3b + jr $ra + + +.section .text.exception_enable_interrupts +exception_enable_interrupts: + .global exception_enable_interrupts + mfc0 $t0, C0_STATUS + li $t1, C0_SR_IE + or $t0, $t0, $t1 + mtc0 $t0, C0_STATUS + jr $ra + + +.section .text.exception_disable_interrupts +exception_disable_interrupts: + .global exception_disable_interrupts + mfc0 $t0, C0_STATUS + li $t1, ~(C0_SR_IE) + and $t0, $t0, $t1 + mtc0 $t0, C0_STATUS + jr $ra + + +.section .text.exception_enable_watchdog +exception_enable_watchdog: + .global exception_enable_watchdog + mtc0 $zero, C0_COUNT + li $t1, WATCHDOG_TIMEOUT + mtc0 $t1, C0_COMPARE + mfc0 $t0, C0_STATUS + li $t1, C0_SR_IM7 + or $t0, $t0, $t1 + mtc0 $t0, C0_STATUS + jr $ra + + +.section .text.exception_disable_watchdog +exception_disable_watchdog: + .global exception_disable_watchdog + mfc0 $t0, C0_STATUS + li $t1, ~(C0_SR_IM7) + and $t0, $t0, $t1 + mtc0 $t0, C0_STATUS + mtc0 $zero, C0_COMPARE + jr $ra diff --git a/sw/bootloader/src/exception.c b/sw/bootloader/src/exception.c new file mode 100644 index 0000000..9c967ee --- /dev/null +++ b/sw/bootloader/src/exception.c @@ -0,0 +1,83 @@ +#include +#include "display.h" +#include "exception_regs.h" +#include "exception.h" +#include "io.h" +#include "version.h" +#include "vr4300.h" +#include "../assets/assets.h" + + +#define EXCEPTION_INTERRUPT (0) +#define EXCEPTION_SYSCALL (8) + +#define INTERRUPT_MASK_TIMER (1 << 7) + +#define SYSCALL_CODE_MASK (0x03FFFFC0UL) +#define SYSCALL_CODE_BIT (6) + + +static const char *exception_get_description (uint8_t exception_code) { + switch (exception_code) { + case 0: return "Interrupt"; + case 1: return "TLB Modification exception"; + case 2: return "TLB Miss exception (load or instruction fetch)"; + case 3: return "TLB Miss exception (store)"; + case 4: return "Address Error exception (load or instruction fetch)"; + case 5: return "Address Error exception (store)"; + case 6: return "Bus Error exception (instruction fetch)"; + case 7: return "Bus Error exception (data reference: load or store)"; + case 8: return "Syscall exception"; + case 9: return "Breakpoint exception"; + case 10: return "Reserved Instruction exception"; + case 11: return "Coprocessor Unusable exception"; + case 12: return "Arithmetic Overflow exception"; + case 13: return "Trap exception"; + case 15: return "Floating-Point exception"; + case 23: return "Watch exception"; + } + + return "Unknown exception"; +} + + +void exception_fatal_handler (uint32_t exception_code, uint32_t interrupt_mask, exception_t *e) { + version_t *version = version_get(); + uint32_t *instruction_address = (((uint32_t *) (e->epc.u32)) + ((e->cr & C0_CR_BD) ? 1 : 0)); + + display_init((uint32_t *) (&assets_sc64_logo_640_240_dimmed)); + + display_printf("branch: %s | tag: %s\n", version->git_branch, version->git_tag); + display_printf("sha: %s\n", version->git_sha); + display_printf("%s\n\n", version->git_message); + + display_printf("%s\n", exception_get_description(exception_code)); + display_printf(" pc: 0x%08lX sr: 0x%08lX cr: 0x%08lX va: 0x%08lX\n", e->epc.u32, e->sr, e->cr, e->badvaddr.u32); + display_printf(" zr: 0x%08lX at: 0x%08lX v0: 0x%08lX v1: 0x%08lX\n", e->zr.u32, e->at.u32, e->v0.u32, e->v1.u32); + display_printf(" a0: 0x%08lX a1: 0x%08lX a2: 0x%08lX a3: 0x%08lX\n", e->a0.u32, e->a1.u32, e->a2.u32, e->a3.u32); + display_printf(" t0: 0x%08lX t1: 0x%08lX t2: 0x%08lX t3: 0x%08lX\n", e->t0.u32, e->t1.u32, e->t2.u32, e->t3.u32); + display_printf(" t4: 0x%08lX t5: 0x%08lX t6: 0x%08lX t7: 0x%08lX\n", e->t4.u32, e->t5.u32, e->t6.u32, e->t7.u32); + display_printf(" s0: 0x%08lX s1: 0x%08lX s2: 0x%08lX s3: 0x%08lX\n", e->s0.u32, e->s1.u32, e->s2.u32, e->s3.u32); + display_printf(" s4: 0x%08lX s5: 0x%08lX s6: 0x%08lX s7: 0x%08lX\n", e->s4.u32, e->s5.u32, e->s6.u32, e->s7.u32); + display_printf(" t8: 0x%08lX t9: 0x%08lX k0: 0x%08lX k1: 0x%08lX\n", e->t8.u32, e->t9.u32, e->k0.u32, e->k1.u32); + display_printf(" gp: 0x%08lX sp: 0x%08lX s8: 0x%08lX ra: 0x%08lX\n\n", e->gp.u32, e->sp.u32, e->s8.u32, e->ra.u32); + + if (exception_code == EXCEPTION_INTERRUPT) { + if (interrupt_mask & INTERRUPT_MASK_TIMER) { + exception_disable_watchdog(); + display_printf("Still loading after 5 second limit...\n\n"); + return; + } + } else if (exception_code == EXCEPTION_SYSCALL) { + uint32_t code = (((*instruction_address) & SYSCALL_CODE_MASK) >> SYSCALL_CODE_BIT); + + if (code == TRIGGER_CODE_ERROR) { + const char *fmt = (const char *) (e->a0.u32); + va_list args = *((va_list *) (e->sp.u32)); + display_vprintf(fmt, args); + display_printf("\n"); + } + } + + while (1); +} diff --git a/sw/bootloader/src/exception.h b/sw/bootloader/src/exception.h new file mode 100644 index 0000000..7b3873e --- /dev/null +++ b/sw/bootloader/src/exception.h @@ -0,0 +1,17 @@ +#ifndef EXCEPTION_H__ +#define EXCEPTION_H__ + + +#define TRIGGER_CODE_ERROR (0) + +#define EXCEPTION_TRIGGER(code) { asm volatile ("syscall %[c]\n" :: [c] "i" (code)); } + + +void exception_install (void); +void exception_enable_interrupts (void); +void exception_disable_interrupts (void); +void exception_enable_watchdog (void); +void exception_disable_watchdog (void); + + +#endif diff --git a/sw/bootloader/src/exception_regs.h b/sw/bootloader/src/exception_regs.h new file mode 100644 index 0000000..6e23421 --- /dev/null +++ b/sw/bootloader/src/exception_regs.h @@ -0,0 +1,56 @@ +#ifndef EXCEPTION_REGS_H__ +#define EXCEPTION_REGS_H__ + + +#include + + +typedef union { + uint64_t u64; + struct { + uint32_t u32_h; + uint32_t u32; + }; +} uint64_32_t; + +typedef struct { + uint64_32_t zr; + uint64_32_t at; + uint64_32_t v0; + uint64_32_t v1; + uint64_32_t a0; + uint64_32_t a1; + uint64_32_t a2; + uint64_32_t a3; + uint64_32_t t0; + uint64_32_t t1; + uint64_32_t t2; + uint64_32_t t3; + uint64_32_t t4; + uint64_32_t t5; + uint64_32_t t6; + uint64_32_t t7; + uint64_32_t s0; + uint64_32_t s1; + uint64_32_t s2; + uint64_32_t s3; + uint64_32_t s4; + uint64_32_t s5; + uint64_32_t s6; + uint64_32_t s7; + uint64_32_t t8; + uint64_32_t t9; + uint64_32_t k0; + uint64_32_t k1; + uint64_32_t gp; + uint64_32_t sp; + uint64_32_t s8; + uint64_32_t ra; + uint32_t sr; + uint32_t cr; + uint64_32_t epc; + uint64_32_t badvaddr; +} exception_t; + + +#endif diff --git a/sw/n64/src/fatfs/00history.txt b/sw/bootloader/src/fatfs/00history.txt similarity index 100% rename from sw/n64/src/fatfs/00history.txt rename to sw/bootloader/src/fatfs/00history.txt diff --git a/sw/n64/src/fatfs/00readme.txt b/sw/bootloader/src/fatfs/00readme.txt similarity index 100% rename from sw/n64/src/fatfs/00readme.txt rename to sw/bootloader/src/fatfs/00readme.txt diff --git a/sw/bootloader/src/fatfs/diskio.c b/sw/bootloader/src/fatfs/diskio.c new file mode 100644 index 0000000..445496a --- /dev/null +++ b/sw/bootloader/src/fatfs/diskio.c @@ -0,0 +1,119 @@ +#include +#include "ff.h" +#include "diskio.h" +#include "../io.h" +#include "../sc64.h" +#include "../error.h" + + +#define SD_SECTOR_SIZE (512) +#define BUFFER_BLOCKS_MAX (sizeof(SC64_BUFFERS->BUFFER) / SD_SECTOR_SIZE) +#define FROM_BCD(x) ((((x >> 4) & 0x0F) * 10) + (x & 0x0F)) + + +static DSTATUS status = STA_NOINIT; + + +DSTATUS disk_status (BYTE pdrv) { + if (pdrv > 0) { + return STA_NODISK; + } + return status; +} + +DSTATUS disk_initialize (BYTE pdrv) { + if (pdrv > 0) { + return STA_NODISK; + } + if (!sc64_sd_card_init()) { + status &= ~(STA_NOINIT); + } + return status; +} + +DRESULT disk_read (BYTE pdrv, BYTE *buff, LBA_t sector, UINT count) { + if (pdrv > 0) { + return RES_PARERR; + } + uint32_t *physical_address = (uint32_t *) (PHYSICAL(buff)); + if (physical_address < (uint32_t *) (N64_RAM_SIZE)) { + uint8_t aligned_buffer[BUFFER_BLOCKS_MAX * SD_SECTOR_SIZE] __attribute__((aligned(8))); + while (count > 0) { + uint32_t blocks = ((count > BUFFER_BLOCKS_MAX) ? BUFFER_BLOCKS_MAX : count); + size_t length = (blocks * SD_SECTOR_SIZE); + if (sc64_sd_read_sectors((uint32_t *) (SC64_BUFFERS->BUFFER), sector, blocks)) { + return RES_ERROR; + } + if (((uint32_t) (buff) % 8) == 0) { + pi_dma_read((io32_t *) (SC64_BUFFERS->BUFFER), buff, length); + } else { + pi_dma_read((io32_t *) (SC64_BUFFERS->BUFFER), aligned_buffer, length); + memcpy(buff, aligned_buffer, length); + } + buff += length; + sector += blocks; + count -= blocks; + } + } else { + if (sc64_sd_read_sectors(physical_address, sector, count)) { + return RES_ERROR; + } + } + return RES_OK; +} + +#if !FF_FS_READONLY +DRESULT disk_write (BYTE pdrv, const BYTE* buff, LBA_t sector, UINT count) { + if (pdrv > 0) { + return RES_PARERR; + } + uint32_t *physical_address = (uint32_t *) (PHYSICAL(buff)); + if (physical_address < (uint32_t *) (N64_RAM_SIZE)) { + uint8_t aligned_buffer[BUFFER_BLOCKS_MAX * SD_SECTOR_SIZE] __attribute__((aligned(8))); + while (count > 0) { + uint32_t blocks = ((count > BUFFER_BLOCKS_MAX) ? BUFFER_BLOCKS_MAX : count); + size_t length = (blocks * SD_SECTOR_SIZE); + if (((uint32_t) (buff) % 8) == 0) { + pi_dma_write((io32_t *) (SC64_BUFFERS->BUFFER), (void *) (buff), length); + } else { + memcpy(aligned_buffer, buff, length); + pi_dma_write((io32_t *) (SC64_BUFFERS->BUFFER), aligned_buffer, length); + } + if (sc64_sd_write_sectors((uint32_t *) (SC64_BUFFERS->BUFFER), sector, blocks)) { + return RES_ERROR; + } + buff += length; + sector += blocks; + count -= blocks; + } + } else { + if (sc64_sd_write_sectors(physical_address, sector, count)) { + return RES_ERROR; + } + } + return RES_OK; +} +#endif + +DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void *buff) { + if (pdrv > 0) { + return RES_PARERR; + } + if (cmd == CTRL_SYNC) { + return RES_OK; + } + return RES_PARERR; +} + +DWORD get_fattime(void) { + rtc_time_t t; + sc64_get_time(&t); + return ( + ((FROM_BCD(t.year) + 20) << 25) | + (FROM_BCD(t.month) << 21) | + (FROM_BCD(t.day) << 16) | + (FROM_BCD(t.hour) << 11) | + (FROM_BCD(t.minute) << 5) | + (FROM_BCD(t.second) >> 1) + ); +} diff --git a/sw/n64/src/fatfs/diskio.h b/sw/bootloader/src/fatfs/diskio.h similarity index 100% rename from sw/n64/src/fatfs/diskio.h rename to sw/bootloader/src/fatfs/diskio.h diff --git a/sw/n64/src/fatfs/ff.c b/sw/bootloader/src/fatfs/ff.c similarity index 100% rename from sw/n64/src/fatfs/ff.c rename to sw/bootloader/src/fatfs/ff.c diff --git a/sw/n64/src/fatfs/ff.h b/sw/bootloader/src/fatfs/ff.h similarity index 100% rename from sw/n64/src/fatfs/ff.h rename to sw/bootloader/src/fatfs/ff.h diff --git a/sw/n64/src/fatfs/ffconf.h b/sw/bootloader/src/fatfs/ffconf.h similarity index 96% rename from sw/n64/src/fatfs/ffconf.h rename to sw/bootloader/src/fatfs/ffconf.h index 076be51..330c993 100644 --- a/sw/n64/src/fatfs/ffconf.h +++ b/sw/bootloader/src/fatfs/ffconf.h @@ -8,14 +8,14 @@ / Function Configurations /---------------------------------------------------------------------------*/ -#define FF_FS_READONLY 1 +#define FF_FS_READONLY 0 /* This option switches read-only configuration. (0:Read/Write or 1:Read-only) / Read-only configuration removes writing API functions, f_write(), f_sync(), / f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree() / and optional writing functions as well. */ -#define FF_FS_MINIMIZE 1 +#define FF_FS_MINIMIZE 2 /* This option defines minimization level to remove some basic API functions. / / 0: Basic functions are fully enabled. @@ -34,7 +34,7 @@ /* This option switches f_mkfs() function. (0:Disable or 1:Enable) */ -#define FF_USE_FASTSEEK 1 +#define FF_USE_FASTSEEK 0 /* This option switches fast seek function. (0:Disable or 1:Enable) */ @@ -153,7 +153,7 @@ / on character encoding. When LFN is not enabled, these options have no effect. */ -#define FF_FS_RPATH 2 +#define FF_FS_RPATH 0 /* This option configures support for relative path. / / 0: Disable relative path and remove related functions. @@ -166,7 +166,7 @@ / Drive/Volume Configurations /---------------------------------------------------------------------------*/ -#define FF_VOLUMES 2 +#define FF_VOLUMES 1 /* Number of volumes (logical drives) to be used. (1-10) */ @@ -224,7 +224,7 @@ / System Configurations /---------------------------------------------------------------------------*/ -#define FF_FS_TINY 0 +#define FF_FS_TINY 1 /* This option switches tiny buffer configuration. (0:Normal or 1:Tiny) / At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes. / Instead of private sector buffer eliminated from the file object, common sector @@ -237,7 +237,7 @@ / Note that enabling exFAT discards ANSI C (C89) compatibility. */ -#define FF_FS_NORTC 1 +#define FF_FS_NORTC 0 #define FF_NORTC_MON 1 #define FF_NORTC_MDAY 1 #define FF_NORTC_YEAR 2020 diff --git a/sw/n64/src/fatfs/ffsystem.c b/sw/bootloader/src/fatfs/ffsystem.c similarity index 100% rename from sw/n64/src/fatfs/ffsystem.c rename to sw/bootloader/src/fatfs/ffsystem.c diff --git a/sw/n64/src/fatfs/ffunicode.c b/sw/bootloader/src/fatfs/ffunicode.c similarity index 100% rename from sw/n64/src/fatfs/ffunicode.c rename to sw/bootloader/src/fatfs/ffunicode.c diff --git a/sw/bootloader/src/font.c b/sw/bootloader/src/font.c new file mode 100644 index 0000000..0732a3f --- /dev/null +++ b/sw/bootloader/src/font.c @@ -0,0 +1,103 @@ +// Manually converted font "Dogica" from https://www.dafont.com/dogica.font + +#include "font.h" + + +const uint8_t font_data[96][FONT_CHAR_BYTES] = { + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, + { 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, 0x18, 0x00, }, + { 0x00, 0x6C, 0x6C, 0x36, 0x00, 0x00, 0x00, 0x00, }, + { 0x00, 0x6C, 0xFE, 0x6C, 0x6C, 0xFE, 0x6C, 0x00, }, + { 0x00, 0x7C, 0xD6, 0x16, 0x7C, 0xD0, 0xD6, 0x7C, }, + { 0x62, 0x35, 0x37, 0x1A, 0x58, 0xAC, 0xEC, 0x46, }, + { 0x1C, 0x36, 0x36, 0x1C, 0xF6, 0x66, 0xFC, 0x00, }, + { 0x00, 0x30, 0x30, 0x18, 0x00, 0x00, 0x00, 0x00, }, + { 0x30, 0x18, 0x18, 0x18, 0x18, 0x18, 0x30, 0x00, }, + { 0x18, 0x30, 0x30, 0x30, 0x30, 0x30, 0x18, 0x00, }, + { 0x00, 0x18, 0x7E, 0x3C, 0x7E, 0x18, 0x00, 0x00, }, + { 0x00, 0x18, 0x18, 0x7E, 0x18, 0x18, 0x00, 0x00, }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x18, }, + { 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, }, + { 0x60, 0x60, 0x30, 0x30, 0x18, 0x18, 0x0C, 0x0C, }, + { 0x3C, 0x66, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x00, }, + { 0x18, 0x1E, 0x18, 0x18, 0x18, 0x18, 0x7E, 0x00, }, + { 0x3C, 0x66, 0x60, 0x30, 0x18, 0x0C, 0x7E, 0x00, }, + { 0x3E, 0x60, 0x60, 0x3C, 0x60, 0x60, 0x3E, 0x00, }, + { 0x30, 0x38, 0x3C, 0x36, 0x7E, 0x30, 0x30, 0x00, }, + { 0x7E, 0x06, 0x3E, 0x60, 0x60, 0x66, 0x3C, 0x00, }, + { 0x3C, 0x66, 0x06, 0x3E, 0x66, 0x66, 0x3C, 0x00, }, + { 0x7E, 0x66, 0x60, 0x30, 0x18, 0x0C, 0x0C, 0x00, }, + { 0x3C, 0x66, 0x66, 0x3C, 0x66, 0x66, 0x3C, 0x00, }, + { 0x3C, 0x66, 0x66, 0x7C, 0x60, 0x30, 0x1C, 0x00, }, + { 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, }, + { 0x00, 0x00, 0x00, 0x30, 0x00, 0x30, 0x30, 0x18, }, + { 0x00, 0x30, 0x18, 0x0C, 0x18, 0x30, 0x00, 0x00, }, + { 0x00, 0x00, 0xFE, 0x00, 0xFE, 0x00, 0x00, 0x00, }, + { 0x00, 0x18, 0x30, 0x60, 0x30, 0x18, 0x00, 0x00, }, + { 0x3C, 0x66, 0x60, 0x38, 0x0C, 0x00, 0x18, 0x00, }, + { 0x3E, 0x63, 0x7F, 0x7B, 0x3F, 0xC3, 0x7E, 0x00, }, + { 0x3C, 0x66, 0x66, 0x66, 0x7E, 0x66, 0x66, 0x00, }, + { 0x3E, 0x66, 0x66, 0x3E, 0x66, 0x66, 0x3E, 0x00, }, + { 0x3C, 0x66, 0x06, 0x06, 0x06, 0x66, 0x3C, 0x00, }, + { 0x3F, 0x66, 0x66, 0x66, 0x66, 0x66, 0x3E, 0x00, }, + { 0x7E, 0x06, 0x06, 0x3E, 0x06, 0x06, 0x7E, 0x00, }, + { 0x7E, 0x06, 0x06, 0x3E, 0x06, 0x06, 0x06, 0x00, }, + { 0x7C, 0x06, 0x06, 0x76, 0x66, 0x66, 0x7C, 0x00, }, + { 0x66, 0x66, 0x66, 0x7E, 0x66, 0x66, 0x66, 0x00, }, + { 0x3C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x3C, 0x00, }, + { 0x3E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x0E, 0x00, }, + { 0x66, 0x36, 0x1E, 0x1E, 0x36, 0x36, 0x66, 0x00, }, + { 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x7C, 0x00, }, + { 0xC6, 0xC6, 0xEE, 0xFE, 0xC6, 0xC6, 0xC6, 0x00, }, + { 0x66, 0x6E, 0x7E, 0x76, 0x66, 0x66, 0x66, 0x00, }, + { 0x3C, 0x66, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x00, }, + { 0x3E, 0x66, 0x66, 0x3E, 0x06, 0x06, 0x06, 0x00, }, + { 0x3C, 0x66, 0x66, 0x66, 0x6E, 0x36, 0x7C, 0x00, }, + { 0x3E, 0x66, 0x66, 0x3E, 0x36, 0x66, 0x66, 0x00, }, + { 0x3C, 0x66, 0x06, 0x3C, 0x60, 0x66, 0x3C, 0x00, }, + { 0x7E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, }, + { 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x00, }, + { 0x66, 0x66, 0x66, 0x66, 0x3C, 0x3C, 0x18, 0x00, }, + { 0xC3, 0xC3, 0xDB, 0xDB, 0xDB, 0xFF, 0x66, 0x00, }, + { 0x66, 0x66, 0x3C, 0x18, 0x3C, 0x66, 0x66, 0x00, }, + { 0x66, 0x66, 0x66, 0x3C, 0x18, 0x18, 0x18, 0x00, }, + { 0x7E, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x7E, 0x00, }, + { 0x38, 0x18, 0x18, 0x18, 0x18, 0x18, 0x38, 0x00, }, + { 0x0C, 0x0C, 0x18, 0x18, 0x30, 0x30, 0x60, 0x60, }, + { 0x38, 0x30, 0x30, 0x30, 0x30, 0x30, 0x38, 0x00, }, + { 0x00, 0x38, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, }, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, }, + { 0x00, 0x18, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, }, + { 0x00, 0x3C, 0x60, 0x7C, 0x66, 0x66, 0x7C, 0x00, }, + { 0x06, 0x06, 0x3E, 0x66, 0x66, 0x66, 0x3E, 0x00, }, + { 0x00, 0x3C, 0x66, 0x06, 0x06, 0x06, 0x7C, 0x00, }, + { 0x60, 0x60, 0x7C, 0x66, 0x66, 0x66, 0x7C, 0x00, }, + { 0x00, 0x3C, 0x66, 0x7E, 0x06, 0x06, 0x7C, 0x00, }, + { 0x78, 0x0C, 0x0C, 0x3E, 0x0C, 0x0C, 0x0C, 0x00, }, + { 0x00, 0x7C, 0x66, 0x66, 0x66, 0x7C, 0x60, 0x3C, }, + { 0x06, 0x06, 0x3E, 0x6E, 0x66, 0x66, 0x66, 0x00, }, + { 0x18, 0x00, 0x1C, 0x18, 0x18, 0x18, 0x3C, 0x00, }, + { 0x00, 0x3C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x0C, }, + { 0x00, 0x66, 0x36, 0x1E, 0x1E, 0x36, 0x66, 0x00, }, + { 0x00, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x38, 0x00, }, + { 0x00, 0x7E, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0x00, }, + { 0x00, 0x38, 0x6E, 0x66, 0x66, 0x66, 0x66, 0x00, }, + { 0x00, 0x3C, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x00, }, + { 0x00, 0x3E, 0x66, 0x66, 0x66, 0x3E, 0x06, 0x06, }, + { 0x00, 0x7C, 0x66, 0x66, 0x66, 0x7C, 0x60, 0x60, }, + { 0x00, 0x78, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C, 0x00, }, + { 0x00, 0x3C, 0x06, 0x3C, 0x60, 0x66, 0x3C, 0x00, }, + { 0x0C, 0x0C, 0x7C, 0x0C, 0x0C, 0x0C, 0x78, 0x00, }, + { 0x00, 0x66, 0x66, 0x66, 0x66, 0x76, 0x7C, 0x00, }, + { 0x00, 0x66, 0x66, 0x66, 0x3C, 0x3C, 0x18, 0x00, }, + { 0x00, 0xC0, 0xDB, 0xDB, 0xDB, 0xDB, 0x7E, 0x00, }, + { 0x00, 0x66, 0x3C, 0x18, 0x18, 0x3C, 0x66, 0x00, }, + { 0x00, 0x6C, 0x6C, 0x6C, 0x38, 0x30, 0x1C, 0x00, }, + { 0x00, 0x7C, 0x60, 0x30, 0x18, 0x0C, 0x7C, 0x00, }, + { 0x30, 0x58, 0x08, 0x0C, 0x0C, 0x08, 0x58, 0x30, }, + { 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, }, + { 0x18, 0x34, 0x20, 0x60, 0x60, 0x20, 0x34, 0x18, }, + { 0x00, 0x00, 0x00, 0xDC, 0x76, 0x00, 0x00, 0x00, }, + { 0xAA, 0x55, 0xAA, 0x55, 0xAA, 0x55, 0xAA, 0x55, }, +}; diff --git a/sw/bootloader/src/font.h b/sw/bootloader/src/font.h new file mode 100644 index 0000000..350d070 --- /dev/null +++ b/sw/bootloader/src/font.h @@ -0,0 +1,16 @@ +#ifndef FONT_H__ +#define FONT_H__ + + +#include + + +#define FONT_WIDTH (8) +#define FONT_HEIGHT (8) +#define FONT_CHAR_BYTES (8) + + +extern const uint8_t font_data[96][FONT_CHAR_BYTES]; + + +#endif diff --git a/sw/bootloader/src/init.c b/sw/bootloader/src/init.c new file mode 100644 index 0000000..a2e38dc --- /dev/null +++ b/sw/bootloader/src/init.c @@ -0,0 +1,35 @@ +#include "error.h" +#include "exception.h" +#include "io.h" +#include "sc64.h" +#include "test.h" + + +void init (void) { + uint32_t pifram = si_io_read((io32_t *) (&PIFRAM[0x3C])); + si_io_write((io32_t *) (&PIFRAM[0x3C]), pifram | 0x08); + + exception_install(); + + sc64_unlock(); + + if (!sc64_check_presence()) { + error_display("SC64 hardware not detected"); + } + + exception_enable_watchdog(); + exception_enable_interrupts(); + + if (test_check()) { + exception_disable_watchdog(); + test_execute(); + } + + sc64_set_config(CFG_ID_BOOTLOADER_SWITCH, false); +} + +void deinit (void) { + exception_disable_interrupts(); + exception_disable_watchdog(); + sc64_lock(); +} diff --git a/sw/bootloader/src/init.h b/sw/bootloader/src/init.h new file mode 100644 index 0000000..d6c2dc2 --- /dev/null +++ b/sw/bootloader/src/init.h @@ -0,0 +1,9 @@ +#ifndef INIT_H__ +#define INIT_H__ + + +void init (void); +void deinit (void); + + +#endif diff --git a/sw/bootloader/src/interrupt.c b/sw/bootloader/src/interrupt.c new file mode 100644 index 0000000..95d6a47 --- /dev/null +++ b/sw/bootloader/src/interrupt.c @@ -0,0 +1,6 @@ +#include "exception_regs.h" + + +void exception_interrupt_handler (uint32_t exception_code, uint32_t interrupt_mask, exception_t *e) { + while (1); +} diff --git a/sw/bootloader/src/io.c b/sw/bootloader/src/io.c new file mode 100644 index 0000000..d3fa90a --- /dev/null +++ b/sw/bootloader/src/io.c @@ -0,0 +1,80 @@ +#include "io.h" +#include "vr4300.h" + + +static void cache_operation (uint8_t operation, uint8_t line_size, void *address, size_t length) { + uint32_t cache_address = (((uint32_t) (address)) & (~(line_size - 1))); + while (cache_address < ((uint32_t) (address) + length)) { + asm volatile ( + "cache %[operation], (%[cache_address]) \n" :: + [operation] "i" (operation), + [cache_address] "r" (cache_address) + ); + cache_address += line_size; + } +} + +void cache_data_hit_writeback_invalidate (void *address, size_t length) { + cache_operation(HIT_WRITE_BACK_INVALIDATE_D, CACHE_LINE_SIZE_D, address, length); +} + +void cache_data_hit_writeback (void *address, size_t length) { + cache_operation(HIT_WRITE_BACK_D, CACHE_LINE_SIZE_D, address, length); +} + +void cache_inst_hit_invalidate (void *address, size_t length) { + cache_operation(HIT_INVALIDATE_I, CACHE_LINE_SIZE_I, address, length); +} + +uint32_t io_read (io32_t *address) { + io32_t *uncached = UNCACHED(address); + uint32_t value = *uncached; + return value; +} + +void io_write (io32_t *address, uint32_t value) { + io32_t *uncached = UNCACHED(address); + *uncached = value; +} + +uint32_t pi_busy (void) { + return (io_read(&PI->SR) & (PI_SR_IO_BUSY | PI_SR_DMA_BUSY)); +} + +uint32_t pi_io_read (io32_t *address) { + return io_read(address); +} + +void pi_io_write (io32_t *address, uint32_t value) { + io_write(address, value); + while (pi_busy()); +} + +void pi_dma_read (io32_t *address, void *buffer, size_t length) { + cache_data_hit_writeback_invalidate(buffer, length); + io_write(&PI->PADDR, (uint32_t) (PHYSICAL(address))); + io_write(&PI->MADDR, (uint32_t) (PHYSICAL(buffer))); + io_write(&PI->WDMA, length - 1); + while (pi_busy()); +} + +void pi_dma_write (io32_t *address, void *buffer, size_t length) { + cache_data_hit_writeback(buffer, length); + io_write(&PI->PADDR, (uint32_t) (PHYSICAL(address))); + io_write(&PI->MADDR, (uint32_t) (PHYSICAL(buffer))); + io_write(&PI->RDMA, length - 1); + while (pi_busy()); +} + +uint32_t si_busy (void) { + return (io_read(&SI->SR) & (SI_SR_IO_BUSY | SI_SR_DMA_BUSY)); +} + +uint32_t si_io_read (io32_t *address) { + return io_read(address); +} + +void si_io_write (io32_t *address, uint32_t value) { + io_write(address, value); + while (si_busy()); +} diff --git a/sw/n64/src/sys.h b/sw/bootloader/src/io.h similarity index 75% rename from sw/n64/src/sys.h rename to sw/bootloader/src/io.h index 9bf29b1..03d3a18 100644 --- a/sw/n64/src/sys.h +++ b/sw/bootloader/src/io.h @@ -1,5 +1,5 @@ -#ifndef SYS_H__ -#define SYS_H__ +#ifndef IO_H__ +#define IO_H__ #include @@ -12,41 +12,10 @@ typedef volatile uint32_t io32_t; #define ALIGN(value, align) (((value) + ((typeof(value))(align) - 1)) & ~((typeof(value))(align) - 1)) +#define PHYSICAL(address) ((typeof(address)) (((io32_t) (address)) & (0x1FFFFFFFUL))) #define UNCACHED(address) ((typeof(address)) (((io32_t) (address)) | (0xA0000000UL))) -#define CPU_FREQUENCY (93750000UL) - - -#define C0_SR_CU3 (1 << 31) -#define C0_SR_CU2 (1 << 30) -#define C0_SR_CU1 (1 << 29) -#define C0_SR_CU0 (1 << 28) -#define C0_SR_RP (1 << 27) -#define C0_SR_FR (1 << 26) -#define C0_SR_RE (1 << 25) -#define C0_SR_DS_ITS (1 << 24) -#define C0_SR_DS_BEV (1 << 22) -#define C0_SR_DS_TS (1 << 21) -#define C0_SR_DS_SR (1 << 20) -#define C0_SR_DS_CH (1 << 18) -#define C0_SR_DS_CE (1 << 17) -#define C0_SR_DS_DE (1 << 16) -#define C0_SR_IM7 (1 << 15) -#define C0_SR_IM6 (1 << 14) -#define C0_SR_IM5 (1 << 13) -#define C0_SR_IM4 (1 << 12) -#define C0_SR_IM3 (1 << 11) -#define C0_SR_IM2 (1 << 10) -#define C0_SR_IM1 (1 << 9) -#define C0_SR_IM0 (1 << 8) -#define C0_SR_KX (1 << 7) -#define C0_SR_SX (1 << 6) -#define C0_SR_UX (1 << 5) -#define C0_SR_KSU1 (1 << 4) -#define C0_SR_KSU0 (1 << 3) -#define C0_SR_EXR (1 << 2) -#define C0_SR_EXL (1 << 1) -#define C0_SR_IE (1 << 0) +#define N64_RAM_SIZE (0x00800000UL) typedef struct { @@ -179,6 +148,10 @@ typedef struct { #define VI_CR_SERRATE_ON (1 << 6) #define VI_CR_ANTIALIAS_0 (1 << 8) #define VI_CR_ANTIALIAS_1 (1 << 9) +#define VI_CR_PIXEL_ADVANCE_0 (1 << 12) +#define VI_CR_PIXEL_ADVANCE_1 (1 << 13) +#define VI_CR_PIXEL_ADVANCE_2 (1 << 14) +#define VI_CR_PIXEL_ADVANCE_3 (1 << 15) #define VI_CR_DITHER_FILTER_ON (1 << 16) @@ -245,6 +218,8 @@ typedef struct { #define ROM_DDIPL_BASE (0x06000000UL) #define ROM_DDIPL ((io32_t *) ROM_DDIPL_BASE) + + #define ROM_CART_BASE (0x10000000UL) #define ROM_CART ((io32_t *) ROM_CART_BASE) @@ -253,17 +228,67 @@ typedef struct { #define PIFRAM ((io8_t *) PIFRAM_BASE) -void c0_set_status (uint32_t status); -uint32_t c0_get_count (void); -void wait_ms (uint32_t ms); +typedef struct { + io8_t BUFFER[8192]; + io8_t EEPROM[2048]; + io8_t DD_SECTOR[256]; + io8_t FLASHRAM[128]; +} sc64_buffers_t; + +#define SC64_BUFFERS_BASE (0x1FFE0000UL) +#define SC64_BUFFERS ((sc64_buffers_t *) SC64_BUFFERS_BASE) + + +typedef struct { + io32_t SR_CMD; + io32_t DATA[2]; + io32_t VERSION; + io32_t KEY; +} sc64_regs_t; + +#define SC64_REGS_BASE (0x1FFF0000UL) +#define SC64_REGS ((sc64_regs_t *) SC64_REGS_BASE) + +#define SC64_SR_IRQ_PENDING (1 << 29) +#define SC64_SR_CMD_ERROR (1 << 30) +#define SC64_SR_CPU_BUSY (1 << 31) + +#define SC64_KEY_RESET (0x00000000UL) +#define SC64_KEY_UNLOCK_1 (0x5F554E4CUL) +#define SC64_KEY_UNLOCK_2 (0x4F434B5FUL) +#define SC64_KEY_LOCK (0xFFFFFFFFUL) + + +typedef struct { + uint32_t tv_type; + uint32_t device_type; + uint32_t device_base; + uint32_t reset_type; + uint32_t cic_id; + uint32_t version; + uint32_t mem_size; + uint8_t app_nmi_buffer[64]; + uint32_t __reserved_1[37]; + uint32_t mem_size_6105; +} os_info_t; + +#define OS_INFO_BASE (0x80000300UL) +#define OS_INFO ((os_info_t *) OS_INFO_BASE) + + uint32_t io_read (io32_t *address); void io_write (io32_t *address, uint32_t value); uint32_t pi_busy (void); uint32_t pi_io_read (io32_t *address); void pi_io_write (io32_t *address, uint32_t value); +void pi_dma_read (io32_t *address, void *buffer, size_t length); +void pi_dma_write (io32_t *address, void *buffer, size_t length); uint32_t si_busy (void); uint32_t si_io_read (io32_t *address); void si_io_write (io32_t *address, uint32_t value); +void cache_data_hit_writeback_invalidate (void *address, size_t length); +void cache_data_hit_writeback (void *address, size_t length); +void cache_inst_hit_invalidate (void *address, size_t length); #endif diff --git a/sw/bootloader/src/ipl2.S b/sw/bootloader/src/ipl2.S new file mode 100644 index 0000000..abf4f4b --- /dev/null +++ b/sw/bootloader/src/ipl2.S @@ -0,0 +1,15 @@ +.set noat +.set noreorder + +.section .data.ipl2 +ipl2: + .global ipl2 + lui $t5, 0xBFC0 +1: + lw $t0, 0x7FC($t5) + addiu $t5, $t5, 0x7C0 + andi $t0, $t0, 0x80 + bnel $t0, $zero, 1b + lui $t5, 0xBFC0 + lw $t0, 0x24($t5) + lui $t3, 0xB000 diff --git a/sw/bootloader/src/main.c b/sw/bootloader/src/main.c new file mode 100644 index 0000000..88e1944 --- /dev/null +++ b/sw/bootloader/src/main.c @@ -0,0 +1,56 @@ +#include "boot.h" +#include "error.h" +#include "init.h" +#include "io.h" +#include "menu.h" +#include "sc64.h" + + +void main (void) { + boot_info_t boot_info; + sc64_boot_info_t sc64_boot_info; + + sc64_get_boot_info(&sc64_boot_info); + + switch (sc64_boot_info.boot_mode) { + case BOOT_MODE_MENU: + menu_load_and_run(); + break; + + case BOOT_MODE_ROM: + boot_info.device_type = BOOT_DEVICE_TYPE_ROM; + break; + + case BOOT_MODE_DDIPL: + boot_info.device_type = BOOT_DEVICE_TYPE_DD; + break; + + default: + error_display("Unknown boot mode selected [%d]\n", sc64_boot_info.boot_mode); + break; + } + + boot_info.reset_type = OS_INFO->reset_type; + + if (sc64_boot_info.tv_type != TV_TYPE_UNKNOWN) { + boot_info.tv_type = sc64_boot_info.tv_type; + } else { + if (!boot_get_tv_type(&boot_info)) { + boot_info.tv_type = OS_INFO->tv_type; + } + } + + if (sc64_boot_info.cic_seed != CIC_SEED_UNKNOWN) { + boot_info.cic_seed = sc64_boot_info.cic_seed & 0xFF; + boot_info.version = (sc64_boot_info.cic_seed >> 8) & 0x01; + } else { + if (!boot_get_cic_seed_version(&boot_info)) { + boot_info.cic_seed = 0x3F; + boot_info.version = 0; + } + } + + deinit(); + + boot(&boot_info); +} diff --git a/sw/bootloader/src/menu.c b/sw/bootloader/src/menu.c new file mode 100644 index 0000000..e5a8756 --- /dev/null +++ b/sw/bootloader/src/menu.c @@ -0,0 +1,73 @@ +#include "error.h" +#include "fatfs/ff.h" +#include "init.h" +#include "io.h" +#include "menu.h" + + +#define ROM_ENTRY_OFFSET (8) +#define ROM_CODE_OFFSET (4096) +#define ROM_MAX_LOAD_SIZE (1 * 1024 * 1024) + + +static const char *fatfs_error_codes[] = { + "Succeeded", + "A hard error occurred in the low level disk I/O layer", + "Assertion failed", + "The physical drive cannot work", + "Could not find the file", + "Could not find the path", + "The path name format is invalid", + "Access denied due to prohibited access or directory full", + "Access denied due to prohibited access", + "The file/directory object is invalid", + "The physical drive is write protected", + "The logical drive number is invalid", + "The volume has no work area", + "There is no valid FAT volume", + "The f_mkfs() aborted due to any problem", + "Could not get a grant to access the volume within defined period", + "The operation is rejected according to the file sharing policy", + "LFN working buffer could not be allocated", + "Number of open files > FF_FS_LOCK", + "Given parameter is invalid", +}; + + +#define FF_CHECK(x, message, ...) { \ + fresult = x; \ + if (fresult != FR_OK) { \ + error_display(message " [%s]:\n %s\n", __VA_ARGS__ __VA_OPT__(,) #x, fatfs_error_codes[fresult]); \ + } \ +} + + +void menu_load_and_run (void) { + void (* menu)(void); + FRESULT fresult; + FATFS fs; + FIL fil; + UINT br; + FSIZE_t size = ROM_MAX_LOAD_SIZE; + + FF_CHECK(f_mount(&fs, "", 1), "Couldn't mount drive"); + FF_CHECK(f_open(&fil, "sc64menu.n64", FA_READ), "Couldn't open menu file"); + FF_CHECK(f_lseek(&fil, ROM_ENTRY_OFFSET), "Couldn't seek to entry point offset"); + FF_CHECK(f_read(&fil, &menu, sizeof(menu), &br), "Couldn't read entry point"); + FF_CHECK(f_lseek(&fil, ROM_CODE_OFFSET), "Couldn't seek to code start offset"); + if ((f_size(&fil) - ROM_CODE_OFFSET) < size) { + size = (f_size(&fil) - ROM_CODE_OFFSET); + } + FF_CHECK(f_read(&fil, menu, size, &br), "Couldn't read menu file"); + FF_CHECK(br != size, "Read size is different than expected"); + FF_CHECK(f_close(&fil), "Couldn't close menu file"); + FF_CHECK(f_unmount(""), "Couldn't unmount drive"); + + cache_inst_hit_invalidate(menu, size); + + deinit(); + + menu(); + + while (1); +} diff --git a/sw/bootloader/src/menu.h b/sw/bootloader/src/menu.h new file mode 100644 index 0000000..505608b --- /dev/null +++ b/sw/bootloader/src/menu.h @@ -0,0 +1,8 @@ +#ifndef MENU_H__ +#define MENU_H__ + + +void menu_load_and_run (void); + + +#endif diff --git a/sw/bootloader/src/sc64.c b/sw/bootloader/src/sc64.c new file mode 100644 index 0000000..b452878 --- /dev/null +++ b/sw/bootloader/src/sc64.c @@ -0,0 +1,212 @@ +#include "io.h" +#include "sc64.h" + + +#define SC64_VERSION_2 (0x53437632) + + +typedef enum { + SC64_CMD_VERSION_GET = 'v', + SC64_CMD_CONFIG_SET = 'C', + SC64_CMD_CONFIG_GET = 'c', + SC64_CMD_TIME_SET = 'T', + SC64_CMD_TIME_GET = 't', + SC64_CMD_USB_WRITE_STATUS = 'U', + SC64_CMD_USB_WRITE = 'M', + SC64_CMD_USB_READ_STATUS = 'u', + SC64_CMD_USB_READ = 'm', + SC64_CMD_SD_CARD_OP = 'i', + SC64_CMD_SD_SECTOR_SET = 'I', + SC64_CMD_SD_WRITE = 'S', + SC64_CMD_SD_READ = 's', + SC64_CMD_DD_SD_DISK_INFO = 'D', + SC64_CMD_FLASH_ERASE_BLOCK = 'P', + SC64_CMD_FLASH_WAIT_BUSY = 'p', +} cmd_id_t; + +typedef enum { + SD_CARD_OP_DEINIT = 0, + SD_CARD_OP_INIT = 1, + SD_CARD_OP_GET_STATUS = 2, + SD_CARD_OP_GET_INFO = 3, +} sd_card_op_t; + + +static bool sc64_wait_cpu_busy (void) { + uint32_t sr; + do { + sr = pi_io_read(&SC64_REGS->SR_CMD); + } while (sr & SC64_SR_CPU_BUSY); + return (sr & SC64_SR_CMD_ERROR); +} + +static bool sc64_execute_cmd (uint8_t cmd, uint32_t *args, uint32_t *result) { + sc64_wait_cpu_busy(); + if (args != NULL) { + pi_io_write(&SC64_REGS->DATA[0], args[0]); + pi_io_write(&SC64_REGS->DATA[1], args[1]); + } + pi_io_write(&SC64_REGS->SR_CMD, ((uint32_t) (cmd)) & 0xFF); + bool error = sc64_wait_cpu_busy(); + if (result != NULL) { + result[0] = pi_io_read(&SC64_REGS->DATA[0]); + result[1] = pi_io_read(&SC64_REGS->DATA[1]); + } + return error; +} + +void sc64_unlock (void) { + pi_io_write(&SC64_REGS->KEY, SC64_KEY_RESET); + pi_io_write(&SC64_REGS->KEY, SC64_KEY_UNLOCK_1); + pi_io_write(&SC64_REGS->KEY, SC64_KEY_UNLOCK_2); +} + +void sc64_lock (void) { + pi_io_write(&SC64_REGS->KEY, SC64_KEY_RESET); + pi_io_write(&SC64_REGS->KEY, SC64_KEY_LOCK); +} + +bool sc64_check_presence (void) { + uint32_t version = pi_io_read(&SC64_REGS->VERSION); + return (version == SC64_VERSION_2); +} + +cmd_error_t sc64_get_error (void) { + if (pi_io_read(&SC64_REGS->SR_CMD) & SC64_SR_CMD_ERROR) { + return (cmd_error_t) pi_io_read(&SC64_REGS->DATA[0]); + } + return CMD_OK; +} + +void sc64_set_config (cfg_id_t id, uint32_t value) { + uint32_t args[2] = { id, value }; + sc64_execute_cmd(SC64_CMD_CONFIG_SET, args, NULL); +} + +uint32_t sc64_get_config (cfg_id_t id) { + uint32_t args[2] = { id, 0 }; + uint32_t result[2]; + sc64_execute_cmd(SC64_CMD_CONFIG_GET, args, result); + return result[1]; +} + +void sc64_get_boot_info (sc64_boot_info_t *info) { + info->cic_seed = (uint16_t) sc64_get_config(CFG_ID_CIC_SEED); + info->tv_type = (tv_type_t) sc64_get_config(CFG_ID_TV_TYPE); + info->boot_mode = (boot_mode_t) sc64_get_config(CFG_ID_BOOT_MODE); +} + +void sc64_set_time (rtc_time_t *t) { + uint32_t args[2] = { + ((t->hour << 16) | (t->minute << 8) | t->second), + ((t->weekday << 24) | (t->year << 16) | (t->month << 8) | t->day), + }; + sc64_execute_cmd(SC64_CMD_TIME_SET, args, NULL); +} + +void sc64_get_time (rtc_time_t *t) { + uint32_t result[2]; + sc64_execute_cmd(SC64_CMD_TIME_GET, NULL, result); + t->second = (result[0] & 0xFF); + t->minute = ((result[0] >> 8) & 0xFF); + t->hour = ((result[0] >> 16) & 0xFF); + t->weekday = ((result[1] >> 24) & 0xFF); + t->day = (result[1] & 0xFF); + t->month = ((result[1] >> 8) & 0xFF); + t->year = ((result[1] >> 16) & 0xFF); +} + +bool sc64_usb_write_ready (void) { + uint32_t result[2]; + sc64_execute_cmd(SC64_CMD_USB_WRITE_STATUS, NULL, result); + return (!(result[0] & (1 << 31))); +} + +bool sc64_usb_write (uint32_t *address, uint8_t type, uint32_t length) { + while (!sc64_usb_write_ready()); + uint32_t args[2] = { (uint32_t) (address), ((type << 24) | (length & 0xFFFFFF)) }; + return sc64_execute_cmd(SC64_CMD_USB_WRITE, args, NULL); +} + +bool sc64_usb_read_ready (uint8_t *type, uint32_t *length) { + uint32_t result[2]; + sc64_execute_cmd(SC64_CMD_USB_READ_STATUS, NULL, result); + if (type != NULL) { + *type = result[0] & 0xFF; + } + if (length != NULL) { + *length = result[1]; + } + return (result[1] > 0); +} + +bool sc64_usb_read (uint32_t *address, uint32_t length) { + uint32_t args[2] = { (uint32_t) (address), length }; + uint32_t result[2]; + if (sc64_execute_cmd(SC64_CMD_USB_READ, args, NULL)) { + return true; + } + do { + sc64_execute_cmd(SC64_CMD_USB_READ_STATUS, NULL, result); + } while(result[0] & (1 << 31)); + return false; +} + +bool sc64_sd_card_init (void) { + uint32_t args[2] = { 0, SD_CARD_OP_INIT }; + if (sc64_execute_cmd(SC64_CMD_SD_CARD_OP, args, NULL)) { + return true; + } + return false; +} + +bool sc64_sd_card_deinit (void) { + uint32_t args[2] = { 0, SD_CARD_OP_DEINIT }; + if (sc64_execute_cmd(SC64_CMD_SD_CARD_OP, args, NULL)) { + return true; + } + return false; +} + +sd_card_status_t sc64_sd_card_get_status (void) { + uint32_t args[2] = { 0, SD_CARD_OP_GET_STATUS }; + uint32_t result[2]; + if (sc64_execute_cmd(SC64_CMD_SD_CARD_OP, args, result)) { + return false; + } + return (sd_card_status_t) (result[1]); +} + +bool sc64_sd_card_get_info (uint32_t *address) { + uint32_t args[2] = { (uint32_t) (address), SD_CARD_OP_GET_INFO }; + if (sc64_execute_cmd(SC64_CMD_SD_CARD_OP, args, NULL)) { + return true; + } + return false; +} + +bool sc64_sd_write_sectors (uint32_t *address, uint32_t sector, uint32_t count) { + uint32_t sector_set_args[2] = { sector, 0 }; + uint32_t write_args[2] = { (uint32_t) (address), count }; + if (sc64_execute_cmd(SC64_CMD_SD_SECTOR_SET, sector_set_args, NULL)) { + return true; + } + return sc64_execute_cmd(SC64_CMD_SD_WRITE, write_args, NULL); +} + +bool sc64_sd_read_sectors (uint32_t *address, uint32_t sector, uint32_t count) { + uint32_t sector_set_args[2] = { sector, 0 }; + uint32_t read_args[2] = { (uint32_t) (address), count }; + if (sc64_execute_cmd(SC64_CMD_SD_SECTOR_SET, sector_set_args, NULL)) { + return true; + } + return sc64_execute_cmd(SC64_CMD_SD_READ, read_args, NULL); +} + +bool sc64_dd_set_sd_disk_info (uint32_t *address, uint32_t length) { + uint32_t args[2] = { (uint32_t) (address), length }; + if (sc64_execute_cmd(SC64_CMD_DD_SD_DISK_INFO, args, NULL)) { + return true; + } + return false; +} diff --git a/sw/bootloader/src/sc64.h b/sw/bootloader/src/sc64.h new file mode 100644 index 0000000..70e5e9e --- /dev/null +++ b/sw/bootloader/src/sc64.h @@ -0,0 +1,122 @@ +#ifndef SC64_H__ +#define SC64_H__ + + +#include +#include + + +typedef enum { + CMD_OK = 0, + CMD_ERROR_BAD_ADDRESS = 1, + CMD_ERROR_BAD_CONFIG_ID = 2, + CMD_ERROR_TIMEOUT = 3, + CMD_ERROR_UNKNOWN_CMD = -1, +} cmd_error_t; + +typedef enum { + CFG_ID_BOOTLOADER_SWITCH, + CFG_ID_ROM_WRITE_ENABLE, + CFG_ID_ROM_SHADOW_ENABLE, + CFG_ID_DD_MODE, + CFG_ID_ISV_ENABLE, + CFG_ID_BOOT_MODE, + CFG_ID_SAVE_TYPE, + CFG_ID_CIC_SEED, + CFG_ID_TV_TYPE, + CFG_ID_DD_SD_ENABLE, + CFG_ID_DD_DRIVE_TYPE, + CFG_ID_DD_DISK_STATE, + CFG_ID_BUTTON_STATE, + CFG_ID_BUTTON_MODE, + CFG_ID_ROM_EXTENDED_ENABLE, +} cfg_id_t; + +typedef enum { + DD_MODE_DISABLED = 0, + DD_MODE_REGS = 1, + DD_MODE_IPL = 2, + DD_MODE_FULL = 3 +} dd_mode_t; + +typedef enum { + BOOT_MODE_MENU = 0, + BOOT_MODE_ROM = 1, + BOOT_MODE_DDIPL = 2, + BOOT_MODE_DIRECT = 3 +} boot_mode_t; + +typedef enum { + SAVE_TYPE_NONE = 0, + SAVE_TYPE_EEPROM_4K = 1, + SAVE_TYPE_EEPROM_16K = 2, + SAVE_TYPE_SRAM = 3, + SAVE_TYPE_FLASHRAM = 4, + SAVE_TYPE_SRAM_BANKED = 5 +} save_type_t; + +typedef enum { + CIC_SEED_UNKNOWN = 0xFFFF +} cic_seed_t; + +typedef enum { + TV_TYPE_PAL = 0, + TV_TYPE_NTSC = 1, + TV_TYPE_MPAL = 2, + TV_TYPE_UNKNOWN = 3 +} tv_type_t; + +typedef enum { + BUTTON_MODE_NONE, + BUTTON_MODE_N64_IRQ, + BUTTON_MODE_USB_PACKET, + BUTTON_MODE_DD_DISK_SWAP, +} button_mode_t; + +typedef enum { + SD_CARD_STATUS_INITIALIZED = (1 << 0), + SD_CARD_STATUS_TYPE_BLOCK = (1 << 1), + SD_CARD_STATUS_50MHZ_MODE = (1 << 2), +} sd_card_status_t; + + +typedef struct { + boot_mode_t boot_mode; + uint16_t cic_seed; + tv_type_t tv_type; +} sc64_boot_info_t; + +typedef struct { + uint8_t second; + uint8_t minute; + uint8_t hour; + uint8_t weekday; + uint8_t day; + uint8_t month; + uint8_t year; +} rtc_time_t; + + +void sc64_unlock (void); +void sc64_lock (void); +bool sc64_check_presence (void); +cmd_error_t sc64_get_error (void); +void sc64_set_config (cfg_id_t id, uint32_t value); +uint32_t sc64_get_config (cfg_id_t id); +void sc64_get_boot_info (sc64_boot_info_t *info); +void sc64_set_time (rtc_time_t *t); +void sc64_get_time (rtc_time_t *t); +bool sc64_usb_write_ready (void); +bool sc64_usb_write (uint32_t *address, uint8_t type, uint32_t length); +bool sc64_usb_read_ready (uint8_t *type, uint32_t *length); +bool sc64_usb_read (uint32_t *address, uint32_t length); +bool sc64_sd_card_init (void); +bool sc64_sd_card_deinit (void); +sd_card_status_t sc64_sd_card_get_status (void); +bool sc64_sd_card_get_info (uint32_t *address); +bool sc64_sd_write_sectors (uint32_t *address, uint32_t sector, uint32_t count); +bool sc64_sd_read_sectors (uint32_t *address, uint32_t sector, uint32_t count); +bool sc64_dd_set_sd_disk_info (uint32_t *address, uint32_t length); + + +#endif diff --git a/sw/n64/src/startup.S b/sw/bootloader/src/startup.S similarity index 52% rename from sw/n64/src/startup.S rename to sw/bootloader/src/startup.S index c875e9f..2b2fe03 100644 --- a/sw/n64/src/startup.S +++ b/sw/bootloader/src/startup.S @@ -1,6 +1,4 @@ -#define STR(x) #x -#define XSTR(s) STR(s) -#define VERSION XSTR(__SC64_VERSION) +#include "vr4300.h" .section .text.rom_header @@ -21,9 +19,7 @@ header_crc: .org 0x20, 0x00 header_text_info: - .global header_text_info - .ascii "SummerLoader64 " - .ascii VERSION + .ascii "SC64 bootloader" .org 0x40, 0x00 @@ -39,7 +35,14 @@ entry_handler: la $gp, _gp la $sp, _sp -run: +bss_init: + la $a0, _sbss + la $a1, _ebss +1: + sd $zero, 0($a0) + addiu $a0, 8 + bltu $a0, $a1, 1b + la $t0, init jalr $t0 @@ -48,19 +51,3 @@ run: loop: j loop - - -.section .text.ipl2 -ipl2: - .global ipl2 - .set noat - .set noreorder - lui $t5, 0xBFC0 -1: - lw $t0, 0x7FC($t5) - addiu $t5, $t5, 0x7C0 - andi $t0, $t0, 0x80 - bnel $t0, $zero, 1b - lui $t5, 0xBFC0 - lw $t0, 0x24($t5) - lui $t3, 0xB000 diff --git a/sw/bootloader/src/syscalls.c b/sw/bootloader/src/syscalls.c new file mode 100644 index 0000000..70c1327 --- /dev/null +++ b/sw/bootloader/src/syscalls.c @@ -0,0 +1,22 @@ +#include +#include + + +extern char _sheap __attribute__((section(".data"))); +extern char _eheap __attribute__((section(".data"))); + + +caddr_t _sbrk_r (struct _reent *prt, ptrdiff_t incr) { + static char *curr_heap_end = &_sheap; + char *prev_heap_end; + + prev_heap_end = curr_heap_end; + curr_heap_end += incr; + + if (curr_heap_end > &_eheap) { + errno = ENOMEM; + return (caddr_t) -1; + } + + return (caddr_t) prev_heap_end; +} diff --git a/sw/bootloader/src/test.c b/sw/bootloader/src/test.c new file mode 100644 index 0000000..5095ccd --- /dev/null +++ b/sw/bootloader/src/test.c @@ -0,0 +1,66 @@ +#include +#include "display.h" +#include "io.h" +#include "sc64.h" +#include "test.h" + + +bool test_check (void) { + if (sc64_get_config(CFG_ID_BUTTON_STATE)) { + return true; + } + return false; +} + +void test_execute (void) { + sd_card_status_t card_status; + uint8_t card_info[32] __attribute__((aligned(8))); + + display_init(NULL); + + display_printf("SC64 Test suite\n\n"); + + if (sc64_sd_card_init()) { + display_printf("SD card init error!\n"); + while (1); + } + + card_status = sc64_sd_card_get_status(); + + if (card_status & SD_CARD_STATUS_INITIALIZED) { + display_printf("SD card initialized\n"); + } + if (card_status & SD_CARD_STATUS_TYPE_BLOCK) { + display_printf("SD card type block\n"); + } + if (card_status & SD_CARD_STATUS_50MHZ_MODE) { + display_printf("SD card 50 MHz clock mode\n"); + } + + if (sc64_sd_card_get_info((uint32_t *) (SC64_BUFFERS->BUFFER))) { + display_printf("SD card get info error!\n"); + while (1); + } + + pi_dma_read((io32_t *) (SC64_BUFFERS->BUFFER), card_info, sizeof(card_info)); + + display_printf("SD Card registers:\n CSD: 0x"); + for (int i = 0; i < 16; i++) { + display_printf("%02X", card_info[i]); + } + display_printf("\n CID: 0x"); + for (int i = 16; i < 32; i++) { + display_printf("%02X", card_info[i]); + } + display_printf("\n "); + for (int i = 16; i < 32; i++) { + display_printf("%c ", card_info[i] >= ' ' ? card_info[i] : 0xFF); + } + + if (sc64_sd_card_deinit()) { + display_printf("SD card deinit error!\n"); + while (1); + } + + while (1); +} diff --git a/sw/bootloader/src/test.h b/sw/bootloader/src/test.h new file mode 100644 index 0000000..a56bcd8 --- /dev/null +++ b/sw/bootloader/src/test.h @@ -0,0 +1,12 @@ +#ifndef TEST_H__ +#define TEST_H__ + + +#include + + +bool test_check (void); +void test_execute (void); + + +#endif diff --git a/sw/bootloader/src/version.c b/sw/bootloader/src/version.c new file mode 100644 index 0000000..645dfc8 --- /dev/null +++ b/sw/bootloader/src/version.c @@ -0,0 +1,30 @@ +#include "version.h" + + +static version_t version = { +#ifdef GIT_BRANCH + .git_branch = GIT_BRANCH, +#else +#warning "No GIT_BRANCH provided" +#endif +#ifdef GIT_TAG + .git_tag = GIT_TAG, +#else +#warning "No GIT_TAG provided" +#endif +#ifdef GIT_SHA + .git_sha = GIT_SHA, +#else +#warning "No GIT_SHA provided" +#endif +#ifdef GIT_MESSAGE + .git_message = GIT_MESSAGE, +#else +#warning "No GIT_MESSAGE provided" +#endif +}; + + +version_t *version_get (void) { + return &version; +} diff --git a/sw/bootloader/src/version.h b/sw/bootloader/src/version.h new file mode 100644 index 0000000..8b875ed --- /dev/null +++ b/sw/bootloader/src/version.h @@ -0,0 +1,16 @@ +#ifndef VERSION_H__ +#define VERSION_H__ + + +typedef const struct { + const char *git_branch; + const char *git_tag; + const char *git_sha; + const char *git_message; +} version_t; + + +const version_t *version_get (void); + + +#endif diff --git a/sw/bootloader/src/vr4300.h b/sw/bootloader/src/vr4300.h new file mode 100644 index 0000000..58b3617 --- /dev/null +++ b/sw/bootloader/src/vr4300.h @@ -0,0 +1,75 @@ +#ifndef VR4300_H__ +#define VR4300_H__ + + +#define HIT_INVALIDATE_I ((4 << 2) | 0) +#define HIT_WRITE_BACK_INVALIDATE_D ((5 << 2) | 1) +#define HIT_WRITE_BACK_D ((6 << 2) | 1) + +#define CACHE_LINE_SIZE_I (32) +#define CACHE_LINE_SIZE_D (16) + +#define C0_BADVADDR $8 +#define C0_COUNT $9 +#define C0_COMPARE $11 +#define C0_STATUS $12 +#define C0_CAUSE $13 +#define C0_EPC $14 + + +#define C0_SR_IE (1 << 0) +#define C0_SR_EXL (1 << 1) +#define C0_SR_EXR (1 << 2) +#define C0_SR_KSU0 (1 << 3) +#define C0_SR_KSU1 (1 << 4) +#define C0_SR_UX (1 << 5) +#define C0_SR_SX (1 << 6) +#define C0_SR_KX (1 << 7) +#define C0_SR_IM0 (1 << 8) +#define C0_SR_IM1 (1 << 9) +#define C0_SR_IM2 (1 << 10) +#define C0_SR_IM3 (1 << 11) +#define C0_SR_IM4 (1 << 12) +#define C0_SR_IM5 (1 << 13) +#define C0_SR_IM6 (1 << 14) +#define C0_SR_IM7 (1 << 15) +#define C0_SR_DS_DE (1 << 16) +#define C0_SR_DS_CE (1 << 17) +#define C0_SR_DS_CH (1 << 18) +#define C0_SR_DS_SR (1 << 20) +#define C0_SR_DS_TS (1 << 21) +#define C0_SR_DS_BEV (1 << 22) +#define C0_SR_DS_ITS (1 << 24) +#define C0_SR_RE (1 << 25) +#define C0_SR_FR (1 << 26) +#define C0_SR_RP (1 << 27) +#define C0_SR_CU0 (1 << 28) +#define C0_SR_CU1 (1 << 29) +#define C0_SR_CU2 (1 << 30) +#define C0_SR_CU3 (1 << 31) + + +#define C0_CR_EC0 (1 << 2) +#define C0_CR_EC1 (1 << 3) +#define C0_CR_EC2 (1 << 4) +#define C0_CR_EC3 (1 << 5) +#define C0_CR_EC4 (1 << 6) +#define C0_CR_IP0 (1 << 8) +#define C0_CR_IP1 (1 << 9) +#define C0_CR_IP2 (1 << 10) +#define C0_CR_IP3 (1 << 11) +#define C0_CR_IP4 (1 << 12) +#define C0_CR_IP5 (1 << 13) +#define C0_CR_IP6 (1 << 14) +#define C0_CR_IP7 (1 << 15) +#define C0_CR_CE0 (1 << 28) +#define C0_CR_CE1 (1 << 29) +#define C0_CR_BD (1 << 31) + +#define C0_CR_EC_MASK (C0_CR_EC4 | C0_CR_EC3 | C0_CR_EC2 | C0_CR_EC1 | C0_CR_EC0) +#define C0_CR_EC_BIT (2) +#define C0_CR_IP_MASK (C0_CR_IP7 | C0_CR_IP6 | C0_CR_IP5 | C0_CR_IP4 | C0_CR_IP3 | C0_CR_IP2 | C0_CR_IP1 | C0_CR_IP0) +#define C0_CR_IP_BIT (8) + + +#endif diff --git a/sw/bootloader/tools/asset_converter.py b/sw/bootloader/tools/asset_converter.py new file mode 100644 index 0000000..7341eb2 --- /dev/null +++ b/sw/bootloader/tools/asset_converter.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python3 + +import sys +from PIL import Image + + + +if __name__ == "__main__": + if (len(sys.argv) != 3): + print(f"Usage: python {sys.argv[0]} input_path output_path") + sys.exit(1) + + asset_input = sys.argv[1] + asset_output = sys.argv[2] + + source_asset = None + final_asset = None + + try: + source_asset = Image.open(asset_input) + converted_asset = source_asset.convert("RGBA") + final_asset = open(asset_output, "wb") + final_asset.write(converted_asset.tobytes()) + except FileNotFoundError: + print(f"Couldn't open file \"{asset_input}\"") + sys.exit(2) + except Exception as e: + print(e) + sys.exit(3) + finally: + if (source_asset): + source_asset.close() + if (final_asset): + final_asset.close() diff --git a/sw/bootloader/tools/requirements.txt b/sw/bootloader/tools/requirements.txt new file mode 100644 index 0000000..a6d4d60 --- /dev/null +++ b/sw/bootloader/tools/requirements.txt @@ -0,0 +1 @@ +Pillow==9.2.0 diff --git a/sw/cic b/sw/cic deleted file mode 160000 index 16fd1ee..0000000 --- a/sw/cic +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 16fd1eecd8528ab2d7fd0490f24fb7738017bd39 diff --git a/sw/controller/.gitattributes b/sw/controller/.gitattributes new file mode 100644 index 0000000..18d0af0 --- /dev/null +++ b/sw/controller/.gitattributes @@ -0,0 +1 @@ +lib/** linguist-vendored diff --git a/sw/controller/.gitignore b/sw/controller/.gitignore new file mode 100644 index 0000000..5743e15 --- /dev/null +++ b/sw/controller/.gitignore @@ -0,0 +1,2 @@ +/build +*.svd diff --git a/sw/controller/app.ld b/sw/controller/app.ld new file mode 100644 index 0000000..f90c3fd --- /dev/null +++ b/sw/controller/app.ld @@ -0,0 +1,62 @@ +MEMORY { + loader (rx) : org = 0x08000000, len = 4k + rom (rx) : org = 0x08001000, len = 28k + ram (rwx) : org = 0x20000000, len = 8k +} + +ENTRY(Reset_Handler) + +SECTIONS { + .loader : { + . = ALIGN(4); + KEEP(*(.loader)) + . = ALIGN(4); + } > loader + + .isr_vector : { + . = ALIGN(4); + KEEP(*(.isr_vector)) + . = ALIGN(4); + } > rom + + .text : { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + . = ALIGN(4); + _etext = .; + } > rom + + .bss : { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } > ram + + .data : { + _sidata = LOADADDR(.data); + . = ALIGN(4); + _sdata = .; + *(.data) + *(.data*) + . = ALIGN(4); + _edata = .; + } > ram AT > rom + + .rodata : { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } > rom + + _estack = ORIGIN(ram) + LENGTH(ram); +} diff --git a/sw/controller/app.mk b/sw/controller/app.mk new file mode 100644 index 0000000..c43df45 --- /dev/null +++ b/sw/controller/app.mk @@ -0,0 +1,29 @@ +EXE_NAME = app +LD_SCRIPT = app.ld +BUILD_DIR = build/app +SRC_FILES = \ + app.S \ + app.c \ + button.c \ + cfg.c \ + cic.c \ + dd.c \ + debug.c \ + flash.c \ + flashram.c \ + fpga.c \ + gvr.c \ + hw.c \ + isv.c \ + lcmxo2.c \ + led.c \ + rtc.c \ + sd.c \ + task.c \ + update.c \ + usb.c +PAD_TO = 0x08008000 + +include common.mk + +$(BUILD_DIR)/app.S.o: ../build/loader/loader.bin diff --git a/sw/controller/build.sh b/sw/controller/build.sh new file mode 100755 index 0000000..a969cec --- /dev/null +++ b/sw/controller/build.sh @@ -0,0 +1,14 @@ +#!/bin/bash + +set -e + +case "$1" in + all) + make all -j -f loader.mk USER_FLAGS="$USER_FLAGS" + make all -j -f app.mk USER_FLAGS="$USER_FLAGS" + ;; + clean) + make clean -f loader.mk + make clean -f app.mk + ;; +esac diff --git a/sw/riscv/Makefile b/sw/controller/common.mk similarity index 55% rename from sw/riscv/Makefile rename to sw/controller/common.mk index 566e32b..bee414e 100644 --- a/sw/riscv/Makefile +++ b/sw/controller/common.mk @@ -1,18 +1,15 @@ -TOOLCHAIN = riscv32-unknown-elf- +TOOLCHAIN = arm-none-eabi- CC = $(TOOLCHAIN)gcc CXX = $(TOOLCHAIN)g++ OBJCOPY = $(TOOLCHAIN)objcopy OBJDUMP = $(TOOLCHAIN)objdump SIZE = $(TOOLCHAIN)size -FLAGS = -mabi=ilp32 -march=rv32i $(USER_FLAGS) -CFLAGS = -Os -Wall -ffunction-sections -fdata-sections -ffreestanding -MMD -MP +FLAGS = -mcpu=cortex-m0plus -mthumb -DSTM32G030xx $(USER_FLAGS) -g -ggdb3 +CFLAGS = -Os -Wall -ffunction-sections -fdata-sections -ffreestanding -MMD -MP -I./lib LDFLAGS = -nostartfiles -Wl,--gc-sections SRC_DIR = src -BUILD_DIR = build - -SRC_FILES = startup.S process.c usb.c cfg.c dma.c joybus.c rtc.c i2c.c flashram.c uart.c flash.c dd.c SRCS = $(addprefix $(SRC_DIR)/, $(SRC_FILES)) OBJS = $(addprefix $(BUILD_DIR)/, $(notdir $(patsubst %,%.o,$(SRCS)))) @@ -28,23 +25,23 @@ $(BUILD_DIR)/%.S.o: %.S $(BUILD_DIR)/%.c.o: %.c $(CC) $(FLAGS) $(CFLAGS) -c $< -o $@ -$(BUILD_DIR)/governor.elf: $(OBJS) SC64.ld - $(CXX) $(FLAGS) $(LDFLAGS) -TSC64.ld $(OBJS) -o $@ - @$(OBJDUMP) -D $@ > $(BUILD_DIR)/governor.lst +$(BUILD_DIR)/$(EXE_NAME).elf: $(OBJS) $(LD_SCRIPT) + $(CXX) $(FLAGS) $(LDFLAGS) -T$(LD_SCRIPT) $(OBJS) -o $@ + @$(OBJDUMP) -S -D $@ > $(BUILD_DIR)/$(EXE_NAME).lst -$(BUILD_DIR)/governor.bin: $(BUILD_DIR)/governor.elf - @$(OBJCOPY) -O binary $< $@ +$(BUILD_DIR)/$(EXE_NAME).bin: $(BUILD_DIR)/$(EXE_NAME).elf + $(OBJCOPY) -O binary --gap-fill 0xFF --pad-to $(PAD_TO) $< $@ -$(BUILD_DIR)/governor.hex: $(BUILD_DIR)/governor.bin +$(BUILD_DIR)/$(EXE_NAME).hex: $(BUILD_DIR)/$(EXE_NAME).bin @$(OBJCOPY) -I binary -O ihex $< $@ -print_size: $(BUILD_DIR)/governor.elf +print_size: $(BUILD_DIR)/$(EXE_NAME).elf @echo 'Size of modules:' @$(SIZE) -B -d -t --common $(OBJS) - @echo 'Size of governor:' + @echo 'Size of $(EXE_NAME):' @$(SIZE) -B -d $< -all: $(BUILD_DIR)/governor.hex print_size +all: $(BUILD_DIR)/$(EXE_NAME).hex print_size clean: @rm -rf ./$(BUILD_DIR)/* diff --git a/sw/controller/lib/cmsis_compiler.h b/sw/controller/lib/cmsis_compiler.h new file mode 100644 index 0000000..21a2c71 --- /dev/null +++ b/sw/controller/lib/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/sw/controller/lib/cmsis_gcc.h b/sw/controller/lib/cmsis_gcc.h new file mode 100644 index 0000000..1e08e7e --- /dev/null +++ b/sw/controller/lib/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/sw/controller/lib/cmsis_version.h b/sw/controller/lib/cmsis_version.h new file mode 100644 index 0000000..3174cf6 --- /dev/null +++ b/sw/controller/lib/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/sw/controller/lib/core_cm0plus.h b/sw/controller/lib/core_cm0plus.h new file mode 100644 index 0000000..fe7b424 --- /dev/null +++ b/sw/controller/lib/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/sw/controller/lib/mpu_armv7.h b/sw/controller/lib/mpu_armv7.h new file mode 100644 index 0000000..337eb65 --- /dev/null +++ b/sw/controller/lib/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/sw/controller/lib/stm32g030xx.h b/sw/controller/lib/stm32g030xx.h new file mode 100644 index 0000000..87131b4 --- /dev/null +++ b/sw/controller/lib/stm32g030xx.h @@ -0,0 +1,7335 @@ +/** + ****************************************************************************** + * @file stm32g030xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for stm32g030xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g030xx + * @{ + */ + +#ifndef STM32G030xx_H +#define STM32G030xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 1U /*!< STM32G0xx provides an MPU */ +#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2U /*!< STM32G0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32g030xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + RTC_TAMP_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Ch4_5_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 5 and DMAMUX1 Overrun Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_stm32g0xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + + + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBG_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ + uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ + uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x24--0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x34--0x38 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ + __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ + __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ + __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */ + __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< Reserved Address offset: 0x0C */ + uint32_t RESERVED1[7]; /*!< Reserved Address offset: 0x10 -- 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register, Address offset: 0x34 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED3[48]; /*!< Reserved Address offset: 0x54 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ +} TAMP_TypeDef; + + /** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ + uint32_t RESERVED1[25]; /*!< Reserved 0x1C */ + __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ +#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */ + +#define FLASH_SIZE (((*((uint32_t *)FLASHSIZE_BASE)) & (0x007FU)) << 10U) + +/*!< Peripheral memory map */ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB peripherals */ + +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) +#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) +#define TAMP_BASE (APBPERIPH_BASE + 0x0000B000UL) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) +#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL) +#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */ +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) +#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) +#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) +#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL) + + +/*!< AHB peripherals */ +#define DMA1_BASE (AHBPERIPH_BASE) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) + +/*!< IOPORT */ +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) +#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +#define ADC (ADC1_COMMON) /* Kept for legacy purpose */ + + + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + +#define DBG ((DBG_TypeDef *) DBG_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ +#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ + +/* Legacy defines */ +#define ADC_ISR_EOSEQ (ADC_ISR_EOS) + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ +#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ + +/* Legacy defines */ +#define ADC_IER_EOSEQIE (ADC_IER_EOSIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* Legacy defines */ +#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR_SMPSEL18_Pos (26U) +#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */ +#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */ +#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */ +#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */ +#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */ +#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */ +#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */ +#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */ +#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */ +#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */ +#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */ +#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */ +#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/* Legacy */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* DMAMUX Controller */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DMAMUX_CxCR register **************/ +#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) +#define DMAMUX_CxCR_DMAREQ_ID_Msk (0x3FUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x0000003F */ +#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ +#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ +#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ +#define DMAMUX_CxCR_SOIE_Pos (8U) +#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ +#define DMAMUX_CxCR_EGE_Pos (9U) +#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ +#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ +#define DMAMUX_CxCR_SE_Pos (16U) +#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ +#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ +#define DMAMUX_CxCR_SPOL_Pos (17U) +#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ +#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_CxCR_NBREQ_Pos (19U) +#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ +#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ +#define DMAMUX_CxCR_SYNC_ID_Pos (24U) +#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ +#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ +#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ +#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ +#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ +#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ +#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ + +/******************* Bits definition for DMAMUX_CSR register **************/ +#define DMAMUX_CSR_SOF0_Pos (0U) +#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ +#define DMAMUX_CSR_SOF1_Pos (1U) +#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ +#define DMAMUX_CSR_SOF2_Pos (2U) +#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ +#define DMAMUX_CSR_SOF3_Pos (3U) +#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */ +#define DMAMUX_CSR_SOF4_Pos (4U) +#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */ +#define DMAMUX_CSR_SOF5_Pos (5U) +#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */ +#define DMAMUX_CSR_SOF6_Pos (6U) +#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */ + +/******************** Bits definition for DMAMUX_CFR register **************/ +#define DMAMUX_CFR_CSOF0_Pos (0U) +#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ +#define DMAMUX_CFR_CSOF1_Pos (1U) +#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ +#define DMAMUX_CFR_CSOF2_Pos (2U) +#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ +#define DMAMUX_CFR_CSOF3_Pos (3U) +#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */ +#define DMAMUX_CFR_CSOF4_Pos (4U) +#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */ +#define DMAMUX_CFR_CSOF5_Pos (5U) +#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */ +#define DMAMUX_CFR_CSOF6_Pos (6U) +#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */ + +/******************** Bits definition for DMAMUX_RGxCR register ************/ +#define DMAMUX_RGxCR_SIG_ID_Pos (0U) +#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ +#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ +#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_RGxCR_OIE_Pos (8U) +#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ +#define DMAMUX_RGxCR_GE_Pos (16U) +#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ +#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ +#define DMAMUX_RGxCR_GPOL_Pos (17U) +#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ +#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_RGxCR_GNBREQ_Pos (19U) +#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ +#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for DMAMUX_RGSR register **************/ +#define DMAMUX_RGSR_OF0_Pos (0U) +#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ +#define DMAMUX_RGSR_OF1_Pos (1U) +#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ +#define DMAMUX_RGSR_OF2_Pos (2U) +#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ +#define DMAMUX_RGSR_OF3_Pos (3U) +#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ + +/******************** Bits definition for DMAMUX_RGCFR register **************/ +#define DMAMUX_RGCFR_COF0_Pos (0U) +#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ +#define DMAMUX_RGCFR_COF1_Pos (1U) +#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ +#define DMAMUX_RGCFR_COF2_Pos (2U) +#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ +#define DMAMUX_RGCFR_COF3_Pos (3U) +#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ + +/******************* Bit definition for EXTI_RPR1 register ******************/ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ + +/******************* Bit definition for EXTI_FPR1 register ******************/ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ + +/***************** Bit definition for EXTI_EXTICR1 register **************/ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR2 register **************/ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR3 register **************/ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR4 register **************/ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ + +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ +#define EXTI_IMR1_IM_Pos (0U) +#define EXTI_IMR1_IM_Msk (0x82A8FFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x82A8FFFF */ +#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ + + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ + + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +/* Note: No specific macro feature on this device */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk +#define FLASH_ACR_ICEN_Pos (9U) +#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk +#define FLASH_ACR_ICRST_Pos (11U) +#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk +#define FLASH_ACR_PROGEMPTY_Pos (16U) +#define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk + +/******************* Bits definition for FLASH_SR register ******************/ +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk +#define FLASH_SR_OPERR_Pos (1U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk +#define FLASH_SR_PROGERR_Pos (3U) +#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk +#define FLASH_SR_PGAERR_Pos (5U) +#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk +#define FLASH_SR_SIZERR_Pos (6U) +#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk +#define FLASH_SR_PGSERR_Pos (7U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk +#define FLASH_SR_MISERR_Pos (8U) +#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk +#define FLASH_SR_FASTERR_Pos (9U) +#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk +#define FLASH_SR_OPTVERR_Pos (15U) +#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk +#define FLASH_SR_BSY1_Pos (16U) +#define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk +#define FLASH_SR_CFGBSY_Pos (18U) +#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk + +/******************* Bits definition for FLASH_CR register ******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk +#define FLASH_CR_MER1_Pos (2U) +#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER1 FLASH_CR_MER1_Msk +#define FLASH_CR_PNB_Pos (3U) +#define FLASH_CR_PNB_Msk (0x1FUL << FLASH_CR_PNB_Pos) /*!< 0x000000F8 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk +#define FLASH_CR_STRT_Pos (16U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk +#define FLASH_CR_OPTSTRT_Pos (17U) +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk +#define FLASH_CR_FSTPG_Pos (18U) +#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk +#define FLASH_CR_OBL_LAUNCH_Pos (27U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk +#define FLASH_CR_OPTLOCK_Pos (30U) +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk + +/******************* Bits definition for FLASH_ECCR register ****************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk +#define FLASH_ECCR_SYSF_ECC_Pos (20U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk +#define FLASH_ECCR_ECCCIE_Pos (24U) +#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk + +/******************* Bits definition for FLASH_OPTR register ****************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk +#define FLASH_OPTR_nRST_STOP_Pos (13U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk +#define FLASH_OPTR_nRST_STDBY_Pos (14U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk +#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U) +#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk +#define FLASH_OPTR_nBOOT_SEL_Pos (24U) +#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk +#define FLASH_OPTR_nBOOT1_Pos (25U) +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk +#define FLASH_OPTR_nBOOT0_Pos (26U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk +#define FLASH_WRP1AR_WRP1A_END_Pos (16U) +#define FLASH_WRP1AR_WRP1A_END_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk +#define FLASH_WRP1BR_WRP1B_END_Pos (16U) +#define FLASH_WRP1BR_WRP1B_END_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk + + +/******************************************************************************/ +/* */ +/* General Purpose I/O */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_SWRST_Pos (13U) +#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0U) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG (IWDG) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*! */ +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-reload value bits > */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_OUT2EN_Pos (31U) +#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */ +#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!< RTC_OUT2 output enable */ +#define RTC_CR_TAMPALRM_TYPE_Pos (30U) +#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */ +#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!< TAMPALARM output type */ +#define RTC_CR_TAMPALRM_PU_Pos (29U) +#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ +#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!< TAMPALARM output pull-up config */ +#define RTC_CR_TAMPOE_Pos (26U) +#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ +#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!< Tamper detection output enable on TAMPALARM */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!< Activate timestamp on tamper detection event */ +#define RTC_CR_ITSE_Pos (24U) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!< Timestamp on internal event enable */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable > */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wakeup timer interrupt enable > */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wakeup timer enable > */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< Wakeup clock selection > */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk + +/******************** Bits definition for RTC_CALR register *****************/ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk +#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk + +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk +#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ +#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk +#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk /*!< Wakeup timer flag > */ +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk /*!< Wakeup timer masked flag > */ +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk /*!< Clear wakeup timer flag > */ +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_0 0x00000001U +#define TAMP_FLTCR_TAMPFREQ_1 0x00000002U +#define TAMP_FLTCR_TAMPFREQ_2 0x00000004U +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFLT_0 0x00000008U +#define TAMP_FLTCR_TAMPFLT_1 0x00000010U +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPPRCH_0 0x00000020U +#define TAMP_FLTCR_TAMPPRCH_1 0x00000040U +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk + +/******************** Bits definition for TAMP_SR register ******************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ***************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ***************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ***************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ***************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G0 series) + */ +#define SPI_I2S_SUPPORT /*!< I2S support */ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[21] interrupt */ +#define SYSCFG_ITLINE2_SR_RTC_Pos (1U) +#define SYSCFG_ITLINE2_SR_RTC_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE2_SR_RTC SYSCFG_ITLINE2_SR_RTC_Msk /*!< RTC -> exti[19] interrupt .... */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos (0U) +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC SYSCFG_ITLINE3_SR_FLASH_ECC_Msk /*!< Flash ITF ECC interrupt */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U) +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U) +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< RCC interrupt */ +#define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U) +#define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */ +#define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U) +#define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */ +#define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U) +#define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */ +#define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U) +#define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */ +#define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U) +#define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 4 */ +#define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U) +#define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 5 */ +#define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U) +#define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 6 */ +#define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U) +#define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 7 */ +#define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U) +#define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 8 */ +#define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U) +#define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */ +#define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 9 */ +#define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U) +#define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */ +#define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 10 */ +#define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U) +#define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */ +#define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 11 */ +#define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U) +#define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */ +#define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 12 */ +#define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U) +#define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */ +#define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 13 */ +#define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U) +#define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */ +#define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 14 */ +#define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U) +#define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */ +#define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U) +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U) +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U) +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U) +#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U) +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (2U) +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */ +#define SYSCFG_ITLINE12_SR_ADC_Pos (0U) +#define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U) +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U) +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U) +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U) +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ +#define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U) +#define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U) +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U) +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U) +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U) +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U) +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U) +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt -> exti[22]*/ +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ +#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */ +#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*! rom + + .startup : { + . = ALIGN(4); + *(.text.Reset_Handler) + . = ALIGN(4); + } > rom + + .text : { + _sitext = LOADADDR(.text); + . = ALIGN(4); + _stext = .; + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + . = ALIGN(4); + _etext = .; + } > ram AT > rom + + .bss : { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } > ram + + .data : { + _sidata = LOADADDR(.data); + . = ALIGN(4); + _sdata = .; + *(.data) + *(.data*) + . = ALIGN(4); + _edata = .; + } > ram AT > rom + + .rodata : { + _sirodata = LOADADDR(.rodata); + . = ALIGN(4); + _srodata = .; + *(.rodata) + *(.rodata*) + . = ALIGN(4); + _erodata = .; + } > ram AT > rom + + _app_header = ORIGIN(rom) + LENGTH(rom); + _app_magic = _app_header + 16; + _estack = ORIGIN(ram) + LENGTH(ram); +} diff --git a/sw/controller/loader.mk b/sw/controller/loader.mk new file mode 100644 index 0000000..32917db --- /dev/null +++ b/sw/controller/loader.mk @@ -0,0 +1,14 @@ +EXE_NAME = loader +LD_SCRIPT = loader.ld +BUILD_DIR = build/loader +SRC_FILES = \ + loader.S \ + flash.c \ + fpga.c \ + hw.c \ + lcmxo2.c \ + loader.c \ + update.c +PAD_TO = 0x08001000 + +include common.mk diff --git a/sw/controller/src/app.S b/sw/controller/src/app.S new file mode 100644 index 0000000..2c524e0 --- /dev/null +++ b/sw/controller/src/app.S @@ -0,0 +1,164 @@ +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb + +.section .loader, "a", %progbits +.type g_pfnVectors, %object +loader: + .incbin "../build/loader/loader.bin" + + +.section .text.Reset_Handler +.type Reset_Handler, %function +Reset_Handler: + .global Reset_Handler + cpsid i + +init_data: + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b 2f +1: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 +2: + adds r4, r0, r3 + cmp r4, r1 + bcc 1b + +init_bss: + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b 2f +1: + str r3, [r2] + adds r2, r2, #4 +2: + cmp r2, r4 + bcc 1b + +run: + bl app + +loop: + b loop + + +.section .text.Default_Handler, "ax", %progbits +Default_Handler: + .global Default_Handler + b Default_Handler + + +.section .isr_vector, "a", %progbits +.type g_pfnVectors, %object +g_pfnVectors: + .global g_pfnVectors + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0x34364353 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word 0 + .word RTC_TAMP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_1_IRQHandler + .word EXTI2_3_IRQHandler + .word EXTI4_15_IRQHandler + .word 0 + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_3_IRQHandler + .word DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler + .word ADC1_IRQHandler + .word TIM1_BRK_UP_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word 0 + .word TIM3_IRQHandler + .word 0 + .word 0 + .word TIM14_IRQHandler + .word 0 + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word I2C1_IRQHandler + .word I2C2_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word 0 + + .weak NMI_Handler + .thumb_set NMI_Handler, Default_Handler + .weak HardFault_Handler + .thumb_set HardFault_Handler, Default_Handler + .weak SVC_Handler + .thumb_set SVC_Handler, Default_Handler + .weak PendSV_Handler + .thumb_set PendSV_Handler, Default_Handler + .weak SysTick_Handler + .thumb_set SysTick_Handler, Default_Handler + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler, Default_Handler + .weak RTC_TAMP_IRQHandler + .thumb_set RTC_TAMP_IRQHandler, Default_Handler + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler, Default_Handler + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler, Default_Handler + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler, Default_Handler + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler, Default_Handler + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler, Default_Handler + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler, Default_Handler + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler, Default_Handler + .weak DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler + .thumb_set DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler, Default_Handler + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler, Default_Handler + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler, Default_Handler + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler, Default_Handler + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler, Default_Handler + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler, Default_Handler + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler, Default_Handler + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler, Default_Handler + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler, Default_Handler + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler, Default_Handler + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler, Default_Handler + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler, Default_Handler + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler, Default_Handler + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler, Default_Handler diff --git a/sw/controller/src/app.c b/sw/controller/src/app.c new file mode 100644 index 0000000..9bceeb5 --- /dev/null +++ b/sw/controller/src/app.c @@ -0,0 +1,32 @@ +#include +#include "cic.h" +#include "gvr.h" +#include "hw.h" +#include "led.h" +#include "rtc.h" +#include "task.h" + + +#define CIC_STACK_SIZE (256) +#define RTC_STACK_SIZE (256) +#define LED_STACK_SIZE (256) +#define GVR_STACK_SIZE (2048) + + +uint8_t cic_stack[CIC_STACK_SIZE] __attribute__((aligned(8))); +uint8_t rtc_stack[RTC_STACK_SIZE] __attribute__((aligned(8))); +uint8_t led_stack[LED_STACK_SIZE] __attribute__((aligned(8))); +uint8_t gvr_stack[GVR_STACK_SIZE] __attribute__((aligned(8))); + + +void app (void) { + hw_init(); + cic_hw_init(); + + task_create(TASK_ID_CIC, cic_task, cic_stack, CIC_STACK_SIZE); + task_create(TASK_ID_RTC, rtc_task, rtc_stack, RTC_STACK_SIZE); + task_create(TASK_ID_LED, led_task, led_stack, LED_STACK_SIZE); + task_create(TASK_ID_GVR, gvr_task, gvr_stack, GVR_STACK_SIZE); + + task_scheduler_start(); +} diff --git a/sw/controller/src/button.c b/sw/controller/src/button.c new file mode 100644 index 0000000..1c10b30 --- /dev/null +++ b/sw/controller/src/button.c @@ -0,0 +1,92 @@ +#include +#include "button.h" +#include "dd.h" +#include "fpga.h" +#include "usb.h" + + +#define BUTTON_COUNTER_TRIGGER_ON (64) +#define BUTTON_COUNTER_TRIGGER_OFF (0) + + +struct process { + uint8_t counter; + bool state; + button_mode_t mode; + bool trigger; +}; + + +static struct process p; + + +bool button_get_state (void) { + return p.state; +} + +bool button_set_mode (button_mode_t mode) { + if (mode > BUTTON_MODE_DD_DISK_SWAP) { + return true; + } + p.mode = mode; + if (p.mode == BUTTON_MODE_NONE) { + p.trigger = false; + } + return false; +} + +button_mode_t button_get_mode (void) { + return p.mode; +} + +void button_init (void) { + p.counter = 0; + p.state = false; + p.mode = BUTTON_MODE_NONE; + p.trigger = false; +} + +void button_process (void) { + usb_tx_info_t packet_info; + uint32_t status = fpga_reg_get(REG_CFG_SCR); + if (status & CFG_SCR_BUTTON_STATE) { + if (p.counter < BUTTON_COUNTER_TRIGGER_ON) { + p.counter += 1; + } + } else { + if (p.counter > BUTTON_COUNTER_TRIGGER_OFF) { + p.counter -= 1; + } + } + if (!p.state && p.counter == BUTTON_COUNTER_TRIGGER_ON) { + p.state = true; + p.trigger = true; + } + if (p.state && p.counter == BUTTON_COUNTER_TRIGGER_OFF) { + p.state = false; + } + if (p.trigger) { + switch (p.mode) { + case BUTTON_MODE_N64_IRQ: + fpga_reg_set(REG_CFG_CMD, CFG_CMD_IRQ); + p.trigger = false; + break; + + case BUTTON_MODE_USB_PACKET: + usb_create_packet(&packet_info, PACKET_CMD_BUTTON_TRIGGER); + if (usb_enqueue_packet(&packet_info)) { + p.trigger = false; + } + break; + + case BUTTON_MODE_DD_DISK_SWAP: + dd_handle_button(); + p.trigger = false; + break; + + default: + p.trigger = false; + break; + } + } +} diff --git a/sw/controller/src/button.h b/sw/controller/src/button.h new file mode 100644 index 0000000..3c41913 --- /dev/null +++ b/sw/controller/src/button.h @@ -0,0 +1,23 @@ +#ifndef BUTTON_H__ +#define BUTTON_H__ + + +#include + + +typedef enum { + BUTTON_MODE_NONE, + BUTTON_MODE_N64_IRQ, + BUTTON_MODE_USB_PACKET, + BUTTON_MODE_DD_DISK_SWAP, +} button_mode_t; + + +bool button_get_state (void); +bool button_set_mode (button_mode_t mode); +button_mode_t button_get_mode (void); +void button_init (void); +void button_process (void); + + +#endif diff --git a/sw/controller/src/cfg.c b/sw/controller/src/cfg.c new file mode 100644 index 0000000..8481e84 --- /dev/null +++ b/sw/controller/src/cfg.c @@ -0,0 +1,585 @@ +#include "button.h" +#include "cfg.h" +#include "dd.h" +#include "flash.h" +#include "fpga.h" +#include "isv.h" +#include "rtc.h" +#include "sd.h" +#include "usb.h" + + +typedef enum { + CFG_ID_BOOTLOADER_SWITCH, + CFG_ID_ROM_WRITE_ENABLE, + CFG_ID_ROM_SHADOW_ENABLE, + CFG_ID_DD_MODE, + CFG_ID_ISV_ADDRESS, + CFG_ID_BOOT_MODE, + CFG_ID_SAVE_TYPE, + CFG_ID_CIC_SEED, + CFG_ID_TV_TYPE, + CFG_ID_DD_SD_ENABLE, + CFG_ID_DD_DRIVE_TYPE, + CFG_ID_DD_DISK_STATE, + CFG_ID_BUTTON_STATE, + CFG_ID_BUTTON_MODE, + CFG_ID_ROM_EXTENDED_ENABLE, +} cfg_id_t; + +typedef enum { + DD_MODE_DISABLED = 0, + DD_MODE_REGS = 1, + DD_MODE_IPL = 2, + DD_MODE_FULL = 3 +} dd_mode_t; + +typedef enum { + BOOT_MODE_MENU = 0, + BOOT_MODE_ROM = 1, + BOOT_MODE_DD = 2, + BOOT_MODE_DIRECT = 3 +} boot_mode_t; + +typedef enum { + SAVE_TYPE_NONE = 0, + SAVE_TYPE_EEPROM_4K = 1, + SAVE_TYPE_EEPROM_16K = 2, + SAVE_TYPE_SRAM = 3, + SAVE_TYPE_FLASHRAM = 4, + SAVE_TYPE_SRAM_BANKED = 5 +} save_type_t; + +typedef enum { + CIC_SEED_UNKNOWN = 0xFFFF +} cic_seed_t; + +typedef enum { + TV_TYPE_PAL = 0, + TV_TYPE_NTSC = 1, + TV_TYPE_MPAL = 2, + TV_TYPE_UNKNOWN = 3 +} tv_type_t; + +typedef enum { + CFG_ERROR_OK = 0, + CFG_ERROR_BAD_ARGUMENT = 1, + CFG_ERROR_BAD_ADDRESS = 2, + CFG_ERROR_BAD_CONFIG_ID = 3, + CFG_ERROR_TIMEOUT = 4, + CFG_ERROR_SD_CARD = 5, + CFG_ERROR_UNKNOWN_CMD = -1, +} cfg_error_t; + +typedef enum { + SD_CARD_OP_DEINIT = 0, + SD_CARD_OP_INIT = 1, + SD_CARD_OP_GET_STATUS = 2, + SD_CARD_OP_GET_INFO = 3, +} sd_card_op_t; + +typedef enum { + SDRAM = (1 << 0), + FLASH = (1 << 1), + BRAM = (1 << 2), +} translate_type_t; + + +struct process { + boot_mode_t boot_mode; + save_type_t save_type; + cic_seed_t cic_seed; + tv_type_t tv_type; + bool usb_output_ready; + uint32_t sd_card_sector; +}; + + +static struct process p; + + +static void cfg_set_usb_output_ready (void) { + p.usb_output_ready = true; +} + +static bool cfg_translate_address (uint32_t *address, uint32_t length, translate_type_t type) { + if (length == 0) { + return true; + } + *address &= 0x1FFFFFFF; + if (type & SDRAM) { + if (*address >= 0x06000000 && *address < 0x06400000) { + if ((*address + length) <= 0x06400000) { + *address = *address - 0x06000000 + 0x03BC0000; + return false; + } + } + if (*address >= 0x08000000 && *address < 0x08020000) { + if ((*address + length) <= 0x08020000) { + *address = *address - 0x08000000 + 0x03FE0000; + return false; + } + } + if (*address >= 0x10000000 && *address < 0x14000000) { + if ((*address + length) <= 0x14000000) { + *address = *address - 0x10000000 + 0x00000000; + return false; + } + } + } + if (type & FLASH) { + if (*address >= 0x14000000 && *address < 0x14E00000) { + if ((*address + length) <= 0x14E00000) { + *address = *address - 0x14000000 + 0x04000000; + return false; + } + } + if (*address >= 0x1FFC0000 && *address < 0x1FFE0000) { + if ((*address + length) <= 0x1FFE0000) { + *address = *address - 0x1FFC0000 + 0x04E00000; + return false; + } + } + } + if (type & BRAM) { + if (*address >= 0x1FFE0000 && *address < 0x1FFE2000) { + if ((*address + length) <= 0x1FFE2000) { + *address = *address - 0x1FFE0000 + 0x05000000; + return false; + } + } + if (*address >= 0x1FFE2000 && *address < 0x1FFE2800) { + if ((*address + length) <= 0x1FFE2800) { + *address = *address - 0x1FFE2000 + 0x05002000; + return false; + } + } + } + return true; +} + +static void cfg_set_error (cfg_error_t error) { + fpga_reg_set(REG_CFG_DATA_0, error); + fpga_reg_set(REG_CFG_DATA_1, 0); + fpga_reg_set(REG_CFG_CMD, CFG_CMD_ERROR | CFG_CMD_DONE); +} + +static void cfg_change_scr_bits (uint32_t mask, bool value) { + if (value) { + fpga_reg_set(REG_CFG_SCR, fpga_reg_get(REG_CFG_SCR) | mask); + } else { + fpga_reg_set(REG_CFG_SCR, fpga_reg_get(REG_CFG_SCR) & (~mask)); + } +} + +static bool cfg_set_save_type (save_type_t save_type) { + if (save_type > SAVE_TYPE_SRAM_BANKED) { + return true; + } + + uint32_t save_reset_mask = ( + CFG_SCR_EEPROM_16K | + CFG_SCR_EEPROM_ENABLED | + CFG_SCR_FLASHRAM_ENABLED | + CFG_SCR_SRAM_BANKED | + CFG_SCR_SRAM_ENABLED + ); + + cfg_change_scr_bits(save_reset_mask, false); + + switch (save_type) { + case SAVE_TYPE_NONE: + break; + case SAVE_TYPE_EEPROM_4K: + cfg_change_scr_bits(CFG_SCR_EEPROM_ENABLED, true); + break; + case SAVE_TYPE_EEPROM_16K: + cfg_change_scr_bits(CFG_SCR_EEPROM_16K | CFG_SCR_EEPROM_ENABLED, true); + break; + case SAVE_TYPE_SRAM: + cfg_change_scr_bits(CFG_SCR_SRAM_ENABLED, true); + break; + case SAVE_TYPE_FLASHRAM: + cfg_change_scr_bits(CFG_SCR_FLASHRAM_ENABLED, true); + break; + case SAVE_TYPE_SRAM_BANKED: + cfg_change_scr_bits(CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_ENABLED, true); + break; + default: + save_type = SAVE_TYPE_NONE; + break; + } + + p.save_type = save_type; + + return false; +} + + +uint32_t cfg_get_version (void) { + return fpga_reg_get(REG_CFG_VERSION); +} + +bool cfg_query (uint32_t *args) { + uint32_t scr = fpga_reg_get(REG_CFG_SCR); + + switch (args[0]) { + case CFG_ID_BOOTLOADER_SWITCH: + args[1] = (scr & CFG_SCR_BOOTLOADER_ENABLED); + break; + case CFG_ID_ROM_WRITE_ENABLE: + args[1] = (scr & CFG_SCR_ROM_WRITE_ENABLED); + break; + case CFG_ID_ROM_SHADOW_ENABLE: + args[1] = (scr & CFG_SCR_ROM_SHADOW_ENABLED); + break; + case CFG_ID_DD_MODE: + args[1] = DD_MODE_DISABLED; + if (scr & CFG_SCR_DDIPL_ENABLED) { + args[1] |= DD_MODE_IPL; + } + if (scr & CFG_SCR_DD_ENABLED) { + args[1] |= DD_MODE_REGS; + } + break; + case CFG_ID_ISV_ADDRESS: + args[1] = isv_get_address(); + break; + case CFG_ID_BOOT_MODE: + args[1] = p.boot_mode; + break; + case CFG_ID_SAVE_TYPE: + args[1] = p.save_type; + break; + case CFG_ID_CIC_SEED: + args[1] = p.cic_seed; + break; + case CFG_ID_TV_TYPE: + args[1] = p.tv_type; + break; + case CFG_ID_DD_SD_ENABLE: + args[1] = dd_get_sd_mode(); + break; + case CFG_ID_DD_DRIVE_TYPE: + args[1] = dd_get_drive_type(); + break; + case CFG_ID_DD_DISK_STATE: + args[1] = dd_get_disk_state(); + break; + case CFG_ID_BUTTON_STATE: + args[1] = button_get_state(); + break; + case CFG_ID_BUTTON_MODE: + args[1] = button_get_mode(); + break; + case CFG_ID_ROM_EXTENDED_ENABLE: + args[1] = (scr & CFG_SCR_ROM_EXTENDED_ENABLED); + break; + default: + return true; + } + + return false; +} + +bool cfg_update (uint32_t *args) { + switch (args[0]) { + case CFG_ID_BOOTLOADER_SWITCH: + cfg_change_scr_bits(CFG_SCR_BOOTLOADER_ENABLED, args[1]); + break; + case CFG_ID_ROM_WRITE_ENABLE: + cfg_change_scr_bits(CFG_SCR_ROM_WRITE_ENABLED, args[1]); + break; + case CFG_ID_ROM_SHADOW_ENABLE: + cfg_change_scr_bits(CFG_SCR_ROM_SHADOW_ENABLED, args[1]); + break; + case CFG_ID_DD_MODE: + if (args[1] == DD_MODE_DISABLED) { + cfg_change_scr_bits(CFG_SCR_DD_ENABLED | CFG_SCR_DDIPL_ENABLED, false); + } else if (args[1] == DD_MODE_REGS) { + cfg_change_scr_bits(CFG_SCR_DD_ENABLED, true); + cfg_change_scr_bits(CFG_SCR_DDIPL_ENABLED, false); + } else if (args[1] == DD_MODE_IPL) { + cfg_change_scr_bits(CFG_SCR_DD_ENABLED, false); + cfg_change_scr_bits(CFG_SCR_DDIPL_ENABLED, true); + } else if (args[1] == DD_MODE_FULL) { + cfg_change_scr_bits(CFG_SCR_DD_ENABLED | CFG_SCR_DDIPL_ENABLED, true); + } else { + return true; + } + break; + case CFG_ID_ISV_ADDRESS: + return isv_set_address(args[1]); + break; + case CFG_ID_BOOT_MODE: + if (args[1] > BOOT_MODE_DIRECT) { + return true; + } + p.boot_mode = args[1]; + cfg_change_scr_bits(CFG_SCR_BOOTLOADER_SKIP, (args[1] == BOOT_MODE_DIRECT)); + break; + case CFG_ID_SAVE_TYPE: + return cfg_set_save_type((save_type_t) (args[1])); + break; + case CFG_ID_CIC_SEED: + if ((args[1] != 0xFFFF) && (args[1] > 0x1FF)) { + return true; + } + p.cic_seed = (cic_seed_t) (args[1] & 0xFFFF); + break; + case CFG_ID_TV_TYPE: + if (args[1] > TV_TYPE_UNKNOWN) { + return true; + } + p.tv_type = (tv_type_t) (args[1] & 0x03); + break; + case CFG_ID_DD_SD_ENABLE: + dd_set_sd_mode(args[1]); + break; + case CFG_ID_DD_DRIVE_TYPE: + return dd_set_drive_type(args[1]); + break; + case CFG_ID_DD_DISK_STATE: + return dd_set_disk_state(args[1]); + break; + case CFG_ID_BUTTON_STATE: + return true; + break; + case CFG_ID_BUTTON_MODE: + return button_set_mode(args[1]); + break; + case CFG_ID_ROM_EXTENDED_ENABLE: + cfg_change_scr_bits(CFG_SCR_ROM_EXTENDED_ENABLED, args[1]); + break; + default: + return true; + } + + return false; +} + +void cfg_get_time (uint32_t *args) { + rtc_time_t t; + rtc_get_time(&t); + args[0] = ((t.hour << 16) | (t.minute << 8) | t.second); + args[1] = ((t.weekday << 24) | (t.year << 16) | (t.month << 8) | t.day); +} + +void cfg_set_time (uint32_t *args) { + rtc_time_t t; + t.second = (args[0] & 0xFF); + t.minute = ((args[0] >> 8) & 0xFF); + t.hour = ((args[0] >> 16) & 0xFF); + t.weekday = ((args[0] >> 24) & 0xFF); + t.day = (args[1] & 0xFF); + t.month = ((args[1] >> 8) & 0xFF); + t.year = ((args[1] >> 16) & 0xFF); + rtc_set_time(&t); +} + +void cfg_reset_state (void) { + uint32_t mask = ( + CFG_SCR_BOOTLOADER_SKIP | + CFG_SCR_ROM_WRITE_ENABLED | + CFG_SCR_ROM_SHADOW_ENABLED | + CFG_SCR_DD_ENABLED | + CFG_SCR_DDIPL_ENABLED | + CFG_SCR_ROM_EXTENDED_ENABLED + ); + cfg_change_scr_bits(mask, false); + cfg_set_save_type(SAVE_TYPE_NONE); + button_set_mode(BUTTON_MODE_NONE); + dd_set_drive_type(DD_DRIVE_TYPE_RETAIL); + dd_set_disk_state(DD_DISK_STATE_EJECTED); + dd_set_sd_mode(false); + isv_set_address(0); + p.cic_seed = CIC_SEED_UNKNOWN; + p.tv_type = TV_TYPE_UNKNOWN; + p.boot_mode = BOOT_MODE_MENU; +} + +void cfg_init (void) { + fpga_reg_set(REG_CFG_SCR, CFG_SCR_BOOTLOADER_ENABLED); + cfg_reset_state(); + p.usb_output_ready = true; +} + +void cfg_process (void) { + uint32_t reg; + uint32_t args[2]; + uint32_t prev_cfg[2]; + usb_tx_info_t packet_info; + + reg = fpga_reg_get(REG_CFG_CMD); + + if (reg & CFG_CMD_PENDING) { + args[0] = fpga_reg_get(REG_CFG_DATA_0); + args[1] = fpga_reg_get(REG_CFG_DATA_1); + char cmd = (char) ((reg & CFG_CMD_MASK) >> CFG_CMD_BIT); + + switch (cmd) { + case 'v': + args[0] = cfg_get_version(); + break; + + case 'c': + if (cfg_query(args)) { + cfg_set_error(CFG_ERROR_BAD_CONFIG_ID); + return; + } + break; + + case 'C': + prev_cfg[0] = args[0]; + cfg_query(prev_cfg); + if (cfg_update(args)) { + cfg_set_error(CFG_ERROR_BAD_CONFIG_ID); + return; + } + args[1] = prev_cfg[1]; + break; + + case 't': + cfg_get_time(args); + break; + + case 'T': + cfg_set_time(args); + break; + + case 'm': + if (cfg_translate_address(&args[0], args[1], (SDRAM | BRAM))) { + cfg_set_error(CFG_ERROR_BAD_ADDRESS); + return; + } + if (!usb_prepare_read(args)) { + return; + } + break; + + case 'M': + if (cfg_translate_address(&args[0], args[1] & 0xFFFFFF, (SDRAM | BRAM))) { + cfg_set_error(CFG_ERROR_BAD_ADDRESS); + return; + } + usb_create_packet(&packet_info, PACKET_CMD_DEBUG_OUTPUT); + packet_info.data_length = 4; + packet_info.data[0] = args[1]; + packet_info.dma_length = (args[1] & 0xFFFFFF); + packet_info.dma_address = args[0]; + packet_info.done_callback = cfg_set_usb_output_ready; + if (usb_enqueue_packet(&packet_info)) { + p.usb_output_ready = false; + } else { + return; + } + break; + + case 'u': + usb_get_read_info(args); + break; + + case 'U': + args[0] = p.usb_output_ready ? 0 : (1 << 31); + break; + + case 'i': + switch (args[1]) { + case SD_CARD_OP_DEINIT: + sd_card_deinit(); + break; + case SD_CARD_OP_INIT: + if (sd_card_init()) { + cfg_set_error(CFG_ERROR_SD_CARD); + return; + } + break; + case SD_CARD_OP_GET_STATUS: + args[1] = sd_card_get_status(); + break; + case SD_CARD_OP_GET_INFO: + if (cfg_translate_address(&args[0], 32, (SDRAM | BRAM))) { + cfg_set_error(CFG_ERROR_BAD_ADDRESS); + return; + } + if (sd_card_get_info(args[0])) { + cfg_set_error(CFG_ERROR_SD_CARD); + return; + } + break; + default: + cfg_set_error(CFG_ERROR_BAD_ARGUMENT); + return; + } + break; + + case 'I': + p.sd_card_sector = args[0]; + break; + + case 's': + if (args[1] >= 0x800000) { + cfg_set_error(CFG_ERROR_BAD_ARGUMENT); + return; + } + if (cfg_translate_address(&args[0], args[1] * SD_SECTOR_SIZE, (SDRAM | BRAM | FLASH))) { + cfg_set_error(CFG_ERROR_BAD_ADDRESS); + return; + } + if (sd_read_sectors(args[0], p.sd_card_sector, args[1])) { + cfg_set_error(CFG_ERROR_SD_CARD); + return; + } + break; + + case 'S': + if (args[1] >= 0x800000) { + cfg_set_error(CFG_ERROR_BAD_ARGUMENT); + return; + } + if (cfg_translate_address(&args[0], args[1] * SD_SECTOR_SIZE, (SDRAM | BRAM | FLASH))) { + cfg_set_error(CFG_ERROR_BAD_ADDRESS); + return; + } + if (sd_write_sectors(args[0], p.sd_card_sector, args[1])) { + cfg_set_error(CFG_ERROR_SD_CARD); + return; + } + break; + + case 'D': + if (cfg_translate_address(&args[0], args[1], (SDRAM | BRAM))) { + cfg_set_error(CFG_ERROR_BAD_ADDRESS); + return; + } + dd_set_sd_disk_info(args[0], args[1]); + break; + + case 'p': + flash_wait_busy(); + args[0] = FLASH_ERASE_BLOCK_SIZE; + break; + + case 'P': + if (cfg_translate_address(&args[0], FLASH_ERASE_BLOCK_SIZE, FLASH)) { + cfg_set_error(CFG_ERROR_BAD_ADDRESS); + return; + } + flash_erase_block(args[0]); + break; + + case '?': + args[0] = fpga_reg_get(REG_DEBUG_0); + args[1] = fpga_reg_get(REG_DEBUG_1); + break; + + default: + cfg_set_error(CFG_ERROR_UNKNOWN_CMD); + return; + } + + fpga_reg_set(REG_CFG_DATA_0, args[0]); + fpga_reg_set(REG_CFG_DATA_1, args[1]); + fpga_reg_set(REG_CFG_CMD, CFG_CMD_DONE); + } +} diff --git a/sw/controller/src/cfg.h b/sw/controller/src/cfg.h new file mode 100644 index 0000000..8ca463b --- /dev/null +++ b/sw/controller/src/cfg.h @@ -0,0 +1,19 @@ +#ifndef CFG_H__ +#define CFG_H__ + + +#include +#include + + +uint32_t cfg_get_version (void); +bool cfg_query (uint32_t *args); +bool cfg_update (uint32_t *args); +void cfg_get_time (uint32_t *args); +void cfg_set_time (uint32_t *args); +void cfg_reset_state (void); +void cfg_init (void); +void cfg_process (void); + + +#endif diff --git a/sw/controller/src/cic.c b/sw/controller/src/cic.c new file mode 100644 index 0000000..19e9ead --- /dev/null +++ b/sw/controller/src/cic.c @@ -0,0 +1,383 @@ +// Original code from https://github.com/jago85/UltraCIC_C licensed under the MIT License + +#include +#include "cic.h" +#include "hw.h" +#include "led.h" +#include "rtc.h" +#include "task.h" + + +typedef enum { + REGION_NTSC, + REGION_PAL, + __REGION_MAX +} cic_region_t; + + +static volatile bool cic_enabled = false; +static volatile bool cic_detect_enabled; + +static volatile uint8_t cic_next_rd; +static volatile uint8_t cic_next_wr; + +static volatile bool cic_disabled = false; +static volatile bool cic_dd_mode = false; +static volatile uint8_t cic_seed = 0x3F; +static volatile uint8_t cic_checksum[6] = { 0xA5, 0x36, 0xC0, 0xF1, 0xD8, 0x59 }; + +static uint8_t cic_ram[32]; +static uint8_t cic_x105_ram[30]; + +static const uint8_t cic_ram_init[2][32] = {{ + 0x0E, 0x00, 0x09, 0x0A, 0x01, 0x08, 0x05, 0x0A, 0x01, 0x03, 0x0E, 0x01, 0x00, 0x0D, 0x0E, 0x0C, + 0x00, 0x0B, 0x01, 0x04, 0x0F, 0x08, 0x0B, 0x05, 0x07, 0x0C, 0x0D, 0x06, 0x01, 0x0E, 0x09, 0x08 +}, { + 0x0E, 0x00, 0x04, 0x0F, 0x05, 0x01, 0x02, 0x01, 0x07, 0x01, 0x09, 0x08, 0x05, 0x07, 0x05, 0x0A, + 0x00, 0x0B, 0x01, 0x02, 0x03, 0x0F, 0x08, 0x02, 0x07, 0x01, 0x09, 0x08, 0x01, 0x01, 0x05, 0x0C +}}; + + +static void cic_irq_reset_falling (void) { + cic_enabled = false; + hw_gpio_set(GPIO_ID_N64_CIC_DQ); + led_clear_error(LED_ERROR_CIC); +} + +static void cic_irq_reset_rising (void) { + if (!cic_disabled) { + cic_enabled = true; + task_set_ready_and_reset(TASK_ID_CIC); + } +} + +static void cic_irq_clk_falling (void) { + if (cic_enabled) { + if (!cic_next_wr) { + hw_gpio_reset(GPIO_ID_N64_CIC_DQ); + } + cic_next_rd = hw_gpio_get(GPIO_ID_N64_CIC_DQ) ? 1 : 0; + task_set_ready(TASK_ID_CIC); + } +} + +static void cic_irq_clk_rising (void) { + hw_gpio_set(GPIO_ID_N64_CIC_DQ); + if (cic_detect_enabled) { + cic_detect_enabled = false; + if (!hw_gpio_get(GPIO_ID_N64_CIC_DQ)) { + cic_enabled = false; + } + } +} + +static uint8_t cic_read (void) { + cic_next_wr = 1; + task_yield(); + return cic_next_rd; +} + +static void cic_write (uint8_t bit) { + cic_next_wr = bit; + task_yield(); +} + +static void cic_start_detect (void) { + cic_detect_enabled = cic_dd_mode; +} + +static uint8_t cic_read_nibble (void) { + uint8_t data = 0; + for (int i = 0; i < 4; i++) { + data = ((data << 1) | cic_read()); + } + return data; +} + +static void cic_write_nibble (uint8_t data) { + cic_write(data & 0x08); + cic_write(data & 0x04); + cic_write(data & 0x02); + cic_write(data & 0x01); +} + +static void cic_write_ram_nibbles (uint8_t index) { + do { + cic_write_nibble(cic_ram[index++]); + } while ((index & 0x0F) != 0); +} + +static void cic_encode_round (uint8_t index) { + uint8_t data = cic_ram[index++]; + do { + data = ((((data + 1) & 0x0F) + cic_ram[index]) & 0x0F); + cic_ram[index++] = data; + } while ((index & 0x0F) != 0); +} + +static void cic_write_id (cic_region_t region) { + cic_start_detect(); + cic_write(cic_dd_mode ? 1 : 0); + cic_write(region == REGION_PAL ? 1 : 0); + cic_write(0); + cic_write(1); +} + +static void cic_write_id_failed (void) { + uint8_t current_region = rtc_get_region(); + uint8_t next_region = (current_region == REGION_NTSC) ? REGION_PAL : REGION_NTSC; + rtc_set_region(next_region); + led_blink_error(LED_ERROR_CIC); +} + +static void cic_write_seed (void) { + cic_ram[0x0A] = 0x0B; + cic_ram[0x0B] = 0x05; + cic_ram[0x0C] = (cic_seed >> 4); + cic_ram[0x0D] = cic_seed; + cic_ram[0x0E] = (cic_seed >> 4); + cic_ram[0x0F] = cic_seed; + cic_encode_round(0x0A); + cic_encode_round(0x0A); + cic_write_ram_nibbles(0x0A); +} + +static void cic_write_checksum (void) { + for (int i = 0; i < 4; i++) { + cic_ram[i] = 0x00; + } + for (int i = 0; i < 6; i++) { + cic_ram[(i * 2) + 4] = ((cic_checksum[i] >> 4) & 0x0F); + cic_ram[(i * 2) + 5] = (cic_checksum[i] & 0x0F); + } + cic_encode_round(0x00); + cic_encode_round(0x00); + cic_encode_round(0x00); + cic_encode_round(0x00); + cic_write(0); + cic_write_ram_nibbles(0x00); +} + +static void cic_init_ram (cic_region_t region) { + if (region < __REGION_MAX) { + for (int i = 0; i < 32; i++) { + cic_ram[i] = cic_ram_init[region][i]; + } + } + cic_ram[0x01] = cic_read_nibble(); + cic_ram[0x11] = cic_read_nibble(); +} + +static void cic_exchange_bytes (uint8_t *a, uint8_t *b) { + uint8_t tmp = *a; + *a = *b; + *b = tmp; +} + +static void cic_round (uint8_t *m) { + uint8_t a, b, x; + + x = m[15]; + a = x; + + do { + b = 1; + a += (m[b] + 1); + m[b] = a; + b++; + a += (m[b] + 1); + cic_exchange_bytes(&a, &m[b]); + m[b] = ~(m[b]); + b++; + a &= 0x0F; + a += ((m[b] & 0x0F) + 1); + if (a < 16) { + cic_exchange_bytes(&a, &m[b]); + b++; + } + a += m[b]; + m[b] = a; + b++; + a += m[b]; + cic_exchange_bytes(&a, &m[b]); + b++; + a &= 0x0F; + a += 8; + if (a < 16) { + a += m[b]; + } + cic_exchange_bytes(&a, &m[b]); + b++; + do { + a += (m[b] + 1); + m[b] = a; + b++; + b &= 0x0F; + } while (b != 0); + a = (x + 0x0F); + x = (a & 0x0F); + } while (x != 0x0F); +} + +static void cic_compare_mode (cic_region_t region) { + cic_round(&cic_ram[0x10]); + cic_round(&cic_ram[0x10]); + cic_round(&cic_ram[0x10]); + + uint8_t index = (cic_ram[0x17] & 0x0F); + if (index == 0) { + index = 1; + } + index |= 0x10; + + do { + cic_read(); + cic_write(cic_ram[index] & 0x01); + if (region == REGION_PAL) { + index--; + } else { + index++; + } + } while (index & 0x0F); +} + +static void cic_x105_algorithm (void) { + uint8_t a = 5; + uint8_t carry = 1; + + for (int i = 0; i < 30; ++i) { + if (!(cic_x105_ram[i] & 0x01)) { + a += 8; + } + if (!(a & 0x02)) { + a += 4; + } + a = ((a + cic_x105_ram[i]) & 0x0F); + cic_x105_ram[i] = a; + if (!carry) { + a += 7; + } + a = ((a + cic_x105_ram[i]) & 0x0F); + a = (a + cic_x105_ram[i] + carry); + if (a >= 0x10) { + carry = 1; + a -= 0x10; + } else { + carry = 0; + } + a = (~(a) & 0x0F); + cic_x105_ram[i] = a; + } +} + +static void cic_x105_mode (void) { + cic_write_nibble(0x0A); + cic_write_nibble(0x0A); + + for (int i = 0; i < 30; i++) { + cic_x105_ram[i] = cic_read_nibble(); + } + + cic_x105_algorithm(); + + cic_write(0); + + for (int i = 0; i < 30; i++) { + cic_write_nibble(cic_x105_ram[i]); + } +} + +static void cic_soft_reset_timeout (void) { + hw_gpio_reset(GPIO_ID_N64_CIC_DQ); + task_set_ready(TASK_ID_CIC); +} + +static void cic_soft_reset (void) { + cic_read(); + hw_tim_setup(TIM_ID_CIC, 550, cic_soft_reset_timeout); + task_yield(); +} + + +void cic_reset_parameters (void) { + cic_disabled = false; + cic_dd_mode = false; + cic_seed = 0x3F; + cic_checksum[0] = 0xA5; + cic_checksum[1] = 0x36; + cic_checksum[2] = 0xC0; + cic_checksum[3] = 0xF1; + cic_checksum[4] = 0xD8; + cic_checksum[5] = 0x59; +} + +void cic_set_parameters (uint32_t *args) { + cic_disabled = (args[0] >> 24) & (1 << 1); + cic_dd_mode = (args[0] >> 24) & (1 << 0); + cic_seed = (args[0] >> 16) & 0xFF; + cic_checksum[0] = (args[0] >> 8) & 0xFF; + cic_checksum[1] = args[0] & 0xFF; + cic_checksum[2] = (args[1] >> 24) & 0xFF; + cic_checksum[3] = (args[1] >> 16) & 0xFF; + cic_checksum[4] = (args[1] >> 8) & 0xFF; + cic_checksum[5] = args[1] & 0xFF; +} + +void cic_hw_init (void) { + hw_gpio_irq_setup(GPIO_ID_N64_RESET, GPIO_IRQ_FALLING, cic_irq_reset_falling); + hw_gpio_irq_setup(GPIO_ID_N64_RESET, GPIO_IRQ_RISING, cic_irq_reset_rising); + hw_gpio_irq_setup(GPIO_ID_N64_CIC_CLK, GPIO_IRQ_FALLING, cic_irq_clk_falling); + hw_gpio_irq_setup(GPIO_ID_N64_CIC_CLK, GPIO_IRQ_RISING, cic_irq_clk_rising); +} + +void cic_task (void) { + while (!hw_gpio_get(GPIO_ID_N64_RESET)) { + task_yield(); + } + + cic_region_t region = rtc_get_region(); + if (region >= __REGION_MAX) { + region = REGION_NTSC; + rtc_set_region(region); + } + + cic_write_id(region); + + hw_tim_setup(TIM_ID_CIC, 1000, cic_write_id_failed); + cic_write_seed(); + hw_tim_stop(TIM_ID_CIC); + + cic_write_checksum(); + cic_init_ram(region); + + while (1) { + uint8_t cmd = 0; + cmd |= (cic_read() << 1); + cmd |= cic_read(); + + switch (cmd) { + case 0: { + cic_compare_mode(region); + break; + } + + case 2: { + cic_x105_mode(); + break; + } + + case 3: { + cic_soft_reset(); + break; + } + + case 1: + default: { + while (1) { + task_yield(); + } + break; + } + } + } +} diff --git a/sw/controller/src/cic.h b/sw/controller/src/cic.h new file mode 100644 index 0000000..d5a70e8 --- /dev/null +++ b/sw/controller/src/cic.h @@ -0,0 +1,14 @@ +#ifndef CIC_H__ +#define CIC_H__ + + +#include + + +void cic_reset_parameters (void); +void cic_set_parameters (uint32_t *args); +void cic_hw_init (void); +void cic_task (void); + + +#endif diff --git a/sw/controller/src/dd.c b/sw/controller/src/dd.c new file mode 100644 index 0000000..43f2ef0 --- /dev/null +++ b/sw/controller/src/dd.c @@ -0,0 +1,562 @@ +#include +#include "dd.h" +#include "fpga.h" +#include "hw.h" +#include "led.h" +#include "rtc.h" +#include "sd.h" +#include "usb.h" + + +#define DD_SECTOR_MAX_SIZE (232) +#define DD_BLOCK_DATA_SECTORS_NUM (85) +#define DD_BLOCK_BUFFER_SIZE (ALIGN(DD_SECTOR_MAX_SIZE * DD_BLOCK_DATA_SECTORS_NUM, SD_SECTOR_SIZE) + SD_SECTOR_SIZE) +#define DD_BLOCK_BUFFER_ADDRESS (0x03BC0000UL - DD_BLOCK_BUFFER_SIZE) +#define DD_SECTOR_BUFFER_ADDRESS (0x05002800UL) +#define DD_SD_SECTOR_TABLE_SIZE (DD_BLOCK_BUFFER_SIZE / SD_SECTOR_SIZE) +#define DD_SD_MAX_DISKS (4) + +#define DD_DRIVE_ID_RETAIL (0x0003) +#define DD_DRIVE_ID_DEVELOPMENT (0x0004) +#define DD_VERSION_RETAIL (0x0114) + +#define DD_SPIN_UP_TIME (2000) + + +typedef enum { + DD_CMD_SEEK_READ = 0x01, + DD_CMD_SEEK_WRITE = 0x02, + DD_CMD_CLEAR_DISK_CHANGE = 0x08, + DD_CMD_CLEAR_RESET_STATE = 0x09, + DD_CMD_READ_VERSION = 0x0A, + DD_CMD_SET_DISK_TYPE = 0x0B, + DD_CMD_REQUEST_STATUS = 0x0C, + DD_CMD_SET_RTC_YEAR_MONTH = 0x0F, + DD_CMD_SET_RTC_DAY_HOUR = 0x10, + DD_CMD_SET_RTC_MINUTE_SECOND = 0x11, + DD_CMD_GET_RTC_YEAR_MONTH = 0x12, + DD_CMD_GET_RTC_DAY_HOUR = 0x13, + DD_CMD_GET_RTC_MINUTE_SECOND = 0x14, + DD_CMD_READ_PROGRAM_VERSION = 0x1B, +} dd_cmd_t; + + +enum state { + STATE_IDLE, + STATE_START, + STATE_BLOCK_READ_WAIT, + STATE_SECTOR_READ, + STATE_SECTOR_WRITE, + STATE_BLOCK_WRITE, + STATE_BLOCK_WRITE_WAIT, + STATE_NEXT_BLOCK, +}; + +typedef union { + uint32_t full; + struct { + uint8_t sector_num; + uint8_t sector_size; + uint8_t sector_size_full; + uint8_t sectors_in_block; + }; +} sector_info_t; + +typedef struct { + uint32_t thb_table_address; + uint32_t sector_table_address; +} sd_disk_info_t; + +struct process { + enum state state; + rtc_time_t time; + bool disk_spinning; + bool cmd_response_delayed; + bool cmd_response_ready; + bool bm_running; + bool transfer_mode; + bool full_track_transfer; + bool starting_block; + uint16_t head_track; + uint8_t current_sector; + sector_info_t sector_info; + bool block_ready; + bool block_valid; + uint32_t block_offset; + dd_drive_type_t drive_type; + bool sd_mode; + uint8_t sd_current_disk; + sd_disk_info_t sd_disk_info[DD_SD_MAX_DISKS]; +}; + + +static struct process p; + + +static uint16_t dd_track_head_block (void) { + uint16_t track = ((p.head_track & DD_TRACK_MASK) << 2); + uint16_t head = (((p.head_track & DD_HEAD_MASK) ? 1 : 0) << 1); + uint16_t block = (p.starting_block ? 1 : 0); + return (track | head | block); +} + +static uint32_t dd_fill_sd_sector_table (uint32_t index, uint32_t *sector_table) { + uint32_t tmp; + sd_disk_info_t info = p.sd_disk_info[p.sd_current_disk]; + if (info.thb_table_address == 0xFFFFFFFF) { + return 0; + } + uint32_t thb_entry_address = (info.thb_table_address + (index * sizeof(uint32_t))); + fpga_mem_read(thb_entry_address, sizeof(uint32_t), (uint8_t *) (&tmp)); + uint32_t start_offset = SWAP32(tmp); + if (start_offset == 0xFFFFFFFF) { + return 0; + } + p.block_offset = (start_offset % SD_SECTOR_SIZE); + uint32_t block_length = ((p.sector_info.sector_size + 1) * DD_BLOCK_DATA_SECTORS_NUM); + uint32_t end_offset = ((start_offset + block_length) - 1); + uint32_t starting_sector = (start_offset / SD_SECTOR_SIZE); + uint32_t sectors = (1 + ((end_offset / SD_SECTOR_SIZE) - starting_sector)); + for (int i = 0; i < sectors; i++) { + uint32_t sector_entry_address = info.sector_table_address + ((starting_sector + i) * sizeof(uint32_t)); + fpga_mem_read(sector_entry_address, sizeof(uint32_t), (uint8_t *) (&tmp)); + sector_table[i] = SWAP32(tmp); + } + return sectors; +} + +static void dd_process_sd_request (uint16_t index, uint32_t buffer_address, bool write) { + uint32_t sector_table[DD_SD_SECTOR_TABLE_SIZE]; + uint32_t sectors = dd_fill_sd_sector_table(index, sector_table); + dd_set_block_ready(false); + if (sectors == 0) { + return; + } + uint32_t starting_sector = 0; + uint32_t sectors_to_process = 0; + for (uint32_t i = 0; i < sectors; i++) { + sectors_to_process += 1; + if ((i < (sectors - 1)) && ((sector_table[i] + 1) == sector_table[i + 1])) { + continue; + } + if (write) { + if (sd_write_sectors(buffer_address, sector_table[starting_sector], sectors_to_process)) { + return; + } + } else { + if (sd_read_sectors(buffer_address, sector_table[starting_sector], sectors_to_process)) { + return; + } + } + buffer_address += (sectors_to_process * SD_SECTOR_SIZE); + starting_sector += sectors_to_process; + sectors_to_process = 0; + } + dd_set_block_ready(true); +} + +static bool dd_block_read_request (void) { + uint16_t index = dd_track_head_block(); + uint32_t buffer_address = DD_BLOCK_BUFFER_ADDRESS; + if (p.sd_mode) { + dd_process_sd_request(index, buffer_address, false); + } else { + usb_tx_info_t packet_info; + usb_create_packet(&packet_info, PACKET_CMD_DD_REQUEST); + packet_info.data_length = 12; + packet_info.data[0] = 1; + packet_info.data[1] = buffer_address; + packet_info.data[2] = index; + p.block_ready = false; + p.block_offset = 0; + return usb_enqueue_packet(&packet_info); + } + return true; +} + +static bool dd_block_write_request (void) { + uint32_t index = dd_track_head_block(); + uint32_t buffer_address = DD_BLOCK_BUFFER_ADDRESS; + if (p.sd_mode) { + dd_process_sd_request(index, buffer_address, true); + } else { + usb_tx_info_t packet_info; + usb_create_packet(&packet_info, PACKET_CMD_DD_REQUEST); + packet_info.data_length = 12; + packet_info.data[0] = 2; + packet_info.data[1] = buffer_address; + packet_info.data[2] = index; + packet_info.dma_length = (p.sector_info.sector_size + 1) * DD_BLOCK_DATA_SECTORS_NUM; + packet_info.dma_address = buffer_address; + p.block_ready = false; + p.block_offset = 0; + return usb_enqueue_packet(&packet_info); + } + return true; +} + +static void dd_set_cmd_response_ready (void) { + p.cmd_response_ready = true; +} + + +void dd_set_block_ready (bool valid) { + p.block_ready = true; + p.block_valid = valid; +} + +dd_drive_type_t dd_get_drive_type (void) { + return p.drive_type; +} + +bool dd_set_drive_type (dd_drive_type_t type) { + switch (type) { + case DD_DRIVE_TYPE_RETAIL: + fpga_reg_set(REG_DD_DRIVE_ID, DD_DRIVE_ID_RETAIL); + p.drive_type = type; + break; + + case DD_DRIVE_TYPE_DEVELOPMENT: + fpga_reg_set(REG_DD_DRIVE_ID, DD_DRIVE_ID_DEVELOPMENT); + p.drive_type = type; + break; + + default: + return true; + } + return false; +} + +dd_disk_state_t dd_get_disk_state (void) { + uint32_t scr = fpga_reg_get(REG_DD_SCR); + if (scr & DD_SCR_DISK_CHANGED) { + return DD_DISK_STATE_CHANGED; + } + if (scr & DD_SCR_DISK_INSERTED) { + return DD_DISK_STATE_INSERTED; + } + return DD_DISK_STATE_EJECTED; +} + +bool dd_set_disk_state (dd_disk_state_t state) { + if (state > DD_DISK_STATE_CHANGED) { + return true; + } + uint32_t scr = fpga_reg_get(REG_DD_SCR); + scr &= ~(DD_SCR_DISK_CHANGED | DD_SCR_DISK_INSERTED); + switch (state) { + case DD_DISK_STATE_EJECTED: + break; + + case DD_DISK_STATE_INSERTED: + scr |= DD_SCR_DISK_INSERTED; + break; + + case DD_DISK_STATE_CHANGED: + scr |= (DD_SCR_DISK_CHANGED | DD_SCR_DISK_INSERTED); + break; + } + fpga_reg_set(REG_DD_SCR, scr); + return false; +} + +bool dd_get_sd_mode (void) { + return p.sd_mode; +} + +void dd_set_sd_mode (bool value) { + p.sd_mode = value; +} + +void dd_set_sd_disk_info (uint32_t address, uint32_t length) { + sd_disk_info_t info; + length /= sizeof(info); + p.sd_current_disk = 0; + for (int i = 0; i < DD_SD_MAX_DISKS; i++) { + if (i < length) { + fpga_mem_read(address, sizeof(info), (uint8_t *) (&info)); + p.sd_disk_info[i].thb_table_address = (SWAP32(info.thb_table_address) & 0x1FFFFFFF); + p.sd_disk_info[i].sector_table_address = (SWAP32(info.sector_table_address) & 0x1FFFFFFF); + address += sizeof(info); + } else { + p.sd_disk_info[i].thb_table_address = 0xFFFFFFFF; + p.sd_disk_info[i].sector_table_address = 0xFFFFFFFF; + } + } +} + +void dd_handle_button (void) { + led_blink_act(); + if (dd_get_disk_state() == DD_DISK_STATE_EJECTED) { + dd_set_disk_state(DD_DISK_STATE_INSERTED); + } else { + dd_set_disk_state(DD_DISK_STATE_EJECTED); + for (uint8_t i = 0; i < DD_SD_MAX_DISKS; i++) { + uint8_t sd_next_disk = ((p.sd_current_disk + i + 1) % DD_SD_MAX_DISKS); + if (p.sd_disk_info[sd_next_disk].thb_table_address != 0xFFFFFFFF) { + p.sd_current_disk = sd_next_disk; + break; + } + } + } +} + +void dd_init (void) { + fpga_reg_set(REG_DD_SCR, 0); + fpga_reg_set(REG_DD_HEAD_TRACK, 0); + fpga_reg_set(REG_DD_DRIVE_ID, DD_DRIVE_ID_RETAIL); + p.state = STATE_IDLE; + p.cmd_response_delayed = false; + p.cmd_response_ready = false; + p.disk_spinning = false; + p.bm_running = false; + p.drive_type = DD_DRIVE_TYPE_RETAIL; + p.sd_mode = false; + p.sd_current_disk = 0; + dd_set_sd_disk_info(0, 0); +} + +void dd_process (void) { + uint32_t starting_scr = fpga_reg_get(REG_DD_SCR); + uint32_t scr = starting_scr; + + if (scr & DD_SCR_HARD_RESET) { + p.state = STATE_IDLE; + p.cmd_response_delayed = false; + p.cmd_response_ready = false; + p.disk_spinning = false; + p.bm_running = false; + p.head_track = 0; + scr &= ~(DD_SCR_DISK_CHANGED); + } + + if (scr & DD_SCR_CMD_PENDING) { + uint32_t cmd_data = fpga_reg_get(REG_DD_CMD_DATA); + uint8_t cmd = (cmd_data >> 16) & 0xFF; + uint16_t data = cmd_data & 0xFFFF; + + if (p.cmd_response_delayed) { + if (p.cmd_response_ready) { + p.cmd_response_delayed = false; + fpga_reg_set(REG_DD_HEAD_TRACK, DD_HEAD_TRACK_INDEX_LOCK | data); + scr |= DD_SCR_CMD_READY; + } + } else if ((cmd == DD_CMD_SEEK_READ) || (cmd == DD_CMD_SEEK_WRITE)) { + p.cmd_response_delayed = true; + p.cmd_response_ready = false; + if (!p.disk_spinning) { + p.disk_spinning = true; + hw_tim_setup(TIM_ID_DD, DD_SPIN_UP_TIME, dd_set_cmd_response_ready); + } else { + p.cmd_response_ready = true; + } + fpga_reg_set(REG_DD_HEAD_TRACK, p.head_track & ~(DD_HEAD_TRACK_INDEX_LOCK)); + p.head_track = data & DD_HEAD_TRACK_MASK; + } else { + switch (cmd) { + case DD_CMD_CLEAR_DISK_CHANGE: + scr &= ~(DD_SCR_DISK_CHANGED); + break; + + case DD_CMD_CLEAR_RESET_STATE: + scr &= ~(DD_SCR_DISK_CHANGED); + scr |= DD_SCR_HARD_RESET_CLEAR; + break; + + case DD_CMD_READ_VERSION: + data = DD_VERSION_RETAIL; + break; + + case DD_CMD_SET_DISK_TYPE: + break; + + case DD_CMD_REQUEST_STATUS: + data = 0; + break; + + case DD_CMD_SET_RTC_YEAR_MONTH: + p.time.year = ((data >> 8) & 0xFF); + p.time.month = (data & 0xFF); + break; + + case DD_CMD_SET_RTC_DAY_HOUR: + p.time.day = ((data >> 8) & 0xFF); + p.time.hour = (data & 0xFF); + break; + + case DD_CMD_SET_RTC_MINUTE_SECOND: + p.time.minute = ((data >> 8) & 0xFF); + p.time.second = (data & 0xFF); + rtc_set_time(&p.time); + break; + + case DD_CMD_GET_RTC_YEAR_MONTH: + data = (p.time.year << 8) | p.time.month; + break; + + case DD_CMD_GET_RTC_DAY_HOUR: + data = (p.time.day << 8) | p.time.hour; + break; + + case DD_CMD_GET_RTC_MINUTE_SECOND: + rtc_get_time(&p.time); + data = (p.time.minute << 8) | p.time.second; + break; + + case DD_CMD_READ_PROGRAM_VERSION: + data = 0; + break; + + default: + break; + } + + fpga_reg_set(REG_DD_CMD_DATA, data); + scr |= DD_SCR_CMD_READY; + } + } + + if (scr & DD_SCR_BM_STOP) { + scr |= DD_SCR_BM_STOP_CLEAR; + scr &= ~(DD_SCR_BM_MICRO_ERROR | DD_SCR_BM_TRANSFER_C2 | DD_SCR_BM_TRANSFER_DATA); + p.bm_running = false; + } else if (scr & DD_SCR_BM_START) { + scr |= DD_SCR_BM_CLEAR | DD_SCR_BM_ACK_CLEAR | DD_SCR_BM_START_CLEAR; + scr &= ~(DD_SCR_BM_MICRO_ERROR | DD_SCR_BM_TRANSFER_C2 | DD_SCR_BM_TRANSFER_DATA); + p.state = STATE_START; + p.bm_running = true; + p.transfer_mode = (scr & DD_SCR_BM_TRANSFER_MODE); + p.full_track_transfer = (scr & DD_SCR_BM_TRANSFER_BLOCKS); + p.sector_info.full = fpga_reg_get(REG_DD_SECTOR_INFO); + p.starting_block = (p.sector_info.sector_num == (p.sector_info.sectors_in_block + 1)); + } else if (p.bm_running) { + if (scr & DD_SCR_BM_PENDING) { + scr |= DD_SCR_BM_CLEAR; + if (p.transfer_mode) { + if (p.current_sector < (p.sector_info.sectors_in_block - 4)) { + p.state = STATE_SECTOR_READ; + } else if (p.current_sector == (p.sector_info.sectors_in_block - 4)) { + p.current_sector += 1; + scr &= ~(DD_SCR_BM_TRANSFER_DATA); + scr |= DD_SCR_BM_READY; + } else if (p.current_sector >= p.sector_info.sectors_in_block) { + p.state = STATE_NEXT_BLOCK; + } else { + } + } else { + if (p.current_sector < (p.sector_info.sectors_in_block - 4)) { + p.state = STATE_SECTOR_WRITE; + } + } + } + if (scr & DD_SCR_BM_ACK) { + scr |= DD_SCR_BM_ACK_CLEAR; + if (p.transfer_mode) { + if ((p.current_sector <= (p.sector_info.sectors_in_block - 4))) { + } else if (p.current_sector < p.sector_info.sectors_in_block) { + p.current_sector += 1; + scr |= DD_SCR_BM_READY; + } else if (p.current_sector == p.sector_info.sectors_in_block) { + p.current_sector += 1; + scr |= DD_SCR_BM_TRANSFER_C2 | DD_SCR_BM_READY; + } + } else { + if (p.current_sector == (p.sector_info.sectors_in_block - 4)) { + p.bm_running = false; + } + } + } + + switch (p.state) { + case STATE_IDLE: + break; + + case STATE_START: + p.current_sector = 0; + if (dd_block_read_request()) { + p.state = STATE_BLOCK_READ_WAIT; + } + break; + + case STATE_BLOCK_READ_WAIT: + if (p.block_ready) { + if (p.transfer_mode) { + if (p.block_valid) { + p.state = STATE_SECTOR_READ; + scr |= DD_SCR_BM_TRANSFER_DATA; + } else { + p.state = STATE_SECTOR_READ; + scr |= DD_SCR_BM_MICRO_ERROR; + } + } else { + p.state = STATE_IDLE; + if (p.block_valid) { + scr |= DD_SCR_BM_TRANSFER_DATA | DD_SCR_BM_READY; + } else { + scr |= DD_SCR_BM_MICRO_ERROR | DD_SCR_BM_READY; + } + } + } + break; + + case STATE_SECTOR_READ: + fpga_mem_copy( + DD_BLOCK_BUFFER_ADDRESS + p.block_offset + (p.current_sector * (p.sector_info.sector_size + 1)), + DD_SECTOR_BUFFER_ADDRESS, + p.sector_info.sector_size + 1 + ); + p.state = STATE_IDLE; + p.current_sector += 1; + scr |= DD_SCR_BM_READY; + break; + + case STATE_SECTOR_WRITE: + fpga_mem_copy( + DD_SECTOR_BUFFER_ADDRESS, + DD_BLOCK_BUFFER_ADDRESS + p.block_offset + (p.current_sector * (p.sector_info.sector_size + 1)), + p.sector_info.sector_size + 1 + ); + p.current_sector += 1; + if (p.current_sector < (p.sector_info.sectors_in_block - 4)) { + p.state = STATE_IDLE; + scr |= DD_SCR_BM_READY; + } else { + p.state = STATE_BLOCK_WRITE; + } + break; + + case STATE_BLOCK_WRITE: + if (dd_block_write_request()) { + p.state = STATE_BLOCK_WRITE_WAIT; + } + break; + + case STATE_BLOCK_WRITE_WAIT: + if (p.block_ready) { + p.state = STATE_NEXT_BLOCK; + } + break; + + case STATE_NEXT_BLOCK: + if (p.full_track_transfer) { + p.state = STATE_START; + p.full_track_transfer = false; + p.starting_block = !p.starting_block; + scr &= ~(DD_SCR_BM_TRANSFER_C2); + } else { + if (p.transfer_mode) { + p.bm_running = false; + } else { + p.state = STATE_IDLE; + scr &= ~(DD_SCR_BM_TRANSFER_C2 | DD_SCR_BM_TRANSFER_DATA); + scr |= DD_SCR_BM_READY; + } + } + break; + } + } + + if (scr != starting_scr) { + fpga_reg_set(REG_DD_SCR, scr); + } +} diff --git a/sw/controller/src/dd.h b/sw/controller/src/dd.h new file mode 100644 index 0000000..3bddaff --- /dev/null +++ b/sw/controller/src/dd.h @@ -0,0 +1,34 @@ +#ifndef DD_H__ +#define DD_H__ + + +#include +#include + + +typedef enum { + DD_DRIVE_TYPE_RETAIL = 0, + DD_DRIVE_TYPE_DEVELOPMENT = 1, +} dd_drive_type_t; + +typedef enum { + DD_DISK_STATE_EJECTED = 0, + DD_DISK_STATE_INSERTED = 1, + DD_DISK_STATE_CHANGED = 2, +} dd_disk_state_t; + + +void dd_set_block_ready (bool valid); +dd_drive_type_t dd_get_drive_type (void); +bool dd_set_drive_type (dd_drive_type_t type); +dd_disk_state_t dd_get_disk_state (void); +bool dd_set_disk_state (dd_disk_state_t state); +bool dd_get_sd_mode (void); +void dd_set_sd_mode (bool value); +void dd_set_sd_disk_info (uint32_t address, uint32_t length); +void dd_handle_button (void); +void dd_init (void); +void dd_process (void); + + +#endif diff --git a/sw/controller/src/debug.c b/sw/controller/src/debug.c new file mode 100644 index 0000000..59c5b0f --- /dev/null +++ b/sw/controller/src/debug.c @@ -0,0 +1,34 @@ +#include +#include "debug.h" +#include "hw.h" + + +static char hex_chars[16] = { + '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F', +}; + + +void debug_print_text (char *text) { + hw_uart_write((uint8_t *) (text), strlen(text)); +} + +void debug_print_8bit (uint8_t value) { + char buffer[3] = { + hex_chars[(value >> 4) & 0x0F], + hex_chars[value & 0x0F], + '\0' + }; + debug_print_text(buffer); +} + +void debug_print_16bit (uint16_t value) { + debug_print_8bit((value >> 8) & 0xFF); + debug_print_8bit(value & 0xFF); +} + +void debug_print_32bit (uint32_t value) { + debug_print_8bit((value >> 24) & 0xFF); + debug_print_8bit((value >> 16) & 0xFF); + debug_print_8bit((value >> 8) & 0xFF); + debug_print_8bit(value & 0xFF); +} diff --git a/sw/controller/src/debug.h b/sw/controller/src/debug.h new file mode 100644 index 0000000..46a64c4 --- /dev/null +++ b/sw/controller/src/debug.h @@ -0,0 +1,14 @@ +#ifndef DEBUG_H__ +#define DEBUG_H__ + + +#include + + +void debug_print_text (char *text); +void debug_print_8bit (uint8_t value); +void debug_print_16bit (uint16_t value); +void debug_print_32bit (uint32_t value); + + +#endif diff --git a/sw/controller/src/flash.c b/sw/controller/src/flash.c new file mode 100644 index 0000000..bca24aa --- /dev/null +++ b/sw/controller/src/flash.c @@ -0,0 +1,21 @@ +#include "flash.h" +#include "fpga.h" + + +#define FLASH_ADDRESS (0x04000000UL) +#define ERASE_BLOCK_SIZE (64 * 1024) + + +void flash_wait_busy (void) { + uint8_t dummy[2]; + fpga_mem_read(FLASH_ADDRESS, 2, dummy); +} + +void flash_erase_block (uint32_t offset) { + for (int i = 0; i < (FLASH_ERASE_BLOCK_SIZE / ERASE_BLOCK_SIZE); i++) { + fpga_reg_set(REG_FLASH_SCR, offset); + while (fpga_reg_get(REG_FLASH_SCR) & FLASH_SCR_BUSY); + offset += ERASE_BLOCK_SIZE; + } + flash_wait_busy(); +} diff --git a/sw/controller/src/flash.h b/sw/controller/src/flash.h new file mode 100644 index 0000000..a60d010 --- /dev/null +++ b/sw/controller/src/flash.h @@ -0,0 +1,15 @@ +#ifndef FLASH_H__ +#define FLASH_H__ + + +#include + + +#define FLASH_ERASE_BLOCK_SIZE (128 * 1024) + + +void flash_wait_busy (void); +void flash_erase_block (uint32_t offset); + + +#endif diff --git a/sw/controller/src/flashram.c b/sw/controller/src/flashram.c new file mode 100644 index 0000000..21ccab4 --- /dev/null +++ b/sw/controller/src/flashram.c @@ -0,0 +1,71 @@ +#include +#include "fpga.h" + + +#define FLASHRAM_SIZE (128 * 1024) +#define FLASHRAM_SECTOR_SIZE (16 * 1024) +#define FLASHRAM_PAGE_SIZE (128) +#define FLASHRAM_ADDRESS (0x03FE0000UL) +#define FLASHRAM_BUFFER_ADDRESS (0x05002900UL) + + +enum operation { + OP_NONE, + OP_ERASE_ALL, + OP_ERASE_SECTOR, + OP_WRITE_PAGE +}; + + +static enum operation flashram_operation_type (uint32_t scr) { + if (!(scr & FLASHRAM_SCR_PENDING)) { + return OP_NONE; + } + + if (scr & FLASHRAM_SCR_WRITE_OR_ERASE) { + if (scr & FLASHRAM_SCR_SECTOR_OR_ALL) { + return OP_ERASE_ALL; + } else { + return OP_ERASE_SECTOR; + } + } else { + return OP_WRITE_PAGE; + } +} + + +void flashram_init (void) { + fpga_reg_set(REG_FLASHRAM_SCR, FLASHRAM_SCR_DONE); +} + +void flashram_process (void) { + uint32_t scr = fpga_reg_get(REG_FLASHRAM_SCR); + enum operation op = flashram_operation_type(scr); + uint8_t buffer[FLASHRAM_PAGE_SIZE]; + uint32_t address = FLASHRAM_ADDRESS; + uint32_t erase_size = (op == OP_ERASE_SECTOR) ? FLASHRAM_SECTOR_SIZE : FLASHRAM_SIZE; + uint32_t page = (op != OP_ERASE_ALL) ? ((scr & FLASHRAM_SCR_PAGE_MASK) >> FLASHRAM_SCR_PAGE_BIT) : 0; + address += page * FLASHRAM_PAGE_SIZE; + + switch (op) { + case OP_ERASE_ALL: + case OP_ERASE_SECTOR: + for (int i = 0; i < FLASHRAM_PAGE_SIZE; i++) { + buffer[i] = 0xFF; + } + for (int i = 0; i < erase_size; i += FLASHRAM_PAGE_SIZE) { + fpga_mem_write(address + i, FLASHRAM_PAGE_SIZE, buffer); + } + fpga_reg_set(REG_FLASHRAM_SCR, FLASHRAM_SCR_DONE); + break; + + case OP_WRITE_PAGE: + fpga_mem_copy(FLASHRAM_BUFFER_ADDRESS, address, FLASHRAM_PAGE_SIZE); + fpga_reg_set(REG_FLASHRAM_SCR, FLASHRAM_SCR_DONE); + break; + + case OP_NONE: + default: + break; + } +} diff --git a/sw/riscv/src/flashram.h b/sw/controller/src/flashram.h similarity index 56% rename from sw/riscv/src/flashram.h rename to sw/controller/src/flashram.h index 2d682bc..4fdb24d 100644 --- a/sw/riscv/src/flashram.h +++ b/sw/controller/src/flashram.h @@ -2,11 +2,8 @@ #define FLASHRAM_H__ -#include "sys.h" - - void flashram_init (void); -void process_flashram (void); +void flashram_process (void); #endif diff --git a/sw/controller/src/fpga.c b/sw/controller/src/fpga.c new file mode 100644 index 0000000..9edf7c6 --- /dev/null +++ b/sw/controller/src/fpga.c @@ -0,0 +1,124 @@ +#include "fpga.h" +#include "hw.h" + + +uint8_t fpga_id_get (void) { + fpga_cmd_t cmd = CMD_IDENTIFY; + uint8_t id; + + hw_spi_start(); + hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX); + hw_spi_trx(&id, 1, SPI_RX); + hw_spi_stop(); + + return id; +} + +uint32_t fpga_reg_get (fpga_reg_t reg) { + fpga_cmd_t cmd = CMD_REG_READ; + uint32_t value; + + hw_spi_start(); + hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX); + hw_spi_trx(®, 1, SPI_TX); + hw_spi_trx((uint8_t *) (&value), 4, SPI_RX); + hw_spi_stop(); + + return value; +} + +void fpga_reg_set (fpga_reg_t reg, uint32_t value) { + fpga_cmd_t cmd = CMD_REG_WRITE; + + hw_spi_start(); + hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX); + hw_spi_trx(®, 1, SPI_TX); + hw_spi_trx((uint8_t *) (&value), 4, SPI_TX); + hw_spi_stop(); +} + +void fpga_mem_read (uint32_t address, size_t length, uint8_t *buffer) { + fpga_cmd_t cmd = CMD_MEM_READ; + uint8_t buffer_address = 0; + size_t dma_length = length; + if ((dma_length % 2) != 0) { + dma_length += 1; + } + + fpga_reg_set(REG_MEM_ADDRESS, address); + fpga_reg_set(REG_MEM_SCR, (dma_length << MEM_SCR_LENGTH_BIT) | MEM_SCR_START); + while (fpga_reg_get(REG_MEM_SCR) & MEM_SCR_BUSY); + + hw_spi_start(); + hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX); + hw_spi_trx(&buffer_address, 1, SPI_TX); + hw_spi_trx(buffer, length, SPI_RX); + hw_spi_stop(); +} + +void fpga_mem_write (uint32_t address, size_t length, uint8_t *buffer) { + fpga_cmd_t cmd = CMD_MEM_WRITE; + uint8_t buffer_address = 0; + size_t dma_length = length; + if ((dma_length % 2) != 0) { + dma_length += 1; + } + + hw_spi_start(); + hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX); + hw_spi_trx(&buffer_address, 1, SPI_TX); + hw_spi_trx(buffer, length, SPI_TX); + hw_spi_stop(); + + fpga_reg_set(REG_MEM_ADDRESS, address); + fpga_reg_set(REG_MEM_SCR, (dma_length << MEM_SCR_LENGTH_BIT) | MEM_SCR_DIRECTION | MEM_SCR_START); + while (fpga_reg_get(REG_MEM_SCR) & MEM_SCR_BUSY); +} + +void fpga_mem_copy (uint32_t src, uint32_t dst, size_t length) { + size_t dma_length = length; + if ((dma_length % 2) != 0) { + dma_length += 1; + } + + fpga_reg_set(REG_MEM_ADDRESS, src); + fpga_reg_set(REG_MEM_SCR, (dma_length << MEM_SCR_LENGTH_BIT) | MEM_SCR_START); + while (fpga_reg_get(REG_MEM_SCR) & MEM_SCR_BUSY); + + fpga_reg_set(REG_MEM_ADDRESS, dst); + fpga_reg_set(REG_MEM_SCR, (dma_length << MEM_SCR_LENGTH_BIT) | MEM_SCR_DIRECTION | MEM_SCR_START); + while (fpga_reg_get(REG_MEM_SCR) & MEM_SCR_BUSY); +} + +uint8_t fpga_usb_status_get (void) { + fpga_cmd_t cmd = CMD_USB_STATUS; + uint8_t status; + + hw_spi_start(); + hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX); + hw_spi_trx(&status, 1, SPI_RX); + hw_spi_stop(); + + return status; +} + +uint8_t fpga_usb_pop (void) { + fpga_cmd_t cmd = CMD_USB_READ; + uint8_t data; + + hw_spi_start(); + hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX); + hw_spi_trx(&data, 1, SPI_RX); + hw_spi_stop(); + + return data; +} + +void fpga_usb_push (uint8_t data) { + fpga_cmd_t cmd = CMD_USB_WRITE; + + hw_spi_start(); + hw_spi_trx((uint8_t *) (&cmd), 1, SPI_TX); + hw_spi_trx(&data, 1, SPI_TX); + hw_spi_stop(); +} diff --git a/sw/controller/src/fpga.h b/sw/controller/src/fpga.h new file mode 100644 index 0000000..28a4979 --- /dev/null +++ b/sw/controller/src/fpga.h @@ -0,0 +1,199 @@ +#ifndef FPGA_H__ +#define FPGA_H__ + + +#include +#include + + +typedef enum { + CMD_IDENTIFY, + CMD_REG_READ, + CMD_REG_WRITE, + CMD_MEM_READ, + CMD_MEM_WRITE, + CMD_USB_STATUS, + CMD_USB_READ, + CMD_USB_WRITE +} fpga_cmd_t; + +typedef enum { + REG_MEM_ADDRESS, + REG_MEM_SCR, + REG_USB_SCR, + REG_USB_DMA_ADDRESS, + REG_USB_DMA_LENGTH, + REG_USB_DMA_SCR, + REG_CFG_SCR, + REG_CFG_DATA_0, + REG_CFG_DATA_1, + REG_CFG_CMD, + REG_CFG_VERSION, + REG_FLASHRAM_SCR, + REG_FLASH_SCR, + REG_RTC_SCR, + REG_RTC_TIME_0, + REG_RTC_TIME_1, + REG_SD_SCR, + REG_SD_ARG, + REG_SD_CMD, + REG_SD_RSP_0, + REG_SD_RSP_1, + REG_SD_RSP_2, + REG_SD_RSP_3, + REG_SD_DAT, + REG_SD_DMA_ADDRESS, + REG_SD_DMA_LENGTH, + REG_SD_DMA_SCR, + REG_DD_SCR, + REG_DD_CMD_DATA, + REG_DD_HEAD_TRACK, + REG_DD_SECTOR_INFO, + REG_DD_DRIVE_ID, + REG_VENDOR_SCR, + REG_VENDOR_DATA, + REG_DEBUG_0, + REG_DEBUG_1, +} fpga_reg_t; + + +#define ALIGN(value, align) (((value) + ((typeof(value))(align) - 1)) & ~((typeof(value))(align) - 1)) +#define SWAP16(x) ((((x) & 0xFF) << 8) | (((x) & 0xFF00) >> 8)) +#define SWAP32(x) (((x) & 0xFF) << 24 | ((x) & 0xFF00) << 8 | ((x) & 0xFF0000) >> 8 | ((x) & 0xFF000000) >> 24) + +#define FPGA_ID (0x64) + +#define FPGA_MAX_MEM_TRANSFER (1024) + +#define USB_STATUS_RXNE (1 << 0) +#define USB_STATUS_TXE (1 << 1) + +#define MEM_SCR_START (1 << 0) +#define MEM_SCR_STOP (1 << 1) +#define MEM_SCR_DIRECTION (1 << 2) +#define MEM_SCR_BUSY (1 << 3) +#define MEM_SCR_LENGTH_BIT (4) + +#define USB_SCR_FIFO_FLUSH (1 << 0) +#define USB_SCR_RXNE (1 << 1) +#define USB_SCR_TXE (1 << 2) +#define USB_SCR_RESET_PENDING (1 << 3) +#define USB_SCR_RESET_ACK (1 << 4) +#define USB_SCR_WRITE_FLUSH (1 << 5) +#define USB_SCR_RX_COUNT_BIT (6) +#define USB_SCR_RX_COUNT_MASK (0x7FF << USB_SCR_RX_COUNT_BIT) +#define USB_SCR_TX_COUNT_BIT (17) +#define USB_SCR_TX_COUNT_MASK (0x7FF << USB_SCR_TX_COUNT_BIT) +#define USB_SCR_RESET_STATE (1 << 28) +#define USB_SCR_PWRSAV (1 << 29) + +#define DMA_SCR_START (1 << 0) +#define DMA_SCR_STOP (1 << 1) +#define DMA_SCR_DIRECTION (1 << 2) +#define DMA_SCR_BUSY (1 << 3) + +#define CFG_SCR_BOOTLOADER_ENABLED (1 << 0) +#define CFG_SCR_BOOTLOADER_SKIP (1 << 1) +#define CFG_SCR_ROM_WRITE_ENABLED (1 << 2) +#define CFG_SCR_ROM_SHADOW_ENABLED (1 << 3) +#define CFG_SCR_SRAM_ENABLED (1 << 4) +#define CFG_SCR_SRAM_BANKED (1 << 5) +#define CFG_SCR_FLASHRAM_ENABLED (1 << 6) +#define CFG_SCR_DD_ENABLED (1 << 7) +#define CFG_SCR_DDIPL_ENABLED (1 << 8) +#define CFG_SCR_EEPROM_ENABLED (1 << 9) +#define CFG_SCR_EEPROM_16K (1 << 10) +#define CFG_SCR_ROM_EXTENDED_ENABLED (1 << 11) +#define CFG_SCR_BUTTON_STATE (1 << 31) + +#define CFG_CMD_BIT (0) +#define CFG_CMD_MASK (0xFF << CFG_CMD_BIT) +#define CFG_CMD_PENDING (1 << 8) +#define CFG_CMD_DONE (1 << 9) +#define CFG_CMD_ERROR (1 << 10) +#define CFG_CMD_IRQ (1 << 11) + +#define FLASHRAM_SCR_DONE (1 << 0) +#define FLASHRAM_SCR_PENDING (1 << 1) +#define FLASHRAM_SCR_PAGE_BIT (2) +#define FLASHRAM_SCR_PAGE_MASK (0x3FF << FLASHRAM_SCR_PAGE_BIT) +#define FLASHRAM_SCR_SECTOR_OR_ALL (1 << 12) +#define FLASHRAM_SCR_WRITE_OR_ERASE (1 << 13) + +#define FLASH_SCR_BUSY (1 << 0) + +#define RTC_SCR_PENDING (1 << 0) +#define RTC_SCR_DONE (1 << 1) +#define RTC_SCR_MAGIC (0x52544300) +#define RTC_SCR_MAGIC_MASK (0xFFFFFF00) + +#define SD_SCR_CLOCK_MODE_OFF (0 << 0) +#define SD_SCR_CLOCK_MODE_400KHZ (1 << 0) +#define SD_SCR_CLOCK_MODE_25MHZ (2 << 0) +#define SD_SCR_CLOCK_MODE_50MHZ (3 << 0) +#define SD_SCR_CLOCK_MODE_BIT (0) +#define SD_SCR_CLOCK_MODE_MASK (0x3 << SD_SCR_CLOCK_MODE_BIT) +#define SD_SCR_CMD_BUSY (1 << 2) +#define SD_SCR_CMD_ERROR (1 << 3) +#define SD_SCR_CARD_BUSY (1 << 4) +#define SD_SCR_CARD_INSERTED (1 << 5) +#define SD_SCR_RX_COUNT_BIT (6) +#define SD_SCR_RX_COUNT_MASK (0x7FF << SD_SCR_RX_COUNT_BIT) +#define SD_SCR_TX_COUNT_BIT (17) +#define SD_SCR_TX_COUNT_MASK (0x7FF << SD_SCR_TX_COUNT_BIT) + +#define SD_CMD_INDEX_BIT (0) +#define SD_CMD_INDEX_MASK (0x3F) +#define SD_CMD_SKIP_RESPONSE (1 << 6) +#define SD_CMD_RESERVED_RESPONSE (1 << 7) +#define SD_CMD_LONG_RESPONSE (1 << 8) +#define SD_CMD_IGNORE_CRC (1 << 9) + +#define SD_DAT_FIFO_FLUSH (1 << 0) +#define SD_DAT_START_WRITE (1 << 1) +#define SD_DAT_START_READ (1 << 2) +#define SD_DAT_STOP (1 << 3) +#define SD_DAT_BLOCKS_BIT (4) +#define SD_DAT_BLOCKS_MASK (0xFF << SD_DAT_BLOCKS_BIT) +#define SD_DAT_BUSY (1 << 12) +#define SD_DAT_ERROR (1 << 13) + +#define DD_SCR_HARD_RESET (1 << 0) +#define DD_SCR_HARD_RESET_CLEAR (1 << 1) +#define DD_SCR_CMD_PENDING (1 << 2) +#define DD_SCR_CMD_READY (1 << 3) +#define DD_SCR_BM_PENDING (1 << 4) +#define DD_SCR_BM_READY (1 << 5) +#define DD_SCR_DISK_INSERTED (1 << 6) +#define DD_SCR_DISK_CHANGED (1 << 7) +#define DD_SCR_BM_START (1 << 8) +#define DD_SCR_BM_START_CLEAR (1 << 9) +#define DD_SCR_BM_STOP (1 << 10) +#define DD_SCR_BM_STOP_CLEAR (1 << 11) +#define DD_SCR_BM_TRANSFER_MODE (1 << 12) +#define DD_SCR_BM_TRANSFER_BLOCKS (1 << 13) +#define DD_SCR_BM_TRANSFER_DATA (1 << 14) +#define DD_SCR_BM_TRANSFER_C2 (1 << 15) +#define DD_SCR_BM_MICRO_ERROR (1 << 16) +#define DD_SCR_BM_ACK (1 << 17) +#define DD_SCR_BM_ACK_CLEAR (1 << 18) +#define DD_SCR_BM_CLEAR (1 << 19) + +#define DD_TRACK_MASK (0x0FFF) +#define DD_HEAD_MASK (0x1000) +#define DD_HEAD_TRACK_MASK (DD_HEAD_MASK | DD_TRACK_MASK) +#define DD_HEAD_TRACK_INDEX_LOCK (1 << 13) + + +uint8_t fpga_id_get (void); +uint32_t fpga_reg_get (fpga_reg_t reg); +void fpga_reg_set (fpga_reg_t reg, uint32_t value); +void fpga_mem_read (uint32_t address, size_t length, uint8_t *buffer); +void fpga_mem_write (uint32_t address, size_t length, uint8_t *buffer); +void fpga_mem_copy (uint32_t src, uint32_t dst, size_t length); +uint8_t fpga_usb_status_get (void); +uint8_t fpga_usb_pop (void); +void fpga_usb_push (uint8_t data); + + +#endif diff --git a/sw/controller/src/gvr.c b/sw/controller/src/gvr.c new file mode 100644 index 0000000..bdc836a --- /dev/null +++ b/sw/controller/src/gvr.c @@ -0,0 +1,33 @@ +#include "button.h" +#include "cfg.h" +#include "dd.h" +#include "flashram.h" +#include "fpga.h" +#include "isv.h" +#include "rtc.h" +#include "sd.h" +#include "usb.h" + + +void gvr_task (void) { + while (fpga_id_get() != FPGA_ID); + + button_init(); + cfg_init(); + dd_init(); + flashram_init(); + isv_init(); + sd_init(); + usb_init(); + + while (1) { + button_process(); + cfg_process(); + dd_process(); + flashram_process(); + isv_process(); + rtc_process(); + sd_process(); + usb_process(); + } +} diff --git a/sw/controller/src/gvr.h b/sw/controller/src/gvr.h new file mode 100644 index 0000000..2a782d1 --- /dev/null +++ b/sw/controller/src/gvr.h @@ -0,0 +1,8 @@ +#ifndef GVR_H__ +#define GVR_H__ + + +void gvr_task (void); + + +#endif diff --git a/sw/controller/src/hw.c b/sw/controller/src/hw.c new file mode 100644 index 0000000..cff7c0e --- /dev/null +++ b/sw/controller/src/hw.c @@ -0,0 +1,604 @@ +#include +#include "hw.h" + + +typedef enum { + GPIO_INPUT = 0b00, + GPIO_OUTPUT = 0b01, + GPIO_ALT = 0b10, + GPIO_ANALOG = 0b11 +} gpio_mode_t; + +typedef enum { + GPIO_PP = 0b0, + GPIO_OD = 0b1 +} gpio_ot_t; + +typedef enum { + GPIO_SPEED_VLOW = 0b00, + GPIO_SPEED_LOW = 0b01, + GPIO_SPEED_HIGH = 0b10, + GPIO_SPEED_VHIGH = 0b11 +} gpio_ospeed_t; + +typedef enum { + GPIO_PULL_NONE = 0b00, + GPIO_PULL_UP = 0b01, + GPIO_PULL_DOWN = 0b10 +} gpio_pupd_t; + +typedef enum { + GPIO_AF_0 = 0x00, + GPIO_AF_1 = 0x01, + GPIO_AF_2 = 0x02, + GPIO_AF_3 = 0x03, + GPIO_AF_4 = 0x04, + GPIO_AF_5 = 0x05, + GPIO_AF_6 = 0x06, + GPIO_AF_7 = 0x07 +} gpio_af_t; + + +typedef struct { + void (*volatile falling)(void); + void (*volatile rising)(void); +} gpio_irq_callback_t; + + +static const GPIO_TypeDef *gpios[] = { GPIOA, GPIOB, 0, 0, 0, 0, 0, 0 }; +static gpio_irq_callback_t gpio_irq_callbacks[16]; +static volatile uint8_t *i2c_data_txptr; +static volatile uint8_t *i2c_data_rxptr; +static volatile uint32_t i2c_next_cr2; +static void (*volatile i2c_callback)(void); +static const TIM_TypeDef *tims[] = { TIM14, TIM16, TIM17, TIM3, TIM1 }; +static void (*volatile tim_callbacks[5])(void); + + +static void hw_gpio_init (gpio_id_t id, gpio_mode_t mode, gpio_ot_t ot, gpio_ospeed_t ospeed, gpio_pupd_t pupd, gpio_af_t af, int value) { + GPIO_TypeDef tmp; + GPIO_TypeDef *gpio = ((GPIO_TypeDef *) (gpios[(id >> 4) & 0x07])); + uint8_t pin = (id & 0x0F); + uint8_t afr = ((pin < 8) ? 0 : 1); + + tmp.MODER = (gpio->MODER & ~(GPIO_MODER_MODE0_Msk << (pin * 2))); + tmp.OTYPER = (gpio->OTYPER & ~(GPIO_OTYPER_OT0_Msk << pin)); + tmp.OSPEEDR = (gpio->OSPEEDR & ~(GPIO_OSPEEDR_OSPEED0_Msk << (pin * 2))); + tmp.PUPDR = (gpio->PUPDR & ~(GPIO_PUPDR_PUPD0_Msk << (pin * 2))); + tmp.AFR[afr] = (gpio->AFR[afr] & ~(GPIO_AFRL_AFSEL0_Msk << ((pin - (afr * 8)) * 4))); + + gpio->MODER |= (GPIO_MODER_MODE0_Msk << (pin * 2)); + gpio->OTYPER = (tmp.OTYPER | (ot << pin)); + gpio->OSPEEDR = (tmp.OSPEEDR | (ospeed << (pin * 2))); + gpio->PUPDR = (tmp.PUPDR | (pupd << (pin * 2))); + gpio->AFR[afr] = (tmp.AFR[afr] | (af << ((pin - (afr * 8)) * 4))); + gpio->BSRR = ((value ? GPIO_BSRR_BS0 : GPIO_BSRR_BR0) << pin); + gpio->MODER = (tmp.MODER | (mode << (pin * 2))); +} + +void hw_gpio_irq_setup (gpio_id_t id, gpio_irq_t irq, void (*callback)(void)) { + uint8_t port = ((id >> 4) & 0x07); + uint8_t pin = (id & 0x0F); + if (irq == GPIO_IRQ_FALLING) { + EXTI->FTSR1 |= (EXTI_FTSR1_FT0 << pin); + gpio_irq_callbacks[pin].falling = callback; + } else { + EXTI->RTSR1 |= (EXTI_RTSR1_RT0 << pin); + gpio_irq_callbacks[pin].rising = callback; + } + EXTI->EXTICR[pin / 4] |= (port << (8 * (pin % 4))); + EXTI->IMR1 |= (EXTI_IMR1_IM0 << pin); +} + +uint32_t hw_gpio_get (gpio_id_t id) { + GPIO_TypeDef *gpio = ((GPIO_TypeDef *) (gpios[(id >> 4) & 0x07])); + uint8_t pin = (id & 0x0F); + return gpio->IDR & (GPIO_IDR_ID0 << pin); +} + +void hw_gpio_set (gpio_id_t id) { + GPIO_TypeDef *gpio = ((GPIO_TypeDef *) (gpios[(id >> 4) & 0x07])); + uint8_t pin = (id & 0x0F); + gpio->BSRR = (GPIO_BSRR_BS0 << pin); +} + +void hw_gpio_reset (gpio_id_t id) { + GPIO_TypeDef *gpio = ((GPIO_TypeDef *) (gpios[(id >> 4) & 0x07])); + uint8_t pin = (id & 0x0F); + gpio->BSRR = (GPIO_BSRR_BR0 << pin); +} + +void hw_uart_write (uint8_t *data, int length) { + for (int i = 0; i < length; i++) { + while (!(USART1->ISR & USART_ISR_TXE_TXFNF)); + USART1->TDR = *data++; + } +} + +void hw_spi_start (void) { + hw_gpio_reset(GPIO_ID_SPI_CS); +} + +void hw_spi_stop (void) { + while (SPI1->SR & SPI_SR_BSY); + hw_gpio_set(GPIO_ID_SPI_CS); +} + +void hw_spi_trx (uint8_t *data, int length, spi_direction_t direction) { + volatile uint8_t dummy __attribute__((unused)); + + DMA1_Channel1->CNDTR = length; + DMA1_Channel2->CNDTR = length; + + if (direction == SPI_TX) { + DMA1_Channel1->CMAR = (uint32_t) (&dummy); + DMA1_Channel1->CCR = DMA_CCR_EN; + + DMA1_Channel2->CMAR = (uint32_t) (data); + DMA1_Channel2->CCR = (DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_EN); + } else { + DMA1_Channel1->CMAR = (uint32_t) (data); + DMA1_Channel1->CCR = (DMA_CCR_MINC | DMA_CCR_EN); + + DMA1_Channel2->CMAR = (uint32_t) (&dummy); + DMA1_Channel2->CCR = (DMA_CCR_DIR | DMA_CCR_EN); + } + + while (DMA1_Channel1->CNDTR || DMA1_Channel2->CNDTR); + + DMA1_Channel1->CCR = 0; + DMA1_Channel2->CCR = 0; +} + +void hw_i2c_read (uint8_t i2c_address, uint8_t address, uint8_t *data, uint8_t length, void (*callback)(void)) { + i2c_data_rxptr = data; + i2c_callback = callback; + I2C1->TXDR = address; + i2c_next_cr2 = ( + I2C_CR2_AUTOEND | + (length << I2C_CR2_NBYTES_Pos) | + I2C_CR2_START | + I2C_CR2_RD_WRN | + (i2c_address << I2C_CR2_SADD_Pos) + ); + I2C1->CR2 = ( + (1 << I2C_CR2_NBYTES_Pos) | + I2C_CR2_START | + (i2c_address << I2C_CR2_SADD_Pos) + ); +} + +void hw_i2c_write (uint8_t i2c_address, uint8_t address, uint8_t *data, uint8_t length, void (*callback)(void)) { + i2c_data_txptr = data; + i2c_callback = callback; + I2C1->TXDR = address; + I2C1->CR2 = ( + I2C_CR2_AUTOEND | + ((length + 1) << I2C_CR2_NBYTES_Pos) | + I2C_CR2_START | + (i2c_address << I2C_CR2_SADD_Pos) + ); +} + +uint32_t hw_i2c_get_error (void) { + return I2C1->ISR & I2C_ISR_NACKF; +} + +void hw_i2c_disable_irq (void) { + NVIC_DisableIRQ(I2C1_IRQn); +} + +void hw_i2c_enable_irq (void) { + NVIC_EnableIRQ(I2C1_IRQn); +} + +void hw_tim_setup (tim_id_t id, uint16_t delay, void (*callback)(void)) { + if (delay == 0) { + if (callback) { + callback(); + } + return; + } + TIM_TypeDef *tim = ((TIM_TypeDef *) (tims[id])); + tim->CR1 = (TIM_CR1_OPM | TIM_CR1_URS); + tim->PSC = (64000 - 1); + tim->ARR = delay; + tim->DIER = TIM_DIER_UIE; + tim->EGR = TIM_EGR_UG; + tim->SR = 0; + tim->CR1 |= TIM_CR1_CEN; + tim_callbacks[id] = callback; +} + +void hw_tim_stop (tim_id_t id) { + TIM_TypeDef *tim = ((TIM_TypeDef *) (tims[id])); + tim->CR1 &= ~(TIM_CR1_CEN); + tim_callbacks[id] = 0; +} + +void hw_tim_disable_irq (tim_id_t id) { + switch (id) { + case TIM_ID_CIC: + NVIC_DisableIRQ(TIM14_IRQn); + break; + case TIM_ID_RTC: + NVIC_DisableIRQ(TIM16_IRQn); + break; + case TIM_ID_SD: + NVIC_DisableIRQ(TIM17_IRQn); + break; + case TIM_ID_DD: + NVIC_DisableIRQ(TIM3_IRQn); + break; + case TIM_ID_LED: + NVIC_DisableIRQ(TIM1_BRK_UP_TRG_COM_IRQn); + break; + default: + break; + } +} + +void hw_tim_enable_irq (tim_id_t id) { + switch (id) { + case TIM_ID_CIC: + NVIC_EnableIRQ(TIM14_IRQn); + break; + case TIM_ID_RTC: + NVIC_EnableIRQ(TIM16_IRQn); + break; + case TIM_ID_SD: + NVIC_EnableIRQ(TIM17_IRQn); + break; + case TIM_ID_DD: + NVIC_EnableIRQ(TIM3_IRQn); + break; + case TIM_ID_LED: + NVIC_EnableIRQ(TIM1_BRK_UP_TRG_COM_IRQn); + break; + default: + break; + } +} + +void hw_delay_ms (uint32_t ms) { + SysTick->VAL = 0; + for (uint32_t i = 0; i < ms; i++) { + while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)); + } +} + +void hw_crc32_reset (void) { + CRC->CR |= CRC_CR_RESET; +} + +uint32_t hw_crc32_calculate (uint8_t *data, uint32_t length) { + for (uint32_t i = 0; i < length; i++) { + *(__IO uint8_t *) (&CRC->DR) = data[i]; + } + return (CRC->DR ^ 0xFFFFFFFF); +} + +uint32_t hw_flash_size (void) { + return FLASH_SIZE; +} + +static void hw_flash_unlock (void) { + while (FLASH->SR & FLASH_SR_BSY1); + if (FLASH->CR & FLASH_CR_LOCK) { + FLASH->KEYR = 0x45670123; + __ISB(); + FLASH->KEYR = 0xCDEF89AB; + } +} + +void hw_flash_erase (void) { + hw_flash_unlock(); + FLASH->CR |= (FLASH_CR_STRT | FLASH_CR_MER1); + while (FLASH->SR & FLASH_SR_BSY1); +} + +void hw_flash_program (uint32_t offset, hw_flash_t value) { + hw_flash_unlock(); + FLASH->CR |= FLASH_CR_PG; + *(__IO uint32_t *) (FLASH_BASE + offset) = ((value) & 0xFFFFFFFF); + __ISB(); + *(__IO uint32_t *) (FLASH_BASE + offset + 4) = ((value >> 32) & 0xFFFFFFFF); + while (FLASH->SR & FLASH_SR_BSY1); + FLASH->CR &= ~(FLASH_CR_PG); +} + +hw_flash_t hw_flash_read (uint32_t offset) { + return *(uint64_t *) (FLASH_BASE + offset); +} + +void hw_loader_reset (loader_parameters_t *parameters) { + RCC->APBENR1 |= RCC_APBENR1_PWREN | RCC_APBENR1_RTCAPBEN; + PWR->CR1 |= PWR_CR1_DBP; + TAMP->BKP0R = parameters->magic; + TAMP->BKP1R = parameters->flags; + TAMP->BKP2R = parameters->mcu_address; + TAMP->BKP3R = parameters->fpga_address; + TAMP->BKP4R = parameters->bootloader_address; + PWR->CR1 &= ~(PWR_CR1_DBP); + RCC->APBENR1 &= ~(RCC_APBENR1_PWREN | RCC_APBENR1_RTCAPBEN); + NVIC_SystemReset(); +} + +void hw_loader_get_parameters (loader_parameters_t *parameters) { + RCC->APBENR1 |= RCC_APBENR1_PWREN | RCC_APBENR1_RTCAPBEN; + parameters->magic = TAMP->BKP0R; + parameters->flags = TAMP->BKP1R; + parameters->mcu_address = TAMP->BKP2R; + parameters->fpga_address = TAMP->BKP3R; + parameters->bootloader_address = TAMP->BKP4R; + PWR->CR1 |= PWR_CR1_DBP; + TAMP->BKP0R = 0; + TAMP->BKP1R = 0; + TAMP->BKP2R = 0; + TAMP->BKP3R = 0; + TAMP->BKP4R = 0; + PWR->CR1 &= ~(PWR_CR1_DBP); + RCC->APBENR1 &= ~(RCC_APBENR1_PWREN | RCC_APBENR1_RTCAPBEN); +} + +static void hw_init_mcu (void) { + FLASH->ACR |= (FLASH_ACR_PRFTEN | (2 << FLASH_ACR_LATENCY_Pos)); + while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (2 << FLASH_ACR_LATENCY_Pos)); + + RCC->PLLCFGR = ( + ((2 - 1) << RCC_PLLCFGR_PLLR_Pos) + | RCC_PLLCFGR_PLLREN + | (16 << RCC_PLLCFGR_PLLN_Pos) + | ((2 - 1) << RCC_PLLCFGR_PLLM_Pos) + | RCC_PLLCFGR_PLLSRC_HSI + ); + + RCC->CR |= RCC_CR_PLLON; + while ((RCC->CR & RCC_CR_PLLRDY_Msk) != RCC_CR_PLLRDY); + + RCC->CFGR = RCC_CFGR_SW_1; + while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_1); + + RCC->IOPENR |= RCC_IOPENR_GPIOAEN | RCC_IOPENR_GPIOBEN; + + SysTick->LOAD = (((64000000 / 1000)) - 1); + SysTick->VAL = 0; + SysTick->CTRL = (SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk); + + hw_gpio_init(GPIO_ID_LED, GPIO_OUTPUT, GPIO_PP, GPIO_SPEED_VLOW, GPIO_PULL_NONE, GPIO_AF_0, 0); +} + +static void hw_init_spi (void) { + RCC->AHBENR |= RCC_AHBENR_DMA1EN; + RCC->APBENR2 |= RCC_APBENR2_SPI1EN; + + DMAMUX1_Channel0->CCR = (16 << DMAMUX_CxCR_DMAREQ_ID_Pos); + DMAMUX1_Channel1->CCR = (17 << DMAMUX_CxCR_DMAREQ_ID_Pos); + + DMA1_Channel1->CPAR = (uint32_t) (&SPI1->DR); + DMA1_Channel2->CPAR = (uint32_t) (&SPI1->DR); + + SPI1->CR2 = ( + SPI_CR2_FRXTH | + (8 - 1) << SPI_CR2_DS_Pos | + SPI_CR2_TXDMAEN | + SPI_CR2_RXDMAEN + ); + SPI1->CR1 = ( + SPI_CR1_SSM | + SPI_CR1_SSI | + SPI_CR1_BR_1 | + SPI_CR1_SPE | + SPI_CR1_MSTR | + SPI_CR1_CPHA + ); + + hw_gpio_init(GPIO_ID_SPI_CS, GPIO_OUTPUT, GPIO_PP, GPIO_SPEED_HIGH, GPIO_PULL_NONE, GPIO_AF_0, 1); + hw_gpio_init(GPIO_ID_SPI_CLK, GPIO_ALT, GPIO_PP, GPIO_SPEED_HIGH, GPIO_PULL_NONE, GPIO_AF_0, 0); + hw_gpio_init(GPIO_ID_SPI_MISO, GPIO_ALT, GPIO_PP, GPIO_SPEED_HIGH, GPIO_PULL_DOWN, GPIO_AF_0, 0); + hw_gpio_init(GPIO_ID_SPI_MOSI, GPIO_ALT, GPIO_PP, GPIO_SPEED_HIGH, GPIO_PULL_NONE, GPIO_AF_0, 0); + hw_gpio_init(GPIO_ID_FPGA_INT, GPIO_INPUT, GPIO_PP, GPIO_SPEED_VLOW, GPIO_PULL_UP, GPIO_AF_0, 0); +} + +static void hw_init_i2c (void) { + RCC->APBENR1 |= RCC_APBENR1_I2C1EN; + + I2C1->TIMINGR = 0x10B17DB5UL; + I2C1->CR1 |= (I2C_CR1_TCIE | I2C_CR1_STOPIE | I2C_CR1_RXIE | I2C_CR1_TXIE | I2C_CR1_PE); + + hw_gpio_init(GPIO_ID_I2C_SCL, GPIO_ALT, GPIO_OD, GPIO_SPEED_VLOW, GPIO_PULL_NONE, GPIO_AF_6, 0); + hw_gpio_init(GPIO_ID_I2C_SDA, GPIO_ALT, GPIO_OD, GPIO_SPEED_VLOW, GPIO_PULL_NONE, GPIO_AF_6, 0); + hw_gpio_init(GPIO_ID_RTC_MFP, GPIO_INPUT, GPIO_PP, GPIO_SPEED_VLOW, GPIO_PULL_UP, GPIO_AF_0, 0); +} + +static void hw_init_uart (void) { + RCC->APBENR2 |= (RCC_APBENR2_USART1EN | RCC_APBENR2_SYSCFGEN); + + SYSCFG->CFGR1 |= (SYSCFG_CFGR1_PA12_RMP | SYSCFG_CFGR1_PA11_RMP); + + USART1->BRR = (64000000UL) / 1000000; + USART1->CR1 = USART_CR1_FIFOEN | USART_CR1_TE | USART_CR1_UE; + + hw_gpio_init(GPIO_ID_UART_TX, GPIO_ALT, GPIO_PP, GPIO_SPEED_LOW, GPIO_PULL_NONE, GPIO_AF_1, 0); + hw_gpio_init(GPIO_ID_UART_RX, GPIO_ALT, GPIO_PP, GPIO_SPEED_LOW, GPIO_PULL_NONE, GPIO_AF_1, 0); +} + +static void hw_init_tim (void) { + RCC->APBENR1 |= ( + RCC_APBENR1_DBGEN | + RCC_APBENR1_TIM3EN + ); + RCC->APBENR2 |= ( + RCC_APBENR2_TIM17EN | + RCC_APBENR2_TIM16EN | + RCC_APBENR2_TIM14EN | + RCC_APBENR2_USART1EN | + RCC_APBENR2_TIM1EN + ); + + DBG->APBFZ1 |= DBG_APB_FZ1_DBG_TIM3_STOP; + DBG->APBFZ2 |= ( + DBG_APB_FZ2_DBG_TIM17_STOP | + DBG_APB_FZ2_DBG_TIM16_STOP | + DBG_APB_FZ2_DBG_TIM14_STOP | + DBG_APB_FZ2_DBG_TIM1_STOP + ); +} + +static void hw_init_misc (void) { + RCC->AHBENR |= RCC_AHBENR_CRCEN; + + CRC->CR = (CRC_CR_REV_OUT | CRC_CR_REV_IN_0); + + hw_gpio_init(GPIO_ID_N64_RESET, GPIO_INPUT, GPIO_PP, GPIO_SPEED_VLOW, GPIO_PULL_DOWN, GPIO_AF_0, 0); + hw_gpio_init(GPIO_ID_N64_CIC_CLK, GPIO_INPUT, GPIO_PP, GPIO_SPEED_VLOW, GPIO_PULL_DOWN, GPIO_AF_0, 0); + hw_gpio_init(GPIO_ID_N64_CIC_DQ, GPIO_OUTPUT, GPIO_OD, GPIO_SPEED_VLOW, GPIO_PULL_UP, GPIO_AF_0, 1); +} + +void hw_init (void) { + hw_init_mcu(); + hw_init_spi(); + hw_init_i2c(); + hw_init_uart(); + hw_init_tim(); + hw_init_misc(); + + NVIC_SetPriority(EXTI0_1_IRQn, 0); + NVIC_SetPriority(EXTI2_3_IRQn, 1); + NVIC_SetPriority(EXTI4_15_IRQn, 2); + NVIC_SetPriority(I2C1_IRQn, 1); + NVIC_SetPriority(TIM14_IRQn, 0); + NVIC_SetPriority(TIM16_IRQn, 1); + NVIC_SetPriority(TIM17_IRQn, 2); + NVIC_SetPriority(TIM3_IRQn, 2); + NVIC_SetPriority(TIM1_BRK_UP_TRG_COM_IRQn, 1); + + NVIC_EnableIRQ(EXTI0_1_IRQn); + NVIC_EnableIRQ(EXTI2_3_IRQn); + NVIC_EnableIRQ(EXTI4_15_IRQn); + NVIC_EnableIRQ(I2C1_IRQn); + NVIC_EnableIRQ(TIM14_IRQn); + NVIC_EnableIRQ(TIM16_IRQn); + NVIC_EnableIRQ(TIM17_IRQn); + NVIC_EnableIRQ(TIM3_IRQn); + NVIC_EnableIRQ(TIM1_BRK_UP_TRG_COM_IRQn); +} + +void hw_loader_init (void) { + hw_init_mcu(); + hw_init_spi(); +} + + +void EXTI0_1_IRQHandler (void) { + for (int i = 0; i <= 1; i++) { + if (EXTI->FPR1 & (EXTI_FPR1_FPIF0 << i)) { + EXTI->FPR1 = (EXTI_FPR1_FPIF0 << i); + if (gpio_irq_callbacks[i].falling) { + gpio_irq_callbacks[i].falling(); + } + } + if (EXTI->RPR1 & (EXTI_RPR1_RPIF0 << i)) { + EXTI->RPR1 = (EXTI_RPR1_RPIF0 << i); + if (gpio_irq_callbacks[i].rising) { + gpio_irq_callbacks[i].rising(); + } + } + } +} + +void EXTI2_3_IRQHandler (void) { + for (int i = 2; i <= 3; i++) { + if (EXTI->FPR1 & (EXTI_FPR1_FPIF0 << i)) { + EXTI->FPR1 = (EXTI_FPR1_FPIF0 << i); + if (gpio_irq_callbacks[i].falling) { + gpio_irq_callbacks[i].falling(); + } + } + if (EXTI->RPR1 & (EXTI_RPR1_RPIF0 << i)) { + EXTI->RPR1 = (EXTI_RPR1_RPIF0 << i); + if (gpio_irq_callbacks[i].rising) { + gpio_irq_callbacks[i].rising(); + } + } + } +} + +void EXTI4_15_IRQHandler (void) { + for (int i = 4; i <= 15; i++) { + if (EXTI->FPR1 & (EXTI_FPR1_FPIF0 << i)) { + EXTI->FPR1 = (EXTI_FPR1_FPIF0 << i); + if (gpio_irq_callbacks[i].falling) { + gpio_irq_callbacks[i].falling(); + } + } + if (EXTI->RPR1 & (EXTI_RPR1_RPIF0 << i)) { + EXTI->RPR1 = (EXTI_RPR1_RPIF0 << i); + if (gpio_irq_callbacks[i].rising) { + gpio_irq_callbacks[i].rising(); + } + } + } +} + +void I2C1_IRQHandler (void) { + if (I2C1->ISR & I2C_ISR_TXIS) { + I2C1->TXDR = *i2c_data_txptr++; + } + + if (I2C1->ISR & I2C_ISR_RXNE) { + *i2c_data_rxptr++ = I2C1->RXDR; + } + + if (I2C1->ISR & I2C_ISR_TC) { + I2C1->CR2 = i2c_next_cr2; + } + + if (I2C1->ISR & I2C_ISR_STOPF) { + I2C1->ICR = I2C_ICR_STOPCF; + if (i2c_callback) { + i2c_callback(); + i2c_callback = 0; + } + } +} + +void TIM14_IRQHandler (void) { + TIM14->SR &= ~(TIM_SR_UIF); + if (tim_callbacks[0]) { + tim_callbacks[0](); + tim_callbacks[0] = 0; + } +} + +void TIM16_IRQHandler (void) { + TIM16->SR &= ~(TIM_SR_UIF); + if (tim_callbacks[1]) { + tim_callbacks[1](); + tim_callbacks[1] = 0; + } +} + +void TIM17_IRQHandler (void) { + TIM17->SR &= ~(TIM_SR_UIF); + if (tim_callbacks[2]) { + tim_callbacks[2](); + tim_callbacks[2] = 0; + } +} + +void TIM3_IRQHandler (void) { + TIM3->SR &= ~(TIM_SR_UIF); + if (tim_callbacks[3]) { + tim_callbacks[3](); + tim_callbacks[3] = 0; + } +} + +void TIM1_BRK_UP_TRG_COM_IRQHandler (void) { + TIM1->SR &= ~(TIM_SR_UIF); + if (tim_callbacks[4]) { + tim_callbacks[4](); + tim_callbacks[4] = 0; + } +} diff --git a/sw/controller/src/hw.h b/sw/controller/src/hw.h new file mode 100644 index 0000000..07658f1 --- /dev/null +++ b/sw/controller/src/hw.h @@ -0,0 +1,92 @@ +#ifndef HW_H__ +#define HW_H__ + + +#include + + +#define GPIO_PORT_PIN(p, n) ((((p) & 0x07) << 4) | ((n) & 0x0F)) + +typedef enum { + GPIO_ID_N64_RESET = GPIO_PORT_PIN(0, 0), + GPIO_ID_N64_CIC_CLK = GPIO_PORT_PIN(0, 1), + GPIO_ID_N64_CIC_DQ = GPIO_PORT_PIN(0, 2), + GPIO_ID_LED = GPIO_PORT_PIN(0, 3), + GPIO_ID_SPI_CS = GPIO_PORT_PIN(0, 4), + GPIO_ID_SPI_CLK = GPIO_PORT_PIN(0, 5), + GPIO_ID_SPI_MISO = GPIO_PORT_PIN(0, 6), + GPIO_ID_SPI_MOSI = GPIO_PORT_PIN(0, 7), + GPIO_ID_UART_TX = GPIO_PORT_PIN(0, 9), + GPIO_ID_UART_RX = GPIO_PORT_PIN(0, 10), + GPIO_ID_FPGA_INT = GPIO_PORT_PIN(1, 2), + GPIO_ID_I2C_SCL = GPIO_PORT_PIN(1, 6), + GPIO_ID_I2C_SDA = GPIO_PORT_PIN(1, 7), + GPIO_ID_RTC_MFP = GPIO_PORT_PIN(1, 9), +} gpio_id_t; + +typedef enum { + GPIO_IRQ_FALLING = 0b01, + GPIO_IRQ_RISING = 0b10, +} gpio_irq_t; + +typedef enum { + TIM_ID_CIC = 0, + TIM_ID_RTC = 1, + TIM_ID_SD = 2, + TIM_ID_DD = 3, + TIM_ID_LED = 4, +} tim_id_t; + +typedef enum { + SPI_TX, + SPI_RX, +} spi_direction_t; + +typedef uint64_t hw_flash_t; + +typedef enum { + LOADER_FLAGS_UPDATE_MCU = (1 << 0), + LOADER_FLAGS_UPDATE_FPGA = (1 << 1), + LOADER_FLAGS_UPDATE_BOOTLOADER = (1 << 2), +} loader_parameters_flags_t; + +typedef struct { + uint32_t magic; + loader_parameters_flags_t flags; + uint32_t mcu_address; + uint32_t fpga_address; + uint32_t bootloader_address; +} loader_parameters_t; + + +void hw_gpio_irq_setup (gpio_id_t id, gpio_irq_t irq, void (*callback)(void)); +uint32_t hw_gpio_get (gpio_id_t id); +void hw_gpio_set (gpio_id_t id); +void hw_gpio_reset (gpio_id_t id); +void hw_uart_write (uint8_t *data, int length); +void hw_spi_start (void); +void hw_spi_stop (void); +void hw_spi_trx (uint8_t *data, int length, spi_direction_t direction); +void hw_i2c_read (uint8_t i2c_address, uint8_t address, uint8_t *data, uint8_t length, void (*callback)(void)); +void hw_i2c_write (uint8_t i2c_address, uint8_t address, uint8_t *data, uint8_t length, void (*callback)(void)); +uint32_t hw_i2c_get_error (void); +void hw_i2c_disable_irq (void); +void hw_i2c_enable_irq (void); +void hw_tim_setup (tim_id_t id, uint16_t delay, void (*callback)(void)); +void hw_tim_stop (tim_id_t id); +void hw_tim_disable_irq (tim_id_t id); +void hw_tim_enable_irq (tim_id_t id); +void hw_delay_ms (uint32_t ms); +void hw_crc32_reset (void); +uint32_t hw_crc32_calculate (uint8_t *data, uint32_t length); +uint32_t hw_flash_size (void); +void hw_flash_erase (void); +void hw_flash_program (uint32_t offset, hw_flash_t value); +hw_flash_t hw_flash_read (uint32_t offset); +void hw_loader_reset (loader_parameters_t *parameters); +void hw_loader_get_parameters (loader_parameters_t *parameters); +void hw_init (void); +void hw_loader_init (void); + + +#endif diff --git a/sw/controller/src/isv.c b/sw/controller/src/isv.c new file mode 100644 index 0000000..2f20f6a --- /dev/null +++ b/sw/controller/src/isv.c @@ -0,0 +1,106 @@ +#include +#include "fpga.h" +#include "isv.h" +#include "usb.h" + + +#define ISV_TOKEN (0x49533634) + +#define ISV_SETUP_TOKEN_ADDRESS (0x00000100) +#define ISV_SETUP_OFFSET_ADDRESS (0x00000104) +#define ISV_SETUP_READY_ADDRESS (0x0000010C) + +#define ISV_TOKEN_OFFSET (0x00000000) +#define ISV_READ_POINTER_OFFSET (0x00000004) +#define ISV_WRITE_POINTER_OFFSET (0x00000014) +#define ISV_BUFFER_OFFSET (0x00000020) + +#define ISV_BUFFER_SIZE ((64 * 1024) - ISV_BUFFER_OFFSET) + + +struct process { + bool ready; + uint32_t address; + uint32_t next_read_pointer; +}; + + +static struct process p; + + +static void isv_set_value (uint32_t address, uint32_t data) { + data = SWAP32(data); + fpga_mem_write(address, 4, (uint8_t *) (&data)); +} + +static uint32_t isv_get_value (uint32_t address) { + uint32_t data; + fpga_mem_read(address, 4, (uint8_t *) (&data)); + return SWAP32(data); +} + +static void isv_update_read_pointer (void) { + p.ready = true; + isv_set_value(p.address + ISV_READ_POINTER_OFFSET, p.next_read_pointer); +} + + +bool isv_set_address (uint32_t address) { + if ((address > 0x03FF0000) || (address % 4)) { + return true; + } + p.address = address; + return false; +} + +uint32_t isv_get_address (void) { + return p.address; +} + +void isv_init (void) { + p.address = 0; + p.ready = true; +} + +void isv_process (void) { + if ((p.address != 0) && p.ready) { + if (isv_get_value(ISV_SETUP_TOKEN_ADDRESS) == ISV_TOKEN) { + isv_set_value(ISV_SETUP_TOKEN_ADDRESS, 0); + isv_set_value(ISV_SETUP_OFFSET_ADDRESS, (p.address | 0x10000000)); + isv_set_value(ISV_SETUP_READY_ADDRESS, ISV_TOKEN); + return; + } + + if (isv_get_value(p.address + ISV_TOKEN_OFFSET) != ISV_TOKEN) { + return; + } + + uint32_t read_pointer = isv_get_value(p.address + ISV_READ_POINTER_OFFSET); + if (read_pointer >= ISV_BUFFER_SIZE) { + return; + } + + uint32_t write_pointer = isv_get_value(p.address + ISV_WRITE_POINTER_OFFSET); + if (write_pointer >= ISV_BUFFER_SIZE) { + return; + } + + if (read_pointer == write_pointer) { + return; + } + + bool wrap = write_pointer < read_pointer; + uint32_t length = (wrap ? ISV_BUFFER_SIZE : write_pointer) - read_pointer; + uint32_t offset = p.address + ISV_BUFFER_OFFSET + read_pointer; + + usb_tx_info_t packet_info; + usb_create_packet(&packet_info, PACKET_CMD_ISV_OUTPUT); + packet_info.dma_length = length; + packet_info.dma_address = offset; + packet_info.done_callback = isv_update_read_pointer; + if (usb_enqueue_packet(&packet_info)) { + p.ready = false; + p.next_read_pointer = wrap ? 0 : write_pointer; + } + } +} diff --git a/sw/controller/src/isv.h b/sw/controller/src/isv.h new file mode 100644 index 0000000..04ae2de --- /dev/null +++ b/sw/controller/src/isv.h @@ -0,0 +1,15 @@ +#ifndef ISV_H__ +#define ISV_H__ + + +#include +#include + + +bool isv_set_address (uint32_t address); +uint32_t isv_get_address (void); +void isv_init (void); +void isv_process (void); + + +#endif diff --git a/sw/controller/src/lcmxo2.c b/sw/controller/src/lcmxo2.c new file mode 100644 index 0000000..4990444 --- /dev/null +++ b/sw/controller/src/lcmxo2.c @@ -0,0 +1,253 @@ +#include +#include "fpga.h" +#include "vendor.h" + + +#define VENDOR_SCR_START (1 << 0) +#define VENDOR_SCR_BUSY (1 << 0) +#define VENDOR_SCR_WRITE (1 << 1) +#define VENDOR_SCR_LENGTH_BIT (2) +#define VENDOR_SCR_DELAY (1 << 4) +#define VENDOR_SCR_ADDRESS_BIT (8) + +#define LCMXO2_CFGCR (0x70) +#define LCMXO2_CFGTXDR (0x71) +#define LCMXO2_CFGRXDR (0x73) + +#define CFGCR_RSTE (1 << 6) +#define CFGCR_WBCE (1 << 7) + +#define ISC_ERASE (0x0E) +#define ISC_DISABLE (0x26) +#define LSC_READ_STATUS (0x3C) +#define LSC_INIT_ADDRESS (0x46) +#define ISC_PROGRAM_DONE (0x5E) +#define LSC_PROG_INCR_NV (0x70) +#define LSC_READ_INCR_NV (0x73) +#define ISC_ENABLE_X (0x74) +#define LSC_REFRESH (0x79) +#define ISC_NOOP (0xFF) + +#define ISC_ERASE_CFG (1 << 18) +#define ISC_ERASE_UFM (1 << 19) + +#define LSC_STATUS_1_BUSY (1 << 4) +#define LSC_STATUS_1_FAIL (1 << 5) + +#define FLASH_PAGE_SIZE (16) +#define FLASH_NUM_PAGES (11260) + + +typedef enum { + CMD_NORMAL, + CMD_DELAYED, + CMD_TWO_OP, +} cmd_type_t; + + +static void lcmxo2_reg_set (uint8_t reg, uint8_t value) { + fpga_reg_set(REG_VENDOR_DATA, value << 24); + fpga_reg_set(REG_VENDOR_SCR, + (reg << VENDOR_SCR_ADDRESS_BIT) | + (0 << VENDOR_SCR_LENGTH_BIT) | + VENDOR_SCR_WRITE | + VENDOR_SCR_START + ); + while (fpga_reg_get(REG_VENDOR_SCR) & VENDOR_SCR_BUSY); +} + +static void lcmxo2_reset_bus (void) { + lcmxo2_reg_set(LCMXO2_CFGCR, CFGCR_RSTE); + lcmxo2_reg_set(LCMXO2_CFGCR, 0); +} + +static void lcmxo2_execute_cmd (uint8_t cmd, uint32_t arg, cmd_type_t type) { + lcmxo2_reg_set(LCMXO2_CFGCR, 0); + uint32_t data = (cmd << 24) | (arg & 0x00FFFFFF); + lcmxo2_reg_set(LCMXO2_CFGCR, CFGCR_WBCE); + fpga_reg_set(REG_VENDOR_DATA, data); + fpga_reg_set(REG_VENDOR_SCR, + (LCMXO2_CFGTXDR << VENDOR_SCR_ADDRESS_BIT) | + (type == CMD_DELAYED ? VENDOR_SCR_DELAY : 0) | + ((type == CMD_TWO_OP ? 2 : 3) << VENDOR_SCR_LENGTH_BIT) | + VENDOR_SCR_WRITE | + VENDOR_SCR_START + ); + while (fpga_reg_get(REG_VENDOR_SCR) & VENDOR_SCR_BUSY); +} + +static void lcmxo2_cleanup (void) { + lcmxo2_reg_set(LCMXO2_CFGCR, 0); +} + +static void lcmxo2_read_data (uint8_t *buffer, uint32_t length) { + while (length > 0) { + uint32_t block_size = (length > 4) ? 4 : length; + fpga_reg_set(REG_VENDOR_SCR, + (LCMXO2_CFGRXDR << VENDOR_SCR_ADDRESS_BIT) | + ((block_size - 1) << VENDOR_SCR_LENGTH_BIT) | + VENDOR_SCR_START + ); + while (fpga_reg_get(REG_VENDOR_SCR) & VENDOR_SCR_BUSY); + uint32_t data = fpga_reg_get(REG_VENDOR_DATA); + data <<= ((4 - block_size) * 8); + for (int i = 0; i < block_size; i++) { + *buffer++ = ((data >> 24) & 0xFF); + data <<= 8; + length -= 1; + } + } +} + +static void lcmxo2_write_data (uint8_t *buffer, uint32_t length) { + while (length > 0) { + uint32_t block_size = (length > 4) ? 4 : length; + uint32_t data = 0; + for (int i = 0; i < block_size; i++) { + data = ((data << 8) | *buffer++); + length -= 1; + } + data <<= ((4 - block_size) * 8); + fpga_reg_set(REG_VENDOR_DATA, data); + fpga_reg_set(REG_VENDOR_SCR, + (LCMXO2_CFGTXDR << VENDOR_SCR_ADDRESS_BIT) | + ((block_size - 1) << VENDOR_SCR_LENGTH_BIT) | + VENDOR_SCR_WRITE | + VENDOR_SCR_START + ); + while (fpga_reg_get(REG_VENDOR_SCR) & VENDOR_SCR_BUSY); + } +} + +static bool lcmxo2_wait_busy (void) { + uint8_t status[4]; + do { + lcmxo2_execute_cmd(LSC_READ_STATUS, 0, CMD_NORMAL); + lcmxo2_read_data(status, 4); + } while(status[2] & LSC_STATUS_1_BUSY); + return status[2] & LSC_STATUS_1_FAIL; +} + +static bool lcmxo2_enable_flash (void) { + lcmxo2_execute_cmd(ISC_ENABLE_X, 0x080000, CMD_NORMAL); + return lcmxo2_wait_busy(); +} + +static void lcmxo2_disable_flash (void) { + lcmxo2_wait_busy(); + lcmxo2_execute_cmd(ISC_DISABLE, 0, CMD_TWO_OP); + lcmxo2_execute_cmd(ISC_NOOP, 0xFFFFFF, CMD_NORMAL); +} + +static bool lcmxo2_erase_flash (void) { + lcmxo2_execute_cmd(ISC_ERASE, ISC_ERASE_UFM | ISC_ERASE_CFG, CMD_NORMAL); + return lcmxo2_wait_busy(); +} + +static void lcmxo2_reset_flash_address (void) { + lcmxo2_execute_cmd(LSC_INIT_ADDRESS, 0, CMD_NORMAL); +} + +static bool lcmxo2_write_flash_page (uint8_t *buffer) { + lcmxo2_execute_cmd(LSC_PROG_INCR_NV, 1, CMD_NORMAL); + lcmxo2_write_data(buffer, FLASH_PAGE_SIZE); + return lcmxo2_wait_busy(); +} + +static void lcmxo2_read_flash_page (uint8_t *buffer) { + lcmxo2_execute_cmd(LSC_READ_INCR_NV, 1, CMD_DELAYED); + lcmxo2_read_data(buffer, FLASH_PAGE_SIZE); +} + +static void lcmxo2_program_done (void) { + lcmxo2_execute_cmd(ISC_PROGRAM_DONE, 0, CMD_NORMAL); + lcmxo2_wait_busy(); +} + +static void lcmxo2_refresh (void) { + lcmxo2_execute_cmd(LSC_REFRESH, 0, CMD_TWO_OP); +} + +static vendor_error_t lcmxo2_fail (vendor_error_t error) { + lcmxo2_disable_flash(); + lcmxo2_cleanup(); + return error; +} + +uint32_t vendor_flash_size (void) { + return (FLASH_PAGE_SIZE * FLASH_NUM_PAGES); +} + +vendor_error_t vendor_backup (uint32_t address, uint32_t *length) { + uint8_t buffer[FLASH_PAGE_SIZE]; + + *length = 0; + + lcmxo2_reset_bus(); + if (lcmxo2_enable_flash()) { + return lcmxo2_fail(VENDOR_ERROR_INIT); + } + lcmxo2_reset_flash_address(); + for (int i = 0; i < (FLASH_PAGE_SIZE * FLASH_NUM_PAGES); i += FLASH_PAGE_SIZE) { + lcmxo2_read_flash_page(buffer); + fpga_mem_write(address + i, FLASH_PAGE_SIZE, buffer); + *length += FLASH_PAGE_SIZE; + } + lcmxo2_disable_flash(); + lcmxo2_cleanup(); + + return VENDOR_OK; +} + +vendor_error_t vendor_update (uint32_t address, uint32_t length) { + uint8_t buffer[FLASH_PAGE_SIZE]; + uint8_t verify_buffer[FLASH_PAGE_SIZE]; + + if (length == 0) { + return VENDOR_ERROR_ARGS; + } + if ((length % FLASH_PAGE_SIZE) != 0) { + return VENDOR_ERROR_ARGS; + } + if (length > (FLASH_PAGE_SIZE * FLASH_NUM_PAGES)) { + return VENDOR_ERROR_ARGS; + } + + lcmxo2_reset_bus(); + if (lcmxo2_enable_flash()) { + return lcmxo2_fail(VENDOR_ERROR_INIT); + } + if (lcmxo2_erase_flash()) { + return lcmxo2_fail(VENDOR_ERROR_ERASE); + } + lcmxo2_reset_flash_address(); + for (int i = 0; i < length; i += FLASH_PAGE_SIZE) { + fpga_mem_read(address + i, FLASH_PAGE_SIZE, buffer); + if (lcmxo2_write_flash_page(buffer)) { + return lcmxo2_fail(VENDOR_ERROR_PROGRAM); + } + } + lcmxo2_program_done(); + lcmxo2_reset_flash_address(); + for (int i = 0; i < length; i += FLASH_PAGE_SIZE) { + lcmxo2_read_flash_page(buffer); + fpga_mem_read(address + i, FLASH_PAGE_SIZE, verify_buffer); + for (int x = 0; x < FLASH_PAGE_SIZE; x++) { + if (buffer[x] != verify_buffer[x]) { + return lcmxo2_fail(VENDOR_ERROR_VERIFY); + } + } + } + lcmxo2_disable_flash(); + lcmxo2_cleanup(); + + return VENDOR_OK; +} + +vendor_error_t vendor_reconfigure (void) { + lcmxo2_reset_bus(); + lcmxo2_refresh(); + lcmxo2_cleanup(); + + return VENDOR_OK; +} diff --git a/sw/controller/src/led.c b/sw/controller/src/led.c new file mode 100644 index 0000000..73178d3 --- /dev/null +++ b/sw/controller/src/led.c @@ -0,0 +1,129 @@ +#include +#include "hw.h" +#include "led.h" +#include "task.h" + + +#define LED_MS_PER_TICK (10) +#define LED_ERROR_TICKS_PERIOD (50) +#define LED_ERROR_TICKS_ON (25) +#define LED_ACT_TICKS_PERIOD (15) +#define LED_ACT_TICKS_ON (6) + + +static bool error_mode = false; +static uint32_t error_timer = 0; +static volatile bool cic_error = false; +static volatile bool rtc_error = false; + +static uint32_t act_timer = 0; +static uint32_t current_act_counter = 0; +static volatile uint32_t next_act_counter = 0; + + +static void led_task_resume (void) { + task_set_ready(TASK_ID_LED); +} + +static void led_update_error_mode (void) { + if (error_mode) { + if (!(cic_error || rtc_error)) { + hw_gpio_reset(GPIO_ID_LED); + error_mode = false; + act_timer = 0; + } + } else { + if (cic_error || rtc_error) { + hw_gpio_reset(GPIO_ID_LED); + error_mode = true; + error_timer = 0; + } + } +} + +static void led_process_errors (void) { + if (error_timer == 0) { + error_timer = LED_ERROR_TICKS_PERIOD; + if (cic_error) { + error_timer *= 1; + } else if (rtc_error) { + error_timer *= 2; + } + error_timer += LED_ERROR_TICKS_PERIOD; + } + + if (error_timer > 0) { + error_timer -= 1; + if (error_timer >= LED_ERROR_TICKS_PERIOD) { + uint32_t error_cycle = (error_timer % LED_ERROR_TICKS_PERIOD); + if (error_cycle == LED_ERROR_TICKS_ON) { + hw_gpio_set(GPIO_ID_LED); + } + if (error_cycle == 0) { + hw_gpio_reset(GPIO_ID_LED); + } + } + } +} + +static void led_process_act (void) { + if (act_timer == 0) { + if (current_act_counter != next_act_counter) { + current_act_counter = next_act_counter; + act_timer = LED_ACT_TICKS_PERIOD; + } + } + + if (act_timer > 0) { + act_timer -= 1; + if (act_timer == LED_ACT_TICKS_ON) { + hw_gpio_set(GPIO_ID_LED); + } + if (act_timer == 0) { + hw_gpio_reset(GPIO_ID_LED); + } + } +} + + +void led_blink_error (led_error_t error) { + switch (error) { + case LED_ERROR_CIC: + cic_error = true; + break; + case LED_ERROR_RTC: + rtc_error = true; + break; + } +} + +void led_clear_error (led_error_t error) { + switch (error) { + case LED_ERROR_CIC: + cic_error = false; + break; + case LED_ERROR_RTC: + rtc_error = false; + break; + } +} + +void led_blink_act (void) { + next_act_counter += 1; +} + +void led_task (void) { + while (1) { + hw_tim_setup(TIM_ID_LED, LED_MS_PER_TICK, led_task_resume); + + led_update_error_mode(); + + if (error_mode) { + led_process_errors(); + } else { + led_process_act(); + } + + task_yield(); + } +} diff --git a/sw/controller/src/led.h b/sw/controller/src/led.h new file mode 100644 index 0000000..1ae724d --- /dev/null +++ b/sw/controller/src/led.h @@ -0,0 +1,17 @@ +#ifndef LED_H__ +#define LED_H__ + + +typedef enum { + LED_ERROR_CIC, + LED_ERROR_RTC, +} led_error_t; + + +void led_blink_error (led_error_t error); +void led_clear_error (led_error_t error); +void led_blink_act (void); +void led_task (void); + + +#endif diff --git a/sw/controller/src/loader.S b/sw/controller/src/loader.S new file mode 100644 index 0000000..da493c8 --- /dev/null +++ b/sw/controller/src/loader.S @@ -0,0 +1,99 @@ +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb + +.section .text.Reset_Handler +.type Reset_Handler, %function +Reset_Handler: + .global Reset_Handler + cpsid i + +init_text: + ldr r0, =_stext + ldr r1, =_etext + ldr r2, =_sitext + bl copy_section + +init_rodata: + ldr r0, =_srodata + ldr r1, =_erodata + ldr r2, =_sirodata + bl copy_section + +init_data: + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + bl copy_section + +init_bss: + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b 2f +1: + str r3, [r2] + adds r2, r2, #4 +2: + cmp r2, r4 + bcc 1b + +run: + bl loader + +boot: + ldr r0, =_app_magic + ldr r0, [r0] + ldr r1, =0x34364353 + cmp r0, r1 + bne empty_image + + ldr r0, =_app_header + push {r0} + bl set_vector_table_offset + pop {r0} + ldr r1, [r0, #0] + msr MSP, r1 + ldr r1, [r0, #4] + blx r1 + +empty_image: + bl no_valid_image + +loop: + b loop + +copy_section: + movs r3, #0 + b 2f +1: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 +2: + adds r4, r0, r3 + cmp r4, r1 + bcc 1b + bx lr + + +.section .text.Default_Handler, "ax", %progbits +Default_Handler: + .global Default_Handler + b Default_Handler + + +.section .isr_vector, "a", %progbits +.type g_pfnVectors, %object +g_pfnVectors: + .global g_pfnVectors + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + + .weak NMI_Handler + .thumb_set NMI_Handler, Default_Handler + .weak HardFault_Handler + .thumb_set HardFault_Handler, Default_Handler diff --git a/sw/controller/src/loader.c b/sw/controller/src/loader.c new file mode 100644 index 0000000..9a10708 --- /dev/null +++ b/sw/controller/src/loader.c @@ -0,0 +1,20 @@ +#include +#include +#include "hw.h" +#include "update.h" + + +void loader (void) { + if (update_check()) { + hw_loader_init(); + update_perform(); + } +} + +void no_valid_image (void) { + hw_gpio_set(GPIO_ID_LED); +} + +void set_vector_table_offset (uint32_t offset) { + SCB->VTOR = (__IOM uint32_t) (offset); +} diff --git a/sw/controller/src/rtc.c b/sw/controller/src/rtc.c new file mode 100644 index 0000000..3aad083 --- /dev/null +++ b/sw/controller/src/rtc.c @@ -0,0 +1,289 @@ +#include "fpga.h" +#include "hw.h" +#include "led.h" +#include "rtc.h" +#include "task.h" + + +#define RTC_I2C_ADDRESS (0xDE) + +#define RTC_ADDRESS_RTCSEC (0x00) +#define RTC_ADDRESS_RTCMIN (0x01) +#define RTC_ADDRESS_RTCHOUR (0x02) +#define RTC_ADDRESS_RTCWKDAY (0x03) +#define RTC_ADDRESS_RTCDATE (0x04) +#define RTC_ADDRESS_RTCMTH (0x05) +#define RTC_ADDRESS_RTCYEAR (0x06) +#define RTC_ADDRESS_CONTROL (0x07) +#define RTC_ADDRESS_OSCTRIM (0x08) +#define RTC_ADDRESS_SRAM_MAGIC (0x20) +#define RTC_ADDRESS_SRAM_REGION (0x24) + +#define RTC_RTCSEC_ST (1 << 7) + +#define RTC_RTCWKDAY_VBATEN (1 << 3) +#define RTC_RTCWKDAY_OSCRUN (1 << 5) + + +static uint8_t rtc_region = 0xFF; +static volatile bool rtc_region_pending = false; +static rtc_time_t rtc_time = { + .second = 0x00, + .minute = 0x00, + .hour = 0x12, + .weekday = 0x02, + .day = 0x01, + .month = 0x03, + .year = 0x22 +}; +static bool rtc_time_valid = false; +static volatile bool rtc_time_pending = false; + +static const uint8_t rtc_regs_bit_mask[7] = { + 0b01111111, + 0b01111111, + 0b00111111, + 0b00000111, + 0b00111111, + 0b00011111, + 0b11111111 +}; + + +static void rtc_task_resume (void) { + task_set_ready(TASK_ID_RTC); +} + +static void rtc_on_error (void) { + rtc_time_valid = false; + led_blink_error(LED_ERROR_RTC); + task_yield(); +} + +static void rtc_read (uint8_t address, uint8_t *data, uint8_t length) { + hw_i2c_read(RTC_I2C_ADDRESS, address, data, length, rtc_task_resume); + task_yield(); + if (hw_i2c_get_error()) { + rtc_on_error(); + } +} + +static void rtc_write (uint8_t address, uint8_t *data, uint8_t length) { + hw_i2c_write(RTC_I2C_ADDRESS, address, data, length, rtc_task_resume); + task_yield(); + if (hw_i2c_get_error()) { + rtc_on_error(); + } +} + +static void rtc_sanitize_time (uint8_t *regs) { + for (int i = 0; i < 7; i++) { + regs[i] &= rtc_regs_bit_mask[i]; + } +} + +static void rtc_wait_osc (bool running) { + uint8_t rtcwkday; + + while (1) { + rtc_read(RTC_ADDRESS_RTCWKDAY, &rtcwkday, 1); + + if (running && (rtcwkday & RTC_RTCWKDAY_OSCRUN)) { + return; + } else if (!running && (!(rtcwkday & RTC_RTCWKDAY_OSCRUN))) { + return; + } + } +} + +static void rtc_read_time (void) { + uint8_t regs[7]; + + rtc_read(RTC_ADDRESS_RTCSEC, regs, 7); + + rtc_sanitize_time(regs); + + if (!rtc_time_pending) { + rtc_time.second = regs[0]; + rtc_time.minute = regs[1]; + rtc_time.hour = regs[2]; + rtc_time.weekday = regs[3]; + rtc_time.day = regs[4]; + rtc_time.month = regs[5]; + rtc_time.year = regs[6]; + + rtc_time_valid = true; + } +} + +static void rtc_write_time (void) { + uint8_t regs[7]; + + regs[0] = 0x00; + + rtc_write(RTC_ADDRESS_RTCSEC, regs, 1); + + rtc_wait_osc(false); + + regs[0] = rtc_time.second; + regs[1] = rtc_time.minute; + regs[2] = rtc_time.hour; + regs[3] = rtc_time.weekday; + regs[4] = rtc_time.day; + regs[5] = rtc_time.month; + regs[6] = rtc_time.year; + + rtc_sanitize_time(regs); + + regs[0] |= RTC_RTCSEC_ST; + regs[3] |= (RTC_RTCWKDAY_OSCRUN | RTC_RTCWKDAY_VBATEN); + + rtc_write(RTC_ADDRESS_RTCSEC, regs, 7); + + rtc_wait_osc(true); +} + +static void rtc_read_region (void) { + rtc_read(RTC_ADDRESS_SRAM_REGION, &rtc_region, 1); +} + +static void rtc_write_region (void) { + rtc_write(RTC_ADDRESS_SRAM_REGION, &rtc_region, 1); +} + +static void rtc_init (void) { + bool uninitialized = false; + const char *magic = "SC64"; + uint8_t buffer[4]; + + rtc_read(RTC_ADDRESS_SRAM_MAGIC, buffer, 4); + + for (int i = 0; i < 4; i++) { + if (buffer[i] != magic[i]) { + uninitialized = true; + break; + } + } + + if (uninitialized) { + buffer[0] = 0; + rtc_write(RTC_ADDRESS_SRAM_MAGIC, (uint8_t *) (magic), 4); + rtc_write(RTC_ADDRESS_OSCTRIM, buffer, 1); + rtc_write_time(); + rtc_write_region(); + } +} + + +bool rtc_get_time (rtc_time_t *time) { + bool vaild; + + hw_i2c_disable_irq(); + hw_tim_disable_irq(TIM_ID_RTC); + + time->second = rtc_time.second; + time->minute = rtc_time.minute; + time->hour = rtc_time.hour; + time->weekday = rtc_time.weekday; + time->day = rtc_time.day; + time->month = rtc_time.month; + time->year = rtc_time.year; + vaild = rtc_time_valid; + + hw_tim_enable_irq(TIM_ID_RTC); + hw_i2c_enable_irq(); + + return vaild; +} + +void rtc_set_time (rtc_time_t *time) { + hw_i2c_disable_irq(); + hw_tim_disable_irq(TIM_ID_RTC); + + rtc_time.second = time->second; + rtc_time.minute = time->minute; + rtc_time.hour = time->hour; + rtc_time.weekday = time->weekday; + rtc_time.day = time->day; + rtc_time.month = time->month; + rtc_time.year = time->year; + rtc_time_pending = true; + + hw_tim_enable_irq(TIM_ID_RTC); + hw_i2c_enable_irq(); +} + +uint8_t rtc_get_region (void) { + return rtc_region; +} + +void rtc_set_region (uint8_t region) { + rtc_region = region; + rtc_region_pending = true; +} + +void rtc_task (void) { + rtc_init(); + + rtc_read_region(); + + while (1) { + if (rtc_time_pending) { + rtc_time_pending = false; + rtc_write_time(); + } + + if (rtc_region_pending) { + rtc_region_pending = false; + rtc_write_region(); + } + + rtc_read_time(); + + hw_tim_setup(TIM_ID_RTC, 50, rtc_task_resume); + + task_yield(); + } +} + +void rtc_process (void) { + rtc_time_t time; + uint32_t data[2]; + uint32_t scr = fpga_reg_get(REG_RTC_SCR); + + if ((scr & RTC_SCR_PENDING) && ((scr & RTC_SCR_MAGIC_MASK) == RTC_SCR_MAGIC)) { + data[0] = fpga_reg_get(REG_RTC_TIME_0); + data[1] = fpga_reg_get(REG_RTC_TIME_1); + + time.weekday = ((data[0] >> 24) & 0xFF) + 1; + time.hour = ((data[0] >> 16) & 0xFF); + time.minute = ((data[0] >> 8) & 0xFF); + time.second = ((data[0] >> 0) & 0xFF); + time.year = ((data[1] >> 16) & 0xFF); + time.month = ((data[1] >> 8) & 0xFF); + time.day = ((data[1] >> 0) & 0xFF); + + rtc_set_time(&time); + + fpga_reg_set(REG_RTC_TIME_0, data[0]); + fpga_reg_set(REG_RTC_TIME_1, data[1]); + fpga_reg_set(REG_RTC_SCR, RTC_SCR_DONE); + } + + rtc_get_time(&time); + + data[0] = ( + ((time.weekday - 1) << 24) | + (time.hour << 16) | + (time.minute << 8) | + (time.second << 0) + ); + data[1] = ( + (time.year << 16) | + (time.month << 8) | + (time.day << 0) + ); + + fpga_reg_set(REG_RTC_TIME_0, data[0]); + fpga_reg_set(REG_RTC_TIME_1, data[1]); +} diff --git a/sw/riscv/src/rtc.h b/sw/controller/src/rtc.h similarity index 52% rename from sw/riscv/src/rtc.h rename to sw/controller/src/rtc.h index 02937e4..3df6502 100644 --- a/sw/riscv/src/rtc.h +++ b/sw/controller/src/rtc.h @@ -2,7 +2,8 @@ #define RTC_H__ -#include "sys.h" +#include +#include typedef struct { @@ -16,12 +17,12 @@ typedef struct { } rtc_time_t; -rtc_time_t *rtc_get_time (void); -bool rtc_is_time_valid (void); -bool rtc_is_time_running (void); +bool rtc_get_time (rtc_time_t *time); void rtc_set_time (rtc_time_t *time); -void rtc_init (void); -void process_rtc (void); +uint8_t rtc_get_region (void); +void rtc_set_region (uint8_t region); +void rtc_task (void); +void rtc_process (void); #endif diff --git a/sw/controller/src/sd.c b/sw/controller/src/sd.c new file mode 100644 index 0000000..5202da5 --- /dev/null +++ b/sw/controller/src/sd.c @@ -0,0 +1,442 @@ +#include +#include +#include "fpga.h" +#include "hw.h" +#include "led.h" +#include "sd.h" + + +#define SD_INIT_BUFFER_ADDRESS (0x05002800UL) + +#define CMD6_ARG_CHECK_HS (0x00FFFFF1UL) +#define CMD6_ARG_SWITCH_HS (0x80FFFFF1UL) + +#define CMD8_ARG_SUPPLY_VOLTAGE_27_36_V (1 << 8) +#define CMD8_ARG_CHECK_PATTERN (0xAA << 0) + +#define ACMD6_ARG_BUS_WIDTH_4BIT (2 << 0) + +#define ACMD41_ARG_OCR (0x300000 << 0) +#define ACMD41_ARG_HCS (1 << 30) + +#define R3_OCR (0x300000 << 0) +#define R3_CCS (1 << 30) +#define R3_BUSY (1 << 31) + +#define R6_RCA_MASK (0xFFFF0000UL) + +#define R7_SUPPLY_VOLTAGE_27_36_V (1 << 8) +#define R7_CHECK_PATTERN (0xAA << 0) + +#define SWITCH_FUNCTION_CURRENT_LIMIT (SD_INIT_BUFFER_ADDRESS + 0) +#define SWITCH_FUNCTION_GROUP_1 (SD_INIT_BUFFER_ADDRESS + 12) +#define SWITCH_FUNCTION_GROUP_1_HS (1 << 1) + +#define DAT_BLOCK_MAX_COUNT (256) + + +typedef enum { + CLOCK_STOP, + CLOCK_400KHZ, + CLOCK_25MHZ, + CLOCK_50MHZ, +} sd_clock_t; + +typedef enum { + RSP_NONE, + RSP_R1, + RSP_R1b, + RSP_R2, + RSP_R3, + RSP_R6, + RSP_R7, +} rsp_type_t; + +typedef enum { + DAT_READ, + DAT_WRITE, +} dat_mode_t; + + +struct process { + bool card_initialized; + bool card_type_block; + uint32_t rca; + uint8_t csd[16]; + uint8_t cid[16]; + volatile bool timeout; +}; + + +static struct process p; + + +static void sd_trigger_timeout (void) { + p.timeout = true; +} + +static void sd_prepare_timeout (uint16_t value) { + p.timeout = false; + hw_tim_setup(TIM_ID_SD, value, sd_trigger_timeout); +} + +static bool sd_did_timeout (void) { + return p.timeout; +} + +static void sd_clear_timeout (void) { + hw_tim_stop(TIM_ID_SD); + p.timeout = false; +} + +static void sd_set_clock (sd_clock_t mode) { + fpga_reg_set(REG_SD_SCR, SD_SCR_CLOCK_MODE_OFF); + + switch (mode) { + case CLOCK_400KHZ: + fpga_reg_set(REG_SD_SCR, SD_SCR_CLOCK_MODE_400KHZ); + break; + case CLOCK_25MHZ: + fpga_reg_set(REG_SD_SCR, SD_SCR_CLOCK_MODE_25MHZ); + break; + case CLOCK_50MHZ: + fpga_reg_set(REG_SD_SCR, SD_SCR_CLOCK_MODE_50MHZ); + break; + default: + break; + } +} + +static bool sd_cmd (uint8_t cmd, uint32_t arg, rsp_type_t rsp_type, void *rsp) { + uint32_t scr; + uint32_t cmd_data; + + cmd_data = ((cmd << SD_CMD_INDEX_BIT) & SD_CMD_INDEX_MASK); + switch (rsp_type) { + case RSP_NONE: + cmd_data |= SD_CMD_SKIP_RESPONSE; + break; + case RSP_R2: + cmd_data |= (SD_CMD_LONG_RESPONSE | SD_CMD_RESERVED_RESPONSE); + break; + case RSP_R3: + cmd_data |= (SD_CMD_IGNORE_CRC | SD_CMD_RESERVED_RESPONSE); + break; + default: + break; + } + + fpga_reg_set(REG_SD_ARG, arg); + fpga_reg_set(REG_SD_CMD, cmd_data); + + do { + scr = fpga_reg_get(REG_SD_SCR); + } while (scr & SD_SCR_CMD_BUSY); + + if (rsp != NULL) { + if (cmd_data & SD_CMD_LONG_RESPONSE) { + uint8_t *rsp_8 = (uint8_t *) (rsp); + for (int i = 0; i < 4; i++) { + uint32_t rsp_data = fpga_reg_get(REG_SD_RSP_3 - i); + uint8_t *rsp_data_8 = (uint8_t *) (&rsp_data); + rsp_data = SWAP32(rsp_data); + for (int i = 0; i < 4; i++) { + *rsp_8++ = *rsp_data_8++; + } + } + } else { + (*(uint32_t *) (rsp)) = fpga_reg_get(REG_SD_RSP_0); + } + } + + if (rsp_type == RSP_R1b) { + do { + scr = fpga_reg_get(REG_SD_SCR); + } while (scr & SD_SCR_CARD_BUSY); + } + + return (scr & SD_SCR_CMD_ERROR); +} + +static bool sd_acmd (uint8_t acmd, uint32_t arg, rsp_type_t rsp_type, void *rsp) { + if (sd_cmd(55, p.rca, RSP_R1, NULL)) { + return true; + } + if (sd_cmd(acmd, arg, rsp_type, rsp)) { + return true; + } + return false; +} + +static void sd_dat_prepare (uint32_t address, uint32_t count, dat_mode_t mode) { + uint32_t length = (count * SD_SECTOR_SIZE); + uint32_t sd_dat = (((count - 1) << SD_DAT_BLOCKS_BIT) | SD_DAT_FIFO_FLUSH); + uint32_t sd_dma_scr = DMA_SCR_START; + + if (mode == DAT_READ) { + sd_dat |= SD_DAT_START_READ; + sd_dma_scr |= DMA_SCR_DIRECTION; + } else { + sd_dat |= SD_DAT_START_WRITE; + } + + fpga_reg_set(REG_SD_DAT, sd_dat); + fpga_reg_set(REG_SD_DMA_ADDRESS, address); + fpga_reg_set(REG_SD_DMA_LENGTH, length); + fpga_reg_set(REG_SD_DMA_SCR, sd_dma_scr); +} + +static void sd_dat_abort (void) { + fpga_reg_set(REG_SD_DMA_SCR, DMA_SCR_STOP); + fpga_reg_set(REG_SD_DAT, SD_DAT_STOP | SD_DAT_FIFO_FLUSH); +} + +static bool sd_dat_wait (uint16_t timeout) { + sd_prepare_timeout(timeout); + + do { + uint32_t sd_dat = fpga_reg_get(REG_SD_DAT); + uint32_t sd_dma_scr = fpga_reg_get(REG_SD_DMA_SCR); + if ((!(sd_dat & SD_DAT_BUSY)) && (!(sd_dma_scr & DMA_SCR_BUSY))) { + sd_clear_timeout(); + return (sd_dat & SD_DAT_ERROR); + } + } while (!sd_did_timeout()); + + sd_dat_abort(); + + return true; +} + + +bool sd_card_init (void) { + uint32_t arg; + uint32_t rsp; + uint16_t tmp; + + if (p.card_initialized) { + return false; + } + + p.card_initialized = true; + p.rca = 0; + + led_blink_act(); + + sd_set_clock(CLOCK_400KHZ); + + sd_cmd(0, 0, RSP_NONE, NULL); + + arg = (CMD8_ARG_SUPPLY_VOLTAGE_27_36_V | CMD8_ARG_CHECK_PATTERN); + if (sd_cmd(8, arg, RSP_R7, &rsp)) { + arg = ACMD41_ARG_OCR; + } else { + if (rsp != (R7_SUPPLY_VOLTAGE_27_36_V | R7_CHECK_PATTERN)) { + sd_card_deinit(); + return true; + } + arg = (ACMD41_ARG_HCS | ACMD41_ARG_OCR); + } + + sd_prepare_timeout(1000); + do { + if (sd_did_timeout()) { + sd_card_deinit(); + return true; + } + if (sd_acmd(41, arg, RSP_R3, &rsp)) { + sd_card_deinit(); + return true; + } + if (rsp & R3_BUSY) { + if ((rsp & R3_OCR) == 0) { + sd_card_deinit(); + return true; + } + p.card_type_block = (rsp & R3_CCS); + break; + } + } while (1); + sd_clear_timeout(); + + if (sd_cmd(2, 0, RSP_R2, NULL)) { + sd_card_deinit(); + return true; + } + + if (sd_cmd(3, 0, RSP_R6, &rsp)) { + sd_card_deinit(); + return true; + } + p.rca = (rsp & R6_RCA_MASK); + + if (sd_cmd(9, p.rca, RSP_R2, p.csd)) { + sd_card_deinit(); + return true; + } + + if (sd_cmd(10, p.rca, RSP_R2, p.cid)) { + sd_card_deinit(); + return true; + } + + if (sd_cmd(7, p.rca, RSP_R1b, NULL)) { + sd_card_deinit(); + return true; + } + + sd_set_clock(CLOCK_25MHZ); + + if (sd_acmd(6, ACMD6_ARG_BUS_WIDTH_4BIT, RSP_R1, NULL)) { + sd_card_deinit(); + return true; + } + + sd_dat_prepare(SD_INIT_BUFFER_ADDRESS, 1, DAT_READ); + if (sd_cmd(6, CMD6_ARG_CHECK_HS, RSP_R1, NULL)) { + sd_dat_abort(); + sd_card_deinit(); + return true; + } + sd_dat_wait(1000); + if (sd_did_timeout()) { + sd_card_deinit(); + return true; + } + fpga_mem_read(SWITCH_FUNCTION_CURRENT_LIMIT, 2, (uint8_t *) (&tmp)); + if (SWAP16(tmp) == 0) { + sd_card_deinit(); + return true; + } + fpga_mem_read(SWITCH_FUNCTION_GROUP_1, 2, (uint8_t *) (&tmp)); + if (SWAP16(tmp) & SWITCH_FUNCTION_GROUP_1_HS) { + sd_dat_prepare(SD_INIT_BUFFER_ADDRESS, 1, DAT_READ); + if (sd_cmd(6, CMD6_ARG_SWITCH_HS, RSP_R1, NULL)) { + sd_dat_abort(); + sd_card_deinit(); + return true; + } + sd_dat_wait(1000); + if (sd_did_timeout()) { + sd_card_deinit(); + return true; + } + fpga_mem_read(SWITCH_FUNCTION_GROUP_1, 2, (uint8_t *) (&tmp)); + if (SWAP16(tmp) & SWITCH_FUNCTION_GROUP_1_HS) { + sd_set_clock(CLOCK_50MHZ); + } + } + + return false; +} + +void sd_card_deinit (void) { + if (p.card_initialized) { + p.card_initialized = false; + sd_set_clock(CLOCK_400KHZ); + sd_cmd(0, 0, RSP_NONE, NULL); + sd_set_clock(CLOCK_STOP); + } +} + +uint32_t sd_card_get_status (void) { + uint32_t scr = fpga_reg_get(REG_SD_SCR); + uint32_t clock_mode_50mhz = ((scr & SD_SCR_CLOCK_MODE_MASK) == SD_SCR_CLOCK_MODE_50MHZ) ? 1 : 0; + uint32_t card_type_block = p.card_type_block ? 1 : 0; + uint32_t initialized = p.card_initialized ? 1 : 0; + return ( + (clock_mode_50mhz << 2) | + (card_type_block << 1) | + (initialized << 0) + ); +} + +bool sd_card_get_info (uint32_t address) { + if (!p.card_initialized) { + return true; + } + fpga_mem_write(address, sizeof(p.csd), p.csd); + address += sizeof(p.csd); + fpga_mem_write(address, sizeof(p.cid), p.cid); + address += sizeof(p.cid); + return false; +} + +bool sd_write_sectors (uint32_t address, uint32_t sector, uint32_t count) { + if (!p.card_initialized || (count == 0)) { + return true; + } + + if (!p.card_type_block) { + sector *= SD_SECTOR_SIZE; + } + + while (count > 0) { + uint32_t blocks = ((count > DAT_BLOCK_MAX_COUNT) ? DAT_BLOCK_MAX_COUNT : count); + led_blink_act(); + if (sd_cmd(23, blocks, RSP_R1, NULL)) { + return true; + } + if (sd_cmd(25, sector, RSP_R1, NULL)) { + return true; + } + sd_dat_prepare(address, blocks, DAT_WRITE); + if (sd_dat_wait(1000)) { + sd_dat_abort(); + sd_cmd(12, 0, RSP_R1b, NULL); + return true; + } + sd_cmd(12, 0, RSP_R1b, NULL); + address += (blocks * SD_SECTOR_SIZE); + sector += (blocks * (p.card_type_block ? 1 : SD_SECTOR_SIZE)); + count -= blocks; + } + + return false; +} + +bool sd_read_sectors (uint32_t address, uint32_t sector, uint32_t count) { + if (!p.card_initialized || (count == 0)) { + return true; + } + + if (!p.card_type_block) { + sector *= SD_SECTOR_SIZE; + } + + while (count > 0) { + uint32_t blocks = ((count > DAT_BLOCK_MAX_COUNT) ? DAT_BLOCK_MAX_COUNT : count); + led_blink_act(); + sd_dat_prepare(address, blocks, DAT_READ); + if (sd_cmd(23, blocks, RSP_R1, NULL)) { + sd_dat_abort(); + return true; + } + if (sd_cmd(18, sector, RSP_R1, NULL)) { + sd_dat_abort(); + return true; + } + if (sd_dat_wait(1000)) { + if (sd_did_timeout()) { + sd_cmd(12, 0, RSP_R1b, NULL); + } + return true; + } + address += (blocks * SD_SECTOR_SIZE); + sector += (blocks * (p.card_type_block ? 1 : SD_SECTOR_SIZE)); + count -= blocks; + } + + return false; +} + +void sd_init (void) { + p.card_initialized = false; + sd_set_clock(CLOCK_STOP); +} + +void sd_process (void) { + if (!(fpga_reg_get(REG_SD_SCR) & SD_SCR_CARD_INSERTED)) { + sd_card_deinit(); + } +} diff --git a/sw/controller/src/sd.h b/sw/controller/src/sd.h new file mode 100644 index 0000000..40445a5 --- /dev/null +++ b/sw/controller/src/sd.h @@ -0,0 +1,21 @@ +#ifndef SD_H__ +#define SD_H__ + + +#include + + +#define SD_SECTOR_SIZE (512) + + +bool sd_card_init (void); +void sd_card_deinit (void); +uint32_t sd_card_get_status (void); +bool sd_card_get_info (uint32_t address); +bool sd_write_sectors (uint32_t address, uint32_t sector, uint32_t count); +bool sd_read_sectors (uint32_t address, uint32_t sector, uint32_t count); +void sd_init (void); +void sd_process (void); + + +#endif diff --git a/sw/controller/src/task.c b/sw/controller/src/task.c new file mode 100644 index 0000000..7731e5f --- /dev/null +++ b/sw/controller/src/task.c @@ -0,0 +1,145 @@ +#include +#include +#include "task.h" + + +#define TASK_INITIAL_XPSR (0x21000000UL) +#define TASK_CONTEXT_SWITCH() { SCB->ICSR = (1 << SCB_ICSR_PENDSVSET_Pos); } + + +typedef enum { + TASK_FLAG_NONE = 0, + TASK_FLAG_READY = (1 << 0), + TASK_FLAG_RESET = (1 << 1), +} task_flags_t; + + +typedef struct { + uint32_t initial_pc; + uint32_t initial_sp; + uint32_t sp; + task_flags_t flags; +} task_t; + + +static task_t task_table[__TASK_ID_MAX]; +static volatile task_id_t task_current = 0; + + +static void task_exit (void) { + task_table[task_current].flags = TASK_FLAG_NONE; + task_yield(); + while (1); +} + +static void task_initialize (task_id_t id) { + task_t *task = &task_table[id]; + uint32_t *sp = ((uint32_t *) (task->initial_sp)); + *--sp = TASK_INITIAL_XPSR; + *--sp = task->initial_pc; + *--sp = ((uint32_t) (task_exit)); + sp -= 13; + task->sp = ((uint32_t) (sp)); +} + +static void task_reset (task_id_t id) { + task_table[id].flags &= ~(TASK_FLAG_RESET); + task_initialize(id); +} + +static uint32_t task_switch_context (uint32_t sp) { + task_table[task_current].sp = sp; + + for (task_id_t id = 0; id < __TASK_ID_MAX; id++) { + if (task_table[id].flags & TASK_FLAG_READY) { + task_current = id; + break; + } + } + + if (task_table[task_current].flags & TASK_FLAG_RESET) { + task_reset(task_current); + } + + return task_table[task_current].sp; +} + + +void task_create (task_id_t id, void (*code)(void), void *stack, size_t stack_size) { + if (id < __TASK_ID_MAX) { + task_t *task = &task_table[id]; + task->initial_pc = (uint32_t) (code); + task->initial_sp = (((uint32_t) (stack)) + stack_size); + task->flags = TASK_FLAG_READY; + task_initialize(id); + } +} + +void task_yield (void) { + task_table[task_current].flags &= ~(TASK_FLAG_READY); + TASK_CONTEXT_SWITCH(); +} + +void task_set_ready (task_id_t id) { + task_table[id].flags |= TASK_FLAG_READY; + TASK_CONTEXT_SWITCH(); +} + +void task_set_ready_and_reset (task_id_t id) { + task_table[id].flags |= (TASK_FLAG_RESET | TASK_FLAG_READY); + TASK_CONTEXT_SWITCH(); +} + +__attribute__((naked)) void task_scheduler_start (void) { + uint32_t sp = task_table[task_current].sp; + + NVIC_SetPriority(PendSV_IRQn, 3); + + asm volatile ( + "add %[sp], #32 \n" + "msr psp, %[sp] \n" + "movs r0, #2 \n" + "msr CONTROL, r0 \n" + "isb \n" + "pop {r0-r5} \n" + "mov lr, r5 \n" + "pop {r3} \n" + "pop {r2} \n" + "cpsie i \n" + "bx r3 \n" + :: [sp] "r" (sp) + ); + + while (1); +} + + +__attribute__((naked)) void PendSV_Handler (void) { + asm volatile ( + "mrs r1, psp \n" + "sub r1, r1, #32 \n" + "mov r0, r1 \n" + "stmia r1!, {r4-r7} \n" + "mov r4, r8 \n" + "mov r5, r9 \n" + "mov r6, r10 \n" + "mov r7, r11 \n" + "stmia r1!, {r4-r7} \n" + "push {lr} \n" + "cpsid i \n" + "blx %[task_switch_context] \n" + "cpsie i \n" + "pop {r2} \n" + "add r0, #16 \n" + "ldmia r0!, {r4-r7} \n" + "mov r8, r4 \n" + "mov r9, r5 \n" + "mov r10, r6 \n" + "mov r11, r7 \n" + "msr psp, r0 \n" + "sub r0, #32 \n" + "ldmia r0!, {r4-r7} \n" + "bx r2 \n" + :: [task_switch_context] "r" (task_switch_context) + ); +} diff --git a/sw/controller/src/task.h b/sw/controller/src/task.h new file mode 100644 index 0000000..5185c34 --- /dev/null +++ b/sw/controller/src/task.h @@ -0,0 +1,24 @@ +#ifndef TASK_H__ +#define TASK_H__ + + +#include + + +typedef enum { + TASK_ID_CIC, + TASK_ID_RTC, + TASK_ID_LED, + TASK_ID_GVR, + __TASK_ID_MAX +} task_id_t; + + +void task_create (task_id_t id, void (*code)(void), void *stack, size_t stack_size); +void task_yield (void); +void task_set_ready (task_id_t id); +void task_set_ready_and_reset (task_id_t id); +void task_scheduler_start (void); + + +#endif diff --git a/sw/controller/src/update.c b/sw/controller/src/update.c new file mode 100644 index 0000000..52ab791 --- /dev/null +++ b/sw/controller/src/update.c @@ -0,0 +1,316 @@ +#include "flash.h" +#include "fpga.h" +#include "hw.h" +#include "update.h" +#include "usb.h" +#include "vendor.h" + + +#define UPDATE_MAGIC_START (0x54535055UL) +#define BOOTLOADER_ADDRESS (0x04E00000UL) +#define BOOTLOADER_LENGTH (0x001E0000UL) + + +typedef enum { + UPDATE_STATUS_MCU = 1, + UPDATE_STATUS_FPGA = 2, + UPDATE_STATUS_BOOTLOADER = 3, + UPDATE_STATUS_DONE = 0x80, + UPDATE_STATUS_ERROR = 0xFF, +} update_status_t; + +typedef enum { + CHUNK_ID_UPDATE_INFO = 1, + CHUNK_ID_MCU_DATA = 2, + CHUNK_ID_FPGA_DATA = 3, + CHUNK_ID_BOOTLOADER_DATA = 4, +} chunk_id_t; + + +static loader_parameters_t parameters; +static const uint8_t update_token[16] = "SC64 Update v2.0"; +static uint8_t status_data[12] = { + 'P', 'K', 'T', PACKET_CMD_UPDATE_STATUS, + 0, 0, 0, 4, + 0, 0, 0, UPDATE_STATUS_ERROR, +}; + + +static uint32_t update_align (uint32_t value) { + if ((value % 16) != 0) { + value += (16 - (value % 16)); + } + return value; +} + +static uint32_t update_checksum (uint32_t address, uint32_t length) { + uint8_t buffer[128]; + uint32_t block_size; + uint32_t checksum = 0; + hw_crc32_reset(); + while (length > 0) { + block_size = (length > sizeof(buffer)) ? sizeof(buffer) : length; + fpga_mem_read(address, block_size, buffer); + checksum = hw_crc32_calculate(buffer, block_size); + address += block_size; + length -= block_size; + } + return checksum; +} + +static uint32_t update_write_token (uint32_t *address) { + uint32_t length = sizeof(update_token); + fpga_mem_write(*address, sizeof(update_token), (uint8_t *) (update_token)); + *address += length; + return length; +} + +static uint32_t update_prepare_chunk (uint32_t *address, chunk_id_t chunk_id) { + uint32_t id = (uint32_t) (chunk_id); + uint32_t length = (4 * sizeof(uint32_t)); + fpga_mem_write(*address, sizeof(id), (uint8_t *) (&id)); + *address += length; + return length; +} + +static uint32_t update_finalize_chunk (uint32_t *address, uint32_t length) { + uint32_t chunk_length = ((4 * sizeof(uint32_t)) + length); + uint32_t aligned_chunk_length = update_align(chunk_length); + uint32_t aligned_length = aligned_chunk_length - (2 * sizeof(uint32_t)); + uint32_t checksum = update_checksum(*address, length); + fpga_mem_write(*address - (3 * sizeof(uint32_t)), sizeof(aligned_length), (uint8_t *) (&aligned_length)); + fpga_mem_write(*address - (2 * sizeof(uint32_t)), sizeof(checksum), (uint8_t *) (&checksum)); + fpga_mem_write(*address - sizeof(uint32_t), sizeof(length), (uint8_t *) (&length)); + length += (aligned_chunk_length - chunk_length); + *address += length; + return length; +} + +static bool update_check_token (uint32_t *address) { + uint8_t buffer[sizeof(update_token)]; + fpga_mem_read(*address, sizeof(update_token), buffer); + for (int i = 0; i < sizeof(update_token); i++) { + if (buffer[i] != update_token[i]) { + return true; + } + } + *address += sizeof(update_token); + return false; +} + +static bool update_get_chunk (uint32_t *address, chunk_id_t *chunk_id, uint32_t *data_address, uint32_t *data_length) { + uint32_t id; + uint32_t chunk_length; + uint32_t checksum; + fpga_mem_read(*address, sizeof(id), (uint8_t *) (&id)); + *chunk_id = (chunk_id_t) (id); + *address += sizeof(id); + fpga_mem_read(*address, sizeof(chunk_length), (uint8_t *) (&chunk_length)); + *address += sizeof(chunk_length); + fpga_mem_read(*address, sizeof(checksum), (uint8_t *) (&checksum)); + *address += sizeof(checksum); + fpga_mem_read(*address, sizeof(*data_length), (uint8_t *) (data_length)); + *address += sizeof(*data_length); + *data_address = *address; + *address += (chunk_length - (2 * sizeof(uint32_t))); + if (checksum != update_checksum(*data_address, *data_length)) { + return true; + } + return false; +} + +static void update_blink_led (uint32_t on, uint32_t off, int repeat) { + for (int i = 0; i < repeat; i++) { + hw_gpio_set(GPIO_ID_LED); + hw_delay_ms(on); + hw_gpio_reset(GPIO_ID_LED); + hw_delay_ms(off); + } +} + +static void update_status_notify (update_status_t status) { + status_data[sizeof(status_data) - 1] = (uint8_t) (status); + for (int i = 0; i < sizeof(status_data); i++) { + while (!(fpga_usb_status_get() & USB_STATUS_TXE)); + fpga_usb_push(status_data[i]); + } + fpga_reg_set(REG_USB_SCR, USB_SCR_WRITE_FLUSH); + if (status == UPDATE_STATUS_DONE) { + update_blink_led(15, 85, 10); + } else if (status == UPDATE_STATUS_ERROR) { + update_blink_led(1000, 1000, 30); + } else { + update_blink_led(15, 185, 2); + hw_delay_ms(500); + } +} + +static bool mcu_update (uint32_t address, uint32_t length) { + hw_flash_t buffer; + hw_flash_erase(); + for (uint32_t offset = 0; offset < length; offset += sizeof(hw_flash_t)) { + fpga_mem_read(address + offset, sizeof(hw_flash_t), (uint8_t *) (&buffer)); + hw_flash_program(offset, buffer); + if (hw_flash_read(offset) != buffer) { + return true; + } + } + return false; +} + +static bool bootloader_update (uint32_t address, uint32_t length) { + uint8_t update_buffer[FPGA_MAX_MEM_TRANSFER]; + uint8_t verify_buffer[FPGA_MAX_MEM_TRANSFER]; + for (uint32_t offset = 0; offset < BOOTLOADER_LENGTH; offset += FLASH_ERASE_BLOCK_SIZE) { + flash_erase_block(BOOTLOADER_ADDRESS + offset); + } + for (uint32_t offset = 0; offset < length; offset += FPGA_MAX_MEM_TRANSFER) { + fpga_mem_copy(address + offset, BOOTLOADER_ADDRESS + offset, FPGA_MAX_MEM_TRANSFER); + } + for (uint32_t offset = 0; offset < length; offset += sizeof(verify_buffer)) { + fpga_mem_read(address + offset, sizeof(update_buffer), update_buffer); + fpga_mem_read(BOOTLOADER_ADDRESS + offset, sizeof(verify_buffer), verify_buffer); + for (int i = 0; i < sizeof(verify_buffer); i++) { + if (update_buffer[i] != verify_buffer[i]) { + return true; + } + } + } + return false; +} + + +update_error_t update_backup (uint32_t address, uint32_t *length) { + uint32_t mcu_length; + uint32_t fpga_length; + uint32_t bootloader_length; + + *length = update_write_token(&address); + + *length += update_prepare_chunk(&address, CHUNK_ID_MCU_DATA); + mcu_length = hw_flash_size(); + for (uint32_t offset = 0; offset < mcu_length; offset += sizeof(hw_flash_t)) { + hw_flash_t buffer = hw_flash_read(offset); + fpga_mem_write(address + offset, sizeof(hw_flash_t), (uint8_t *) (&buffer)); + } + *length += update_finalize_chunk(&address, mcu_length); + + *length += update_prepare_chunk(&address, CHUNK_ID_FPGA_DATA); + if (vendor_backup(address, &fpga_length) != VENDOR_OK) { + return UPDATE_ERROR_READ; + } + *length += update_finalize_chunk(&address, fpga_length); + + *length += update_prepare_chunk(&address, CHUNK_ID_BOOTLOADER_DATA); + bootloader_length = BOOTLOADER_LENGTH; + for (uint32_t offset = 0; offset < bootloader_length; offset += FPGA_MAX_MEM_TRANSFER) { + fpga_mem_copy(BOOTLOADER_ADDRESS + offset, address + offset, FPGA_MAX_MEM_TRANSFER); + } + *length += update_finalize_chunk(&address, bootloader_length); + + return UPDATE_OK; +} + +update_error_t update_prepare (uint32_t address, uint32_t length) { + uint32_t end_address = (address + length); + chunk_id_t id; + uint32_t data_address; + uint32_t data_length; + + if (update_check_token(&address)) { + return UPDATE_ERROR_TOKEN; + } + + parameters.flags = 0; + parameters.mcu_address = 0; + parameters.fpga_address = 0; + parameters.bootloader_address = 0; + + while (address < end_address) { + if (update_get_chunk(&address, &id, &data_address, &data_length)) { + return UPDATE_ERROR_CHECKSUM; + } + + switch (id) { + case CHUNK_ID_UPDATE_INFO: + break; + + case CHUNK_ID_MCU_DATA: + if (data_length > hw_flash_size()) { + return UPDATE_ERROR_SIZE; + } + parameters.flags |= LOADER_FLAGS_UPDATE_MCU; + parameters.mcu_address = data_address; + break; + + case CHUNK_ID_FPGA_DATA: + if (data_length > vendor_flash_size()) { + return UPDATE_ERROR_SIZE; + } + parameters.flags |= LOADER_FLAGS_UPDATE_FPGA; + parameters.fpga_address = data_address; + break; + + case CHUNK_ID_BOOTLOADER_DATA: + if (data_length > BOOTLOADER_LENGTH) { + return UPDATE_ERROR_SIZE; + } + parameters.flags |= LOADER_FLAGS_UPDATE_BOOTLOADER; + parameters.bootloader_address = data_address; + break; + + default: + return UPDATE_ERROR_UNKNOWN_CHUNK; + } + } + + return UPDATE_OK; +} + +void update_start (void) { + parameters.magic = UPDATE_MAGIC_START; + hw_loader_reset(¶meters); +} + +bool update_check (void) { + hw_loader_get_parameters(¶meters); + return (parameters.magic == UPDATE_MAGIC_START); +} + +void update_perform (void) { + uint32_t length; + + if (parameters.flags & LOADER_FLAGS_UPDATE_MCU) { + update_status_notify(UPDATE_STATUS_MCU); + fpga_mem_read(parameters.mcu_address - 4, sizeof(length), (uint8_t *) (&length)); + if (mcu_update(parameters.mcu_address, length)) { + update_status_notify(UPDATE_STATUS_ERROR); + while (1); + } + } + + if (parameters.flags & LOADER_FLAGS_UPDATE_FPGA) { + update_status_notify(UPDATE_STATUS_FPGA); + fpga_mem_read(parameters.fpga_address - 4, sizeof(length), (uint8_t *) (&length)); + if (vendor_update(parameters.fpga_address, length) != VENDOR_OK) { + update_status_notify(UPDATE_STATUS_ERROR); + while (1); + } + } + + if (parameters.flags & LOADER_FLAGS_UPDATE_BOOTLOADER) { + update_status_notify(UPDATE_STATUS_BOOTLOADER); + fpga_mem_read(parameters.bootloader_address - 4, sizeof(length), (uint8_t *) (&length)); + if (bootloader_update(parameters.bootloader_address, length)) { + update_status_notify(UPDATE_STATUS_ERROR); + while (1); + } + } + + update_status_notify(UPDATE_STATUS_DONE); + + vendor_reconfigure(); + + parameters.magic = 0; + hw_loader_reset(¶meters); +} diff --git a/sw/controller/src/update.h b/sw/controller/src/update.h new file mode 100644 index 0000000..b6f029c --- /dev/null +++ b/sw/controller/src/update.h @@ -0,0 +1,26 @@ +#ifndef UPDATE_H__ +#define UPDATE_H__ + + +#include +#include + + +typedef enum { + UPDATE_OK, + UPDATE_ERROR_TOKEN, + UPDATE_ERROR_CHECKSUM, + UPDATE_ERROR_SIZE, + UPDATE_ERROR_UNKNOWN_CHUNK, + UPDATE_ERROR_READ, +} update_error_t; + + +update_error_t update_backup (uint32_t address, uint32_t *length); +update_error_t update_prepare (uint32_t address, uint32_t length); +void update_start (void); +bool update_check (void); +void update_perform (void); + + +#endif diff --git a/sw/controller/src/usb.c b/sw/controller/src/usb.c new file mode 100644 index 0000000..ca73e75 --- /dev/null +++ b/sw/controller/src/usb.c @@ -0,0 +1,462 @@ +#include "cfg.h" +#include "cic.h" +#include "dd.h" +#include "flash.h" +#include "fpga.h" +#include "rtc.h" +#include "update.h" +#include "usb.h" + + +enum rx_state { + RX_STATE_IDLE, + RX_STATE_ARGS, + RX_STATE_DATA, +}; + +enum tx_state { + TX_STATE_IDLE, + TX_STATE_TOKEN, + TX_STATE_DATA, + TX_STATE_DMA, + TX_STATE_FLUSH, +}; + + +struct process { + enum rx_state rx_state; + uint8_t rx_counter; + uint8_t rx_cmd; + uint32_t rx_args[2]; + bool rx_dma_running; + + enum tx_state tx_state; + uint8_t tx_counter; + usb_tx_info_t tx_info; + uint32_t tx_token; + bool tx_dma_running; + + bool response_pending; + bool response_error; + usb_tx_info_t response_info; + + bool packet_pending; + usb_tx_info_t packet_info; + + bool read_ready; + uint32_t read_length; + uint32_t read_address; +}; + + +static struct process p; + + +static const char CMD_TOKEN[3] = { 'C', 'M', 'D' }; +static const uint32_t CMP_TOKEN = (0x434D5000UL); +static const uint32_t ERR_TOKEN = (0x45525200UL); +static const uint32_t PKT_TOKEN = (0x504B5400UL); + + +static bool usb_dma_ready (void) { + return !((fpga_reg_get(REG_USB_DMA_SCR) & DMA_SCR_BUSY)); +} + +static bool usb_rx_byte (uint8_t *data) { + if (fpga_usb_status_get() & USB_STATUS_RXNE) { + *data = fpga_usb_pop(); + return true; + } + return false; +} + +static bool usb_tx_byte (uint8_t data) { + if (fpga_usb_status_get() & USB_STATUS_TXE) { + fpga_usb_push(data); + return true; + } + return false; +} + +static uint8_t usb_rx_word_counter = 0; +static uint32_t usb_rx_word_buffer = 0; + +static bool usb_rx_word (uint32_t *data) { + uint8_t tmp; + while (usb_rx_byte(&tmp)) { + usb_rx_word_buffer = (usb_rx_word_buffer << 8) | tmp; + usb_rx_word_counter += 1; + if (usb_rx_word_counter == 4) { + usb_rx_word_counter = 0; + *data = usb_rx_word_buffer; + usb_rx_word_buffer = 0; + return true; + } + } + return false; +} + +static uint8_t usb_tx_word_counter = 0; + +static bool usb_tx_word (uint32_t data) { + while (usb_tx_byte(data >> ((3 - usb_tx_word_counter) * 8))) { + usb_tx_word_counter += 1; + if (usb_tx_word_counter == 4) { + usb_tx_word_counter = 0; + return true; + } + } + return false; +} + +static uint8_t usb_rx_cmd_counter = 0; + +static bool usb_rx_cmd (uint8_t *cmd) { + uint8_t data; + while (usb_rx_byte(&data)) { + if (usb_rx_cmd_counter == 3) { + *cmd = data; + usb_rx_cmd_counter = 0; + return true; + } + if (data != CMD_TOKEN[usb_rx_cmd_counter++]) { + usb_rx_cmd_counter = 0; + return false; + } + } + return false; +} + +static void usb_rx_process (void) { + if (p.rx_state == RX_STATE_IDLE) { + if (!p.response_pending && usb_rx_cmd(&p.rx_cmd)) { + p.rx_state = RX_STATE_ARGS; + p.rx_counter = 0; + p.rx_dma_running = false; + p.response_error = false; + p.response_info.cmd = p.rx_cmd; + p.response_info.data_length = 0; + p.response_info.dma_length = 0; + p.response_info.done_callback = NULL; + } + } + + if (p.rx_state == RX_STATE_ARGS) { + while (usb_rx_word(&p.rx_args[p.rx_counter])) { + p.rx_counter += 1; + if (p.rx_counter == 2) { + p.rx_counter = 0; + p.rx_state = RX_STATE_DATA; + break; + } + } + } + + if (p.rx_state == RX_STATE_DATA) { + switch (p.rx_cmd) { + case 'v': + p.rx_state = RX_STATE_IDLE; + p.response_pending = true; + p.response_info.data_length = 4; + p.response_info.data[0] = cfg_get_version(); + break; + + case 'R': + cfg_reset_state(); + cic_reset_parameters(); + p.rx_state = RX_STATE_IDLE; + p.response_pending = true; + break; + + case 'B': + cic_set_parameters(p.rx_args); + p.rx_state = RX_STATE_IDLE; + p.response_pending = true; + break; + + case 'c': + p.response_error = cfg_query(p.rx_args); + p.rx_state = RX_STATE_IDLE; + p.response_pending = true; + p.response_info.data_length = 4; + p.response_info.data[0] = p.rx_args[1]; + break; + + case 'C': + p.response_error = cfg_update(p.rx_args); + p.rx_state = RX_STATE_IDLE; + p.response_pending = true; + break; + + case 't': + cfg_get_time(p.rx_args); + p.rx_state = RX_STATE_IDLE; + p.response_pending = true; + p.response_info.data_length = 8; + p.response_info.data[0] = p.rx_args[0]; + p.response_info.data[1] = p.rx_args[1]; + break; + + case 'T': + cfg_set_time(p.rx_args); + p.rx_state = RX_STATE_IDLE; + p.response_pending = true; + break; + + case 'm': + p.rx_state = RX_STATE_IDLE; + p.response_pending = true; + p.response_info.dma_address = p.rx_args[0]; + p.response_info.dma_length = p.rx_args[1]; + break; + + case 'M': + if (usb_dma_ready()) { + if (!p.rx_dma_running) { + fpga_reg_set(REG_USB_DMA_ADDRESS, p.rx_args[0]); + fpga_reg_set(REG_USB_DMA_LENGTH, p.rx_args[1]); + fpga_reg_set(REG_USB_DMA_SCR, DMA_SCR_DIRECTION | DMA_SCR_START); + p.rx_dma_running = true; + } else { + p.rx_state = RX_STATE_IDLE; + p.response_pending = true; + } + } + break; + + case 'D': + dd_set_block_ready(p.rx_args[0] == 0); + p.rx_state = RX_STATE_IDLE; + p.response_pending = true; + break; + + case 'U': + if ((p.read_length > 0) && usb_dma_ready()) { + uint32_t length = (p.read_length > p.rx_args[1]) ? p.rx_args[1] : p.read_length; + if (!p.rx_dma_running) { + fpga_reg_set(REG_USB_DMA_ADDRESS, p.read_address); + fpga_reg_set(REG_USB_DMA_LENGTH, length); + fpga_reg_set(REG_USB_DMA_SCR, DMA_SCR_DIRECTION | DMA_SCR_START); + p.rx_dma_running = true; + p.read_ready = false; + } else { + p.rx_args[1] -= length; + p.read_length -= length; + p.read_address += length; + p.read_ready = true; + if (p.rx_args[1] == 0) { + p.rx_state = RX_STATE_IDLE; + } + } + } + break; + + case 'f': + p.response_info.data[0] = update_backup(p.rx_args[0], &p.response_info.data[1]); + p.rx_state = RX_STATE_IDLE; + p.response_pending = true; + p.response_error = (p.response_info.data[0] != UPDATE_OK); + p.response_info.data_length = 8; + break; + + case 'F': + p.response_info.data[0] = update_prepare(p.rx_args[0], p.rx_args[1]); + p.rx_state = RX_STATE_IDLE; + p.response_pending = true; + p.response_info.data_length = 4; + if (p.response_info.data[0] == UPDATE_OK) { + p.response_info.done_callback = update_start; + } else { + p.response_error = true; + } + break; + + case 'p': + flash_wait_busy(); + p.rx_state = RX_STATE_IDLE; + p.response_pending = true; + p.response_info.data_length = 4; + p.response_info.data[0] = FLASH_ERASE_BLOCK_SIZE; + break; + + case 'P': + flash_erase_block(p.rx_args[0]); + p.rx_state = RX_STATE_IDLE; + p.response_pending = true; + break; + + case '?': + p.rx_state = RX_STATE_IDLE; + p.response_pending = true; + p.response_info.data_length = 8; + p.response_info.data[0] = fpga_reg_get(REG_DEBUG_0); + p.response_info.data[1] = fpga_reg_get(REG_DEBUG_1); + break; + + default: + p.rx_state = RX_STATE_IDLE; + p.response_pending = true; + p.response_error = true; + p.response_info.data_length = 4; + p.response_info.data[0] = 0xFF; + break; + } + } +} + +static void usb_tx_process (void) { + if (p.tx_state == TX_STATE_IDLE) { + if (p.response_pending) { + p.response_pending = false; + p.tx_state = TX_STATE_TOKEN; + p.tx_counter = 0; + p.tx_info = p.response_info; + p.tx_token = p.response_error ? ERR_TOKEN : CMP_TOKEN; + p.tx_dma_running = false; + } else if (p.packet_pending) { + p.packet_pending = false; + p.tx_state = TX_STATE_TOKEN; + p.tx_counter = 0; + p.tx_info = p.packet_info; + p.tx_token = PKT_TOKEN; + p.tx_dma_running = false; + } + } + + if (p.tx_state == TX_STATE_TOKEN) { + if (p.tx_counter == 0) { + if (usb_tx_word(p.tx_token | p.tx_info.cmd)) { + p.tx_counter += 1; + } + } + if (p.tx_counter == 1) { + if (usb_tx_word(p.tx_info.data_length + p.tx_info.dma_length)) { + p.tx_state = TX_STATE_DATA; + p.tx_counter = 0; + } + } + } + + if (p.tx_state == TX_STATE_DATA) { + if (p.tx_info.data_length > 0) { + while (usb_tx_word(p.tx_info.data[p.tx_counter])) { + p.tx_counter += 1; + if (p.tx_counter == (p.tx_info.data_length / 4)) { + p.tx_state = TX_STATE_DMA; + p.tx_counter = 0; + break; + } + } + } else { + p.tx_state = TX_STATE_DMA; + } + } + + if (p.tx_state == TX_STATE_DMA) { + if (p.tx_info.dma_length > 0) { + if (usb_dma_ready()) { + if (!p.tx_dma_running) { + p.tx_dma_running = true; + fpga_reg_set(REG_USB_DMA_ADDRESS, p.tx_info.dma_address); + fpga_reg_set(REG_USB_DMA_LENGTH, p.tx_info.dma_length); + fpga_reg_set(REG_USB_DMA_SCR, DMA_SCR_START); + } else { + p.tx_state = TX_STATE_FLUSH; + } + } + } else { + p.tx_state = TX_STATE_FLUSH; + } + } + + if (p.tx_state == TX_STATE_FLUSH) { + fpga_reg_set(REG_USB_SCR, USB_SCR_WRITE_FLUSH); + if (p.tx_info.done_callback) { + p.tx_info.done_callback(); + } + p.tx_state = TX_STATE_IDLE; + } +} + + +void usb_create_packet (usb_tx_info_t *info, usb_packet_cmd_e cmd) { + info->cmd = (uint8_t) (cmd); + info->data_length = 0; + for (int i = 0; i < 4; i++) { + info->data[i] = 0; + } + info->dma_length = 0; + info->dma_address = 0; + info->done_callback = NULL; +} + +bool usb_enqueue_packet (usb_tx_info_t *info) { + if (p.packet_pending) { + return false; + } + p.packet_pending = true; + p.packet_info = *info; + return true; +} + +bool usb_prepare_read (uint32_t *args) { + if (!p.read_ready) { + return false; + } + p.read_length = args[1]; + p.read_address = args[0]; + return true; +} + +void usb_get_read_info (uint32_t *args) { + uint32_t scr = fpga_reg_get(REG_USB_SCR); + args[0] = 0; + args[1] = 0; + if (p.rx_state == RX_STATE_DATA && p.rx_cmd == 'U') { + args[0] = p.rx_args[0] & 0xFF; + args[1] = p.rx_args[1]; + } + args[0] |= (p.read_length > 0) ? (1 << 31) : 0; + args[0] |= (scr & USB_SCR_RESET_STATE) ? (1 << 30) : 0; + args[0] |= (scr & USB_SCR_PWRSAV) ? (1 << 29) : 0; +} + +void usb_init (void) { + fpga_reg_set(REG_USB_DMA_SCR, DMA_SCR_STOP); + fpga_reg_set(REG_USB_SCR, USB_SCR_FIFO_FLUSH); + + p.rx_state = RX_STATE_IDLE; + p.tx_state = TX_STATE_IDLE; + + p.response_pending = false; + p.packet_pending = false; + + p.read_ready = true; + p.read_length = 0; + p.read_address = 0; + + usb_rx_word_counter = 0; + usb_rx_word_buffer = 0; + usb_tx_word_counter = 0; + usb_rx_cmd_counter = 0; +} + +void usb_process (void) { + uint32_t scr = fpga_reg_get(REG_USB_SCR); + if (scr & (USB_SCR_PWRSAV | USB_SCR_RESET_STATE | USB_SCR_RESET_PENDING)) { + if (p.packet_pending && p.packet_info.done_callback) { + p.packet_pending = false; + p.packet_info.done_callback(); + } + if (scr & USB_SCR_RESET_PENDING) { + if (p.tx_state != TX_STATE_IDLE && p.tx_info.done_callback) { + p.tx_info.done_callback(); + } + usb_init(); + fpga_reg_set(REG_USB_SCR, USB_SCR_RESET_ACK); + } + } else { + usb_rx_process(); + usb_tx_process(); + } +} diff --git a/sw/controller/src/usb.h b/sw/controller/src/usb.h new file mode 100644 index 0000000..2e5273b --- /dev/null +++ b/sw/controller/src/usb.h @@ -0,0 +1,36 @@ +#ifndef USB_H__ +#define USB_H__ + + +#include +#include + + +typedef enum packet_cmd { + PACKET_CMD_BUTTON_TRIGGER = 'B', + PACKET_CMD_DD_REQUEST = 'D', + PACKET_CMD_DEBUG_OUTPUT = 'U', + PACKET_CMD_ISV_OUTPUT = 'I', + PACKET_CMD_UPDATE_STATUS = 'F', +} usb_packet_cmd_e; + + +typedef struct usb_tx_info { + uint8_t cmd; + uint32_t data_length; + uint32_t data[4]; + uint32_t dma_length; + uint32_t dma_address; + void (*done_callback)(void); +} usb_tx_info_t; + + +void usb_create_packet (usb_tx_info_t *info, usb_packet_cmd_e cmd); +bool usb_enqueue_packet (usb_tx_info_t *info); +bool usb_prepare_read (uint32_t *args); +void usb_get_read_info (uint32_t *args); +void usb_init (void); +void usb_process (void); + + +#endif diff --git a/sw/controller/src/vendor.h b/sw/controller/src/vendor.h new file mode 100644 index 0000000..016fac6 --- /dev/null +++ b/sw/controller/src/vendor.h @@ -0,0 +1,24 @@ +#ifndef VENDOR_H__ +#define VENDOR_H__ + + +#include + + +typedef enum { + VENDOR_OK, + VENDOR_ERROR_ARGS, + VENDOR_ERROR_INIT, + VENDOR_ERROR_ERASE, + VENDOR_ERROR_PROGRAM, + VENDOR_ERROR_VERIFY, +} vendor_error_t; + + +uint32_t vendor_flash_size (void); +vendor_error_t vendor_backup (uint32_t address, uint32_t *length); +vendor_error_t vendor_update (uint32_t address, uint32_t length); +vendor_error_t vendor_reconfigure (void); + + +#endif diff --git a/sw/n64/Makefile b/sw/n64/Makefile deleted file mode 100644 index d70114c..0000000 --- a/sw/n64/Makefile +++ /dev/null @@ -1,70 +0,0 @@ -TOOLCHAIN = mips64-elf- -CC = $(TOOLCHAIN)gcc -CXX = $(TOOLCHAIN)g++ -OBJCOPY = $(TOOLCHAIN)objcopy -OBJDUMP = $(TOOLCHAIN)objdump -SIZE = $(TOOLCHAIN)size - -FLAGS = -march=vr4300 -mtune=vr4300 -falign-functions=32 $(USER_FLAGS) -CFLAGS = -Os -Wall -ffunction-sections -fdata-sections -ffreestanding -MMD -MP -ASFLAGS = -Wa,-I$(N64_INST)/mips64-elf/lib -LDFLAGS = -lc -nostartfiles -Wl,--gc-sections - -SRC_DIR = src -BUILD_DIR = build - -SRC_FILES = \ - startup.S \ - boot.c \ - crc32.c \ - init.c \ - main.c \ - sc64.c \ - storage.c \ - sys.c \ - syscalls.c \ - fatfs/diskio.c \ - fatfs/ff.c \ - fatfs/ffsystem.c \ - fatfs/ffunicode.c - -SRCS = $(addprefix $(SRC_DIR)/, $(SRC_FILES)) -OBJS = $(addprefix $(BUILD_DIR)/, $(notdir $(patsubst %,%.o,$(SRCS)))) -DEPS = $(OBJS:.o=.d) - -VPATH = $(SRC_DIR) $(SRC_DIR)/fatfs - -$(@info $(shell mkdir -p ./$(BUILD_DIR) &> /dev/null)) - -$(BUILD_DIR)/%.S.o: %.S - $(CC) -x assembler-with-cpp $(FLAGS) $(ASFLAGS) $(CFLAGS) -c $< -o $@ - -$(BUILD_DIR)/%.c.o: %.c - $(CC) $(FLAGS) $(CFLAGS) -c $< -o $@ - -$(BUILD_DIR)/n64boot.elf: $(OBJS) N64.ld - $(CXX) $(FLAGS) $(LDFLAGS) -TN64.ld $(OBJS) -o $@ - @$(OBJDUMP) -S $@ > $(BUILD_DIR)/n64boot.lst - -$(BUILD_DIR)/n64boot.bin: $(BUILD_DIR)/n64boot.elf - @$(OBJCOPY) -O binary $< $@ - @chksum64 $@ > /dev/null - @truncate --size=90k $@ - -$(BUILD_DIR)/n64boot.hex: $(BUILD_DIR)/n64boot.bin - @$(OBJCOPY) -I binary -O ihex $< $@ - -print_size: $(BUILD_DIR)/n64boot.elf - @echo 'Size of modules:' - @$(SIZE) -B -d -t --common $(OBJS) - @echo 'Size of n64boot:' - @$(SIZE) -B -d $< - -all: $(BUILD_DIR)/n64boot.hex print_size - -clean: - @rm -rf ./$(BUILD_DIR)/* - -.PHONY: all clean print_size - --include $(DEPS) diff --git a/sw/n64/N64.ld b/sw/n64/N64.ld deleted file mode 100644 index f69881b..0000000 --- a/sw/n64/N64.ld +++ /dev/null @@ -1,46 +0,0 @@ -MEMORY { - rdram (rwx) : org = 0x80000400, len = 4M - 0x400 - flash (r) : org = 0xB0000000, len = 90k -} - -ENTRY(entry_handler) - -__stack_size = 64k; - -SECTIONS { - .flash : { - KEEP(*(.text.rom_header)); - KEEP(*(.text.ipl3)); - __ipl3_font = LOADADDR(.flash) + 0xB70; - } > flash - - .text : { - *(.text.entry_handler) - *(.text .text.* .gnu.linkonce.t.*) - *(.rodata .rodata.* .gnu.linkonce.r.*) - *(.data .data.* .gnu.linkonce.d.*) - _gp = . + 0x8000; - *(.sdata .sdata.* .gnu.linkonce.s.*) - *(.lit8 .lit4) - . = ALIGN(4); - } > rdram AT > flash - - .bss : { - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon .scommon.*) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - } > rdram - - _sheap = .; - . = ORIGIN(rdram) + LENGTH(rdram) - __stack_size; - _eheap = .; - - . += __stack_size; - _sp = .; - - /DISCARD/ : { - *(.MIPS.*) - } -} diff --git a/sw/n64/src/fatfs/diskio.c b/sw/n64/src/fatfs/diskio.c deleted file mode 100644 index a14b7bf..0000000 --- a/sw/n64/src/fatfs/diskio.c +++ /dev/null @@ -1,37 +0,0 @@ -#include "ff.h" -#include "diskio.h" -#include "../sc64.h" - -DSTATUS disk_status (BYTE pdrv) { - return 0; -} - -DSTATUS disk_initialize (BYTE pdrv) { - return 0; -} - -DRESULT disk_read (BYTE pdrv, BYTE *buff, LBA_t sector, UINT count) { - if (pdrv == 0) { - return RES_NOTRDY; - } else if (pdrv == 1) { - sc64_debug_fsd_read(buff, sector, count); - return RES_OK; - } - return RES_PARERR; -} - -#if FF_FS_READONLY == 0 -DRESULT disk_write (BYTE pdrv, const BYTE *buff, LBA_t sector, UINT count) { - if (pdrv == 0) { - return RES_NOTRDY; - } else if (pdrv == 1) { - sc64_debug_fsd_write(buff, sector, count); - return RES_OK; - } - return RES_PARERR; -} -#endif - -DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void *buff) { - return RES_PARERR; -} diff --git a/sw/n64/src/init.c b/sw/n64/src/init.c deleted file mode 100644 index 1f1d31b..0000000 --- a/sw/n64/src/init.c +++ /dev/null @@ -1,12 +0,0 @@ -#include "sys.h" -#include "sc64.h" - - -void init (void) { - uint32_t pifram = si_io_read((io32_t *) (&PIFRAM[0x3C])); - si_io_write((io32_t *) (&PIFRAM[0x3C]), pifram | 0x08); - - sc64_init(); - - LOG_I("Initialized\r\n"); -} diff --git a/sw/n64/src/main.c b/sw/n64/src/main.c deleted file mode 100644 index cc429a9..0000000 --- a/sw/n64/src/main.c +++ /dev/null @@ -1,71 +0,0 @@ -#include "boot.h" -#include "sc64.h" -#include "storage.h" - - -void main (void) { - boot_info_t boot_info; - sc64_info_t sc64_info; - - boot_info.reset_type = OS_INFO->reset_type; - - sc64_get_info(&sc64_info); - - LOG_I("Bootloader version: %.32s\r\n", sc64_info.bootloader_version); - - switch (sc64_info.boot_mode) { - case BOOT_MODE_MENU: - LOG_I("Running menu from SD card\r\n"); - storage_run_menu(STORAGE_BACKEND_SD, &boot_info, &sc64_info); - break; - - case BOOT_MODE_ROM: - LOG_I("Running ROM from SDRAM\r\n"); - boot_info.device_type = BOOT_DEVICE_TYPE_ROM; - break; - - case BOOT_MODE_DDIPL: - LOG_I("Running DDIPL from SDRAM\r\n"); - boot_info.device_type = BOOT_DEVICE_TYPE_DD; - break; - - case BOOT_MODE_DIRECT: - LOG_I("Running bootloader from SDRAM - running menu from FSD\r\n"); - storage_run_menu(STORAGE_BACKEND_USB, &boot_info, &sc64_info); - break; - - default: - LOG_E("Unknown boot mode! - %d\r\n", sc64_info.boot_mode); - while (1); - } - - if (sc64_info.tv_type != TV_TYPE_UNKNOWN) { - boot_info.tv_type = sc64_info.tv_type; - LOG_I("Using provided TV type: %d\r\n", boot_info.tv_type); - } else { - if (boot_get_tv_type(&boot_info)) { - LOG_I("Using TV type guessed from ROM header: %d\r\n", boot_info.tv_type); - } else { - boot_info.tv_type = OS_INFO->tv_type; - LOG_I("Using console TV type: %d\r\n", boot_info.tv_type); - } - } - - if (sc64_info.cic_seed != 0xFFFF) { - boot_info.cic_seed = sc64_info.cic_seed & 0xFF; - boot_info.version = (sc64_info.cic_seed >> 8) & 0x01; - LOG_I("Using provided CIC seed and version: 0x%02X.%d\r\n", boot_info.cic_seed, boot_info.version); - } else { - if (boot_get_cic_seed_version(&boot_info)) { - LOG_I("Using CIC seed and version guessed from IPL3: 0x%02X.%d\r\n", boot_info.cic_seed, boot_info.version); - } else { - boot_info.cic_seed = 0x3F; - boot_info.version = 0; - LOG_I("Using 6102/7101 CIC seed and version: 0x%02X.%d\r\n", boot_info.cic_seed, boot_info.version); - } - } - - LOG_I("Booting IPL3\033[0m\r\n\r\n"); - - boot(&boot_info); -} diff --git a/sw/n64/src/sc64.c b/sw/n64/src/sc64.c deleted file mode 100644 index e04bc76..0000000 --- a/sw/n64/src/sc64.c +++ /dev/null @@ -1,203 +0,0 @@ -#include "sc64.h" - - -extern char header_text_info __attribute__((section(".data"))); - - -bool sc64_check_presence (void) { - uint32_t version = pi_io_read(&SC64->VERSION); - return (version == SC64_VERSION_2); -} - -void sc64_wait_cpu_ready (void) { - uint32_t sr; - do { - sr = pi_io_read(&SC64->SR_CMD); - } while (!(sr & SC64_SR_CPU_READY)); -} - -bool sc64_wait_cpu_busy (void) { - uint32_t sr; - do { - sr = pi_io_read(&SC64->SR_CMD); - } while (sr & SC64_SR_CPU_BUSY); - return sr & SC64_SR_CMD_ERROR; -} - -bool sc64_perform_cmd (uint8_t cmd, uint32_t *args, uint32_t *result) { - if (args != NULL) { - pi_io_write(&SC64->DATA[0], args[0]); - pi_io_write(&SC64->DATA[1], args[1]); - } - pi_io_write(&SC64->SR_CMD, ((uint32_t) (cmd)) & 0xFF); - bool error = sc64_wait_cpu_busy(); - if (result != NULL) { - result[0] = pi_io_read(&SC64->DATA[0]); - result[1] = pi_io_read(&SC64->DATA[1]); - } - return error; -} - -uint32_t sc64_get_config (cfg_id_t id) { - uint32_t args[2] = { id, 0 }; - uint32_t result[2]; - sc64_perform_cmd(SC64_CMD_QUERY, args, result); - return result[1]; -} - -void sc64_set_config (cfg_id_t id, uint32_t value) { - uint32_t args[2] = { id, value }; - sc64_perform_cmd(SC64_CMD_CONFIG, args, NULL); -} - -void sc64_get_info (sc64_info_t *info) { - io32_t *src = (io32_t *) UNCACHED(&header_text_info); - uint32_t *dst = (uint32_t *) info->bootloader_version; - - bool sdram_switched = sc64_get_config(CFG_ID_SDRAM_SWITCH); - - if (sdram_switched) { - sc64_set_config(CFG_ID_SDRAM_SWITCH, false); - } - - for (int i = 0; i < sizeof(info->bootloader_version); i += sizeof(uint32_t)) { - *dst++ = pi_io_read(src++); - } - - if (sdram_switched) { - sc64_set_config(CFG_ID_SDRAM_SWITCH, true); - } - - info->dd_enabled = (bool) sc64_get_config(CFG_ID_DD_ENABLE); - info->save_type = (save_type_t) sc64_get_config(CFG_ID_SAVE_TYPE); - info->cic_seed = (uint16_t) sc64_get_config(CFG_ID_CIC_SEED); - info->tv_type = (tv_type_t) sc64_get_config(CFG_ID_TV_TYPE); - info->save_location = (io32_t *) (0x10000000 | sc64_get_config(CFG_ID_SAVE_OFFEST)); - info->ddipl_location = (io32_t *) (0x10000000 | sc64_get_config(CFG_ID_DDIPL_OFFEST)); - info->boot_mode = (boot_mode_t) sc64_get_config(CFG_ID_BOOT_MODE); -} - -void sc64_wait_usb_rx_ready (uint32_t *type, uint32_t *length) { - uint32_t result[2]; - do { - sc64_perform_cmd(SC64_CMD_DEBUG_RX_READY, NULL, result); - } while (result[0] == 0 && result[1] == 0); - *type = result[0]; - *length = result[1]; -} - -void sc64_wait_usb_rx_busy (void) { - uint32_t result[2]; - do { - sc64_perform_cmd(SC64_CMD_DEBUG_RX_BUSY, NULL, result); - } while (result[0]); -} - -void sc64_usb_rx_data (io32_t *address, uint32_t length) { - uint32_t args[2] = { (uint32_t) (address), ALIGN(length, 2) }; - sc64_perform_cmd(SC64_CMD_DEBUG_RX_DATA, args, NULL); -} - -void sc64_wait_usb_tx_ready (void) { - uint32_t result[2]; - do { - sc64_perform_cmd(SC64_CMD_DEBUG_TX_READY, NULL, result); - } while (!result[0]); -} - -void sc64_usb_tx_data (io32_t *address, uint32_t length) { - uint32_t args[2] = { (uint32_t) (address), ALIGN(length, 2) }; - sc64_perform_cmd(SC64_CMD_DEBUG_TX_DATA, args, NULL); -} - -void sc64_debug_write (uint8_t type, const void *data, uint32_t len) { - char *dma = "DMA@"; - char *cmp = "CMPH"; - - io32_t *sdram = (io32_t *) (SC64_DEBUG_WRITE_ADDRESS); - - uint32_t *src = (uint32_t *) (data); - io32_t *dst = sdram; - - uint32_t copy_length = ALIGN(len, 4); - - sc64_wait_usb_tx_ready(); - - bool writable = sc64_get_config(CFG_ID_SDRAM_WRITABLE); - bool sdram_switched = sc64_get_config(CFG_ID_SDRAM_SWITCH); - - if (!writable) { - sc64_set_config(CFG_ID_SDRAM_WRITABLE, true); - } - if (!sdram_switched) { - sc64_set_config(CFG_ID_SDRAM_SWITCH, true); - } - - pi_io_write(dst++, *((uint32_t *) (dma))); - pi_io_write(dst++, (type << 24) | len); - - while (src < ((uint32_t *) (data + copy_length))) { - pi_io_write(dst++, *src++); - if (dst >= (io32_t *) ((void *) (sdram) + SC64_DEBUG_MAX_SIZE)) { - sc64_usb_tx_data(sdram, (dst - sdram) * sizeof(uint32_t)); - sc64_wait_usb_tx_ready(); - dst = sdram; - } - } - - pi_io_write(dst++, *((uint32_t *) (cmp))); - - if (!writable) { - sc64_set_config(CFG_ID_SDRAM_WRITABLE, false); - } - if (!sdram_switched) { - sc64_set_config(CFG_ID_SDRAM_SWITCH, false); - } - - sc64_usb_tx_data(sdram, (dst - sdram) * sizeof(uint32_t)); -} - -void sc64_debug_fsd_read (const void *data, uint32_t sector, uint32_t count) { - uint32_t type; - uint32_t length; - - io32_t *sdram = (io32_t *) (SC64_DEBUG_READ_ADDRESS); - - io32_t *src = sdram; - uint32_t *dst = (uint32_t *) (data); - - uint32_t read_length = count * 512; - - sc64_debug_write(SC64_DEBUG_ID_FSD_SECTOR, §or, 4); - sc64_debug_write(SC64_DEBUG_ID_FSD_READ, &read_length, 4); - sc64_wait_usb_rx_ready(&type, &length); - sc64_usb_rx_data(sdram, length); - sc64_wait_usb_rx_busy(); - - uint32_t copy_length = ALIGN(length, 4); - - bool sdram_switched = sc64_get_config(CFG_ID_SDRAM_SWITCH); - - if (!sdram_switched) { - sc64_set_config(CFG_ID_SDRAM_SWITCH, true); - } - - for (int i = 0; i < copy_length; i += 4) { - *dst++ = pi_io_read(src++); - } - - if (!sdram_switched) { - sc64_set_config(CFG_ID_SDRAM_SWITCH, false); - } -} - -void sc64_debug_fsd_write (const void *data, uint32_t sector, uint32_t count) { - sc64_debug_write(SC64_DEBUG_ID_FSD_SECTOR, §or, 4); - sc64_debug_write(SC64_DEBUG_ID_FSD_WRITE, data, count * 512); -} - -void sc64_init (void) { - while (!sc64_check_presence()); - sc64_wait_cpu_ready(); - sc64_set_config(CFG_ID_SDRAM_SWITCH, true); -} diff --git a/sw/n64/src/sc64.h b/sw/n64/src/sc64.h deleted file mode 100644 index b9ff847..0000000 --- a/sw/n64/src/sc64.h +++ /dev/null @@ -1,126 +0,0 @@ -#ifndef SC64_H__ -#define SC64_H__ - - -#include -#include -#include -#include "sys.h" - - -#ifdef DEBUG -#include -#define LOG_I(args...) {iprintf("\033[32m" args);} -#define LOG_E(args...) {iprintf("\033[31m" args);} -#else -#define LOG_I(args...) -#define LOG_E(args...) -#define assert(expr) -#endif - - -typedef struct { - io32_t SR_CMD; - io32_t DATA[2]; - io32_t VERSION; -} sc64_regs_t; - -#define SC64_BASE (0x1FFF0000) -#define SC64 ((sc64_regs_t *) SC64_BASE) - -#define SC64_SR_CMD_ERROR (1 << 28) -#define SC64_SR_CPU_BUSY (1 << 30) -#define SC64_SR_CPU_READY (1 << 31) - -#define SC64_CMD_CONFIG ('C') -#define SC64_CMD_QUERY ('Q') -#define SC64_CMD_DEBUG_RX_DATA ('E') -#define SC64_CMD_DEBUG_RX_READY ('A') -#define SC64_CMD_DEBUG_RX_BUSY ('F') -#define SC64_CMD_DEBUG_TX_DATA ('D') -#define SC64_CMD_DEBUG_TX_READY ('S') - -#define SC64_VERSION_2 (0x53437632) - -#define SC64_DEBUG_WRITE_ADDRESS (0x13BD8000UL) -#define SC64_DEBUG_READ_ADDRESS (0x13BD0000UL) -#define SC64_DEBUG_MAX_SIZE (32 * 1024) - -#define SC64_DEBUG_ID_TEXT (0x01) -#define SC64_DEBUG_ID_FSD_READ (0xF1) -#define SC64_DEBUG_ID_FSD_WRITE (0xF2) -#define SC64_DEBUG_ID_FSD_SECTOR (0xF3) - - -typedef enum { - CFG_ID_SCR, - CFG_ID_SDRAM_SWITCH, - CFG_ID_SDRAM_WRITABLE, - CFG_ID_DD_ENABLE, - CFG_ID_SAVE_TYPE, - CFG_ID_CIC_SEED, - CFG_ID_TV_TYPE, - CFG_ID_SAVE_OFFEST, - CFG_ID_DDIPL_OFFEST, - CFG_ID_BOOT_MODE, - CFG_ID_FLASH_SIZE, - CFG_ID_FLASH_READ, - CFG_ID_FLASH_PROGRAM, - CFG_ID_RECONFIGURE, -} cfg_id_t; - -typedef enum { - SAVE_TYPE_NONE = 0, - SAVE_TYPE_EEPROM_4K = 1, - SAVE_TYPE_EEPROM_16K = 2, - SAVE_TYPE_SRAM = 3, - SAVE_TYPE_FLASHRAM = 4, - SAVE_TYPE_SRAM_BANKED = 5, - SAVE_TYPE_FLASHRAM_PKST2 = 6, -} save_type_t; - -typedef enum { - TV_TYPE_PAL = 0, - TV_TYPE_NTSC = 1, - TV_TYPE_MPAL = 2, - TV_TYPE_UNKNOWN = 3, -} tv_type_t; - -typedef enum { - BOOT_MODE_MENU = 0, - BOOT_MODE_ROM = 1, - BOOT_MODE_DDIPL = 2, - BOOT_MODE_DIRECT = 3, -} boot_mode_t; - -typedef struct { - bool dd_enabled; - save_type_t save_type; - uint16_t cic_seed; - tv_type_t tv_type; - io32_t *save_location; - io32_t *ddipl_location; - boot_mode_t boot_mode; - char bootloader_version[32]; -} sc64_info_t; - - -bool sc64_check_presence (void); -void sc64_wait_cpu_ready (void); -bool sc64_wait_cpu_busy (void); -bool sc64_perform_cmd (uint8_t cmd, uint32_t *args, uint32_t *result); -uint32_t sc64_get_config (cfg_id_t id); -void sc64_set_config (cfg_id_t id, uint32_t value); -void sc64_get_info (sc64_info_t *info); -void sc64_wait_usb_rx_ready (uint32_t *type, uint32_t *length); -void sc64_wait_usb_rx_busy (void); -void sc64_usb_rx_data (io32_t *address, uint32_t length); -void sc64_wait_usb_tx_ready (void); -void sc64_usb_tx_data (io32_t *address, uint32_t length); -void sc64_debug_write (uint8_t type, const void *data, uint32_t len); -void sc64_debug_fsd_read (const void *data, uint32_t sector, uint32_t count); -void sc64_debug_fsd_write (const void *data, uint32_t sector, uint32_t count); -void sc64_init (void); - - -#endif diff --git a/sw/n64/src/storage.c b/sw/n64/src/storage.c deleted file mode 100644 index ff22ace..0000000 --- a/sw/n64/src/storage.c +++ /dev/null @@ -1,64 +0,0 @@ -#include "storage.h" -#include "sc64.h" -#include "fatfs/ff.h" - - -static const char *fatfs_error_codes[] = { - "(0) Succeeded", - "(1) A hard error occurred in the low level disk I/O layer", - "(2) Assertion failed", - "(3) The physical drive cannot work", - "(4) Could not find the file", - "(5) Could not find the path", - "(6) The path name format is invalid", - "(7) Access denied due to prohibited access or directory full", - "(8) Access denied due to prohibited access", - "(9) The file/directory object is invalid", - "(10) The physical drive is write protected", - "(11) The logical drive number is invalid", - "(12) The volume has no work area", - "(13) There is no valid FAT volume", - "(14) The f_mkfs() aborted due to any problem", - "(15) Could not get a grant to access the volume within defined period", - "(16) The operation is rejected according to the file sharing policy", - "(17) LFN working buffer could not be allocated", - "(18) Number of open files > FF_FS_LOCK", - "(19) Given parameter is invalid", -}; - - -#define FF_CHECK(x) { \ - FRESULT fatfs_result = x; \ - if (fatfs_result) { \ - LOG_E("fatfs error \"%s\" at [%s:%d] in expr: %s\r\n", fatfs_error_codes[fatfs_result], __FILE__, __LINE__, #x); \ - while (1); \ - } \ -} - - -void storage_run_menu (storage_backend_t storage_backend, boot_info_t *boot_info, sc64_info_t *sc64_info) { - FATFS fs; - FIL fil; - - if (storage_backend == STORAGE_BACKEND_SD) { - FF_CHECK(f_mount(&fs, "0:", 1)); - FF_CHECK(f_chdrive("0:")); - } else if (storage_backend == STORAGE_BACKEND_USB) { - FF_CHECK(f_mount(&fs, "1:", 1)); - FF_CHECK(f_chdrive("1:")); - } else { - LOG_E("Unknown storage backend %d\r\n", storage_backend); - while (1); - } - - FF_CHECK(f_open(&fil, "sc64menu.elf", FA_READ)); - - // TODO: Implement ELF loader here - - FF_CHECK(f_close(&fil)); - - // TODO: Execute ELF here - // menu(&boot_info, &sc64_info); - - boot_info->device_type = BOOT_DEVICE_TYPE_ROM; -} diff --git a/sw/n64/src/storage.h b/sw/n64/src/storage.h deleted file mode 100644 index 01e5bd0..0000000 --- a/sw/n64/src/storage.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef STORAGE_H__ -#define STORAGE_H__ - - -#include "boot.h" -#include "sc64.h" - - -typedef enum { - STORAGE_BACKEND_SD = 0, - STORAGE_BACKEND_USB = 1, -} storage_backend_t; - - -void storage_run_menu (storage_backend_t storage_backend, boot_info_t *boot_info, sc64_info_t *sc64_info); - - -#endif diff --git a/sw/n64/src/sys.c b/sw/n64/src/sys.c deleted file mode 100644 index 6d9f860..0000000 --- a/sw/n64/src/sys.c +++ /dev/null @@ -1,71 +0,0 @@ -#include "sys.h" - - -void c0_set_status (uint32_t status) { - asm volatile ( - ".set noat \n" - ".set noreorder \n" - "mtc0 %[status], $12 \n" - "nop \n" - : - : [status] "r" (status) - ); -} - -uint32_t c0_get_count (void) { - uint32_t count; - asm volatile ( - ".set noat \n" - ".set noreorder \n" - "mfc0 %[count], $9 \n" - "nop \n" - : [count] "=r" (count) - ); - return count; -} - -void wait_ms (uint32_t ms) { - uint32_t start = c0_get_count(); - while (c0_get_count() - start < (ms * ((CPU_FREQUENCY / 2) / 1000))); -} - -uint32_t io_read (io32_t *address) { - io32_t *uncached = UNCACHED(address); - asm volatile ("" : : : "memory"); - uint32_t value = *uncached; - asm volatile ("" : : : "memory"); - return value; -} - -void io_write (io32_t *address, uint32_t value) { - io32_t *uncached = UNCACHED(address); - asm volatile ("" : : : "memory"); - *uncached = value; - asm volatile ("" : : : "memory"); -} - -uint32_t pi_busy (void) { - return (io_read(&PI->SR) & (PI_SR_IO_BUSY | PI_SR_DMA_BUSY)); -} - -uint32_t pi_io_read (io32_t *address) { - return io_read(address); -} - -void pi_io_write (io32_t *address, uint32_t value) { - io_write(address, value); - while (pi_busy()); -} - -uint32_t si_busy (void) { - return (io_read(&SI->SR) & (SI_SR_IO_BUSY | SI_SR_DMA_BUSY)); -} - -uint32_t si_io_read (io32_t *address) { - return io_read(address); -} - -void si_io_write (io32_t *address, uint32_t value) { - io_write(address, value); - while (si_busy()); -} diff --git a/sw/n64/src/syscalls.c b/sw/n64/src/syscalls.c deleted file mode 100644 index 7cb1b25..0000000 --- a/sw/n64/src/syscalls.c +++ /dev/null @@ -1,71 +0,0 @@ -#include -#include -#include -#include -#include -#include "sc64.h" - - -extern char _sheap __attribute__((section(".data"))); -extern char _eheap __attribute__((section(".data"))); - - -int _close_r (struct _reent *prt, int fd) { - errno = ENOSYS; - return -1; -} - -int _fstat_r (struct _reent *prt, int fd, struct stat *pstat) { - errno = ENOSYS; - return -1; -} - -int _isatty_r (struct _reent *prt, int fd) { - if (fd == STDIN_FILENO || fd == STDOUT_FILENO || fd == STDERR_FILENO){ - return 1; - } - errno = EBADF; - return 0; -} - -off_t _lseek_r (struct _reent *prt, int fd, off_t pos, int whence) { - errno = ENOSYS; - return -1; -} - -ssize_t _read_r (struct _reent *prt, int fd, void *buf, size_t cnt) { - errno = ENOSYS; - return -1; -} - -caddr_t _sbrk_r (struct _reent *prt, ptrdiff_t incr) { - static char *curr_heap_end = &_sheap; - char *prev_heap_end; - - prev_heap_end = curr_heap_end; - curr_heap_end += incr; - - if (curr_heap_end > &_eheap) { - errno = ENOMEM; - return (caddr_t) -1; - } - - return (caddr_t) prev_heap_end; -} - -ssize_t _write_r (struct _reent *prt, int fd, const void *buf, size_t cnt) { - if (fd == STDIN_FILENO) { - errno = EBADF; - return -1; - } else if (fd == STDOUT_FILENO || fd == STDERR_FILENO) { - sc64_debug_write(SC64_DEBUG_ID_TEXT, buf, cnt); - return cnt; - } - errno = ENOSYS; - return -1; -} - -void __assert_func (const char *file, int line, const char *func, const char *failedexpr) { - LOG_E("\r\nassertion \"%s\" failed: file \"%s\", line %d%s%s\r\n", failedexpr, file, line, func ? ", function: " : "", func ? func : ""); - while (1); -} diff --git a/sw/pc/.gitignore b/sw/pc/.gitignore index a94076f..baaf232 100644 --- a/sw/pc/.gitignore +++ b/sw/pc/.gitignore @@ -1,15 +1,9 @@ -/__pycache__ -/backup -/roms -/saves -*.bak +**/__pycache__ *.bin -*.dat -*.data *.eep *.fla -*.img *.n64 *.srm +*.upd *.v64 *.z64 diff --git a/sw/pc/dd64.py b/sw/pc/dd64.py new file mode 100755 index 0000000..d16aac3 --- /dev/null +++ b/sw/pc/dd64.py @@ -0,0 +1,236 @@ +#!/usr/bin/env python3 + +import sys +from io import BufferedReader +from typing import Optional + + + +class BadBlockError(Exception): + pass + + +class DD64Image: + __DISK_HEADS = 2 + __DISK_TRACKS = 1175 + __DISK_BLOCKS_PER_TRACK = 2 + __DISK_SECTORS_PER_BLOCK = 85 + __DISK_BAD_TRACKS_PER_ZONE = 12 + __DISK_SYSTEM_SECTOR_SIZE = 232 + __DISK_ZONES = [ + (0, 232, 158, 0), + (0, 216, 158, 158), + (0, 208, 149, 316), + (0, 192, 149, 465), + (0, 176, 149, 614), + (0, 160, 149, 763), + (0, 144, 149, 912), + (0, 128, 114, 1061), + (1, 216, 158, 157), + (1, 208, 158, 315), + (1, 192, 149, 464), + (1, 176, 149, 613), + (1, 160, 149, 762), + (1, 144, 149, 911), + (1, 128, 149, 1060), + (1, 112, 114, 1174), + ] + __DISK_VZONE_TO_PZONE = [ + [0, 1, 2, 9, 8, 3, 4, 5, 6, 7, 15, 14, 13, 12, 11, 10], + [0, 1, 2, 3, 10, 9, 8, 4, 5, 6, 7, 15, 14, 13, 12, 11], + [0, 1, 2, 3, 4, 11, 10, 9, 8, 5, 6, 7, 15, 14, 13, 12], + [0, 1, 2, 3, 4, 5, 12, 11, 10, 9, 8, 6, 7, 15, 14, 13], + [0, 1, 2, 3, 4, 5, 6, 13, 12, 11, 10, 9, 8, 7, 15, 14], + [0, 1, 2, 3, 4, 5, 6, 7, 14, 13, 12, 11, 10, 9, 8, 15], + [0, 1, 2, 3, 4, 5, 6, 7, 15, 14, 13, 12, 11, 10, 9, 8], + ] + __DISK_DRIVE_TYPES = [( + 'development', + 192, + [11, 10, 3, 2], + [0, 1, 8, 9, 16, 17, 18, 19, 20, 21, 22, 23], + ), ( + 'retail', + 232, + [9, 8, 1, 0], + [2, 3, 10, 11, 12, 16, 17, 18, 19, 20, 21, 22, 23], + )] + + __file: Optional[BufferedReader] + __drive_type: Optional[str] + __block_info_table: list[tuple[int, int]] + loaded: bool = False + + def __init__(self) -> None: + self.__file = None + self.__drive_type = None + block_info_table_length = self.__DISK_HEADS * self.__DISK_TRACKS * self.__DISK_BLOCKS_PER_TRACK + self.__block_info_table = [None] * block_info_table_length + + def __del__(self) -> None: + self.unload() + + def __check_system_block(self, lba: int, sector_size: int, check_disk_type: bool) -> tuple[bool, bytes]: + self.__file.seek(lba * self.__DISK_SYSTEM_SECTOR_SIZE * self.__DISK_SECTORS_PER_BLOCK) + system_block_data = self.__file.read(sector_size * self.__DISK_SECTORS_PER_BLOCK) + system_data = system_block_data[:sector_size] + for sector in range(1, self.__DISK_SECTORS_PER_BLOCK): + sector_data = system_block_data[(sector * sector_size):][:sector_size] + if (system_data != sector_data): + return (False, None) + if (check_disk_type): + if (system_data[4] != 0x10): + return (False, None) + if ((system_data[5] & 0xF0) != 0x10): + return (False, None) + return (True, system_data) + + def __parse_disk(self) -> None: + disk_system_data = None + disk_id_data = None + disk_bad_lbas = [] + + drive_index = 0 + while (disk_system_data == None) and (drive_index < len(self.__DISK_DRIVE_TYPES)): + (drive_type, system_sector_size, system_data_lbas, bad_lbas) = self.__DISK_DRIVE_TYPES[drive_index] + disk_bad_lbas.clear() + disk_bad_lbas.extend(bad_lbas) + for system_lba in system_data_lbas: + (valid, system_data) = self.__check_system_block(system_lba, system_sector_size, check_disk_type=True) + if (valid): + self.__drive_type = drive_type + disk_system_data = system_data + else: + disk_bad_lbas.append(system_lba) + drive_index += 1 + + for id_lba in [15, 14]: + (valid, id_data) = self.__check_system_block(id_lba, self.__DISK_SYSTEM_SECTOR_SIZE, check_disk_type=False) + if (valid): + disk_id_data = id_data + else: + disk_bad_lbas.append(id_lba) + + if not (disk_system_data and disk_id_data): + raise ValueError('Provided 64DD disk file is not valid') + + disk_zone_bad_tracks = [] + + for zone in range(len(self.__DISK_ZONES)): + zone_bad_tracks = [] + start = 0 if zone == 0 else system_data[0x07 + zone] + stop = system_data[0x07 + zone + 1] + for offset in range(start, stop): + zone_bad_tracks.append(system_data[0x20 + offset]) + for ignored_track in range(self.__DISK_BAD_TRACKS_PER_ZONE - len(zone_bad_tracks)): + zone_bad_tracks.append(self.__DISK_ZONES[zone][2] - ignored_track - 1) + disk_zone_bad_tracks.append(zone_bad_tracks) + + disk_type = disk_system_data[5] & 0x0F + + current_lba = 0 + starting_block = 0 + disk_file_offset = 0 + + for zone in self.__DISK_VZONE_TO_PZONE[disk_type]: + (head, sector_size, tracks, track) = self.__DISK_ZONES[zone] + + for zone_track in range(tracks): + current_zone_track = ( + (tracks - 1) - zone_track) if head else zone_track + + if (current_zone_track in disk_zone_bad_tracks[zone]): + track += (-1) if head else 1 + continue + + for block in range(self.__DISK_BLOCKS_PER_TRACK): + index = (track << 2) | (head << 1) | (starting_block ^ block) + if (current_lba not in disk_bad_lbas): + self.__block_info_table[index] = (disk_file_offset, sector_size * self.__DISK_SECTORS_PER_BLOCK) + else: + self.__block_info_table[index] = None + disk_file_offset += sector_size * self.__DISK_SECTORS_PER_BLOCK + current_lba += 1 + + track += (-1) if head else 1 + starting_block ^= 1 + + def __check_track_head_block(self, track: int, head: int, block: int) -> None: + if (track < 0 or track >= self.__DISK_TRACKS): + raise ValueError('Track outside of possible range') + if (head < 0 or head >= self.__DISK_HEADS): + raise ValueError('Head outside of possible range') + if (block < 0 or block >= self.__DISK_BLOCKS_PER_TRACK): + raise ValueError('Block outside of possible range') + + def __get_table_index(self, track: int, head: int, block: int) -> int: + return (track << 2) | (head << 1) | (block) + + def __get_block_info(self, track: int, head: int, block: int) -> Optional[tuple[int, int]]: + if (self.__file.closed): + return None + self.__check_track_head_block(track, head, block) + index = self.__get_table_index(track, head, block) + return self.__block_info_table[index] + + def load(self, path: str) -> None: + self.unload() + self.__file = open(path, 'rb+') + self.__parse_disk() + self.loaded = True + + def unload(self) -> None: + self.loaded = False + if (self.__file != None and not self.__file.closed): + self.__file.close() + self.__drive_type = None + + def get_block_info_table(self) -> list[tuple[int, int]]: + return self.__block_info_table + + def get_drive_type(self) -> str: + return self.__drive_type + + def read_block(self, track: int, head: int, block: int) -> bytes: + info = self.__get_block_info(track, head, block) + if (info == None): + raise BadBlockError + (offset, block_size) = info + self.__file.seek(offset) + return self.__file.read(block_size) + + def write_block(self, track: int, head: int, block: int, data: bytes) -> None: + info = self.__get_block_info(track, head, block) + if (info == None): + raise BadBlockError + (offset, block_size) = info + if (len(data) != block_size): + raise ValueError(f'Provided data block size is different than expected ({len(data)} != {block_size})') + self.__file.seek(offset) + self.__file.write(data) + + + +if __name__ == '__main__': + id_lba_locations = [ + (7, 0, 1), + (7, 0, 0) + ] + if (len(sys.argv) >= 2): + dd = DD64Image() + dd.load(sys.argv[1]) + print(dd.get_drive_type()) + for (track, head, block) in id_lba_locations: + try: + print(dd.read_block(track, head, block)[:4]) + except BadBlockError: + print(f'Bad ID block [track: {track}, head: {head}, block: {block}]') + if (len(sys.argv) >= 3): + with open(sys.argv[2], 'wb') as f: + block_info_table = dd.get_block_info_table() + for block in block_info_table: + offset = 0xFFFFFFFF if block == None else block[0] + f.write(offset.to_bytes(4, byteorder='big')) + dd.unload() + else: + print(f'[{sys.argv[0]}]: Expected disk image path as first argument') diff --git a/sw/pc/requirements.txt b/sw/pc/requirements.txt index decab53..c3f0da9 100644 --- a/sw/pc/requirements.txt +++ b/sw/pc/requirements.txt @@ -1,2 +1,2 @@ -progressbar2==3.55.0 +Pillow==9.2.0 pyserial==3.5 diff --git a/sw/pc/sc64.py b/sw/pc/sc64.py old mode 100644 new mode 100755 index 93eece2..c8ad058 --- a/sw/pc/sc64.py +++ b/sw/pc/sc64.py @@ -1,162 +1,52 @@ #!/usr/bin/env python3 -from io import TextIOWrapper -from serial import Serial, SerialException -from serial.tools import list_ports import argparse -import filecmp import os -import progressbar -import re -import struct +import queue +import serial import sys import time +from datetime import datetime +from dd64 import BadBlockError, DD64Image +from enum import Enum, IntEnum +from serial.tools import list_ports +from threading import Thread +from typing import Callable, Optional +from PIL import Image -class SC64Exception(Exception): +class ConnectionException(Exception): pass +class SC64Serial: + __disconnect = False + __serial: Optional[serial.Serial] = None + __thread_read = None + __thread_write = None + __queue_output = queue.Queue() + __queue_input = queue.Queue() + __queue_packet = queue.Queue() -class SC64: - __CFG_ID_DD_ENABLE = 3 - __CFG_ID_SAVE_TYPE = 4 - __CFG_ID_CIC_SEED = 5 - __CFG_ID_TV_TYPE = 6 - __CFG_ID_SAVE_OFFEST = 7 - __CFG_ID_DDIPL_OFFEST = 8 - __CFG_ID_BOOT_MODE = 9 - __CFG_ID_FLASH_SIZE = 10 - __CFG_ID_FLASH_READ = 11 - __CFG_ID_FLASH_PROGRAM = 12 - __CFG_ID_RECONFIGURE = 13 - __CFG_ID_DD_SETTING = 14 - __CFG_ID_DD_THB_TABLE_OFFSET = 15 + __VID = 0x0403 + __PID = 0x6014 - __SC64_VERSION_V2 = 0x53437632 - - __UPDATE_OFFSET = 0x03B60000 - - __CHUNK_SIZE = 256 * 1024 - - __MIN_ROM_LENGTH = 0x101000 - __DDIPL_ROM_LENGTH = 0x400000 - - __DEBUG_ID_TEXT = 0x01 - __DEBUG_ID_FSD_READ = 0xF1 - __DEBUG_ID_FSD_WRITE = 0xF2 - __DEBUG_ID_FSD_SECTOR = 0xF3 - __DEBUG_ID_DD_BLOCK = 0xF5 - - __DD_SETTING_DISK_EJECTED = 0 - __DD_SETTING_DISK_INSERTED = 1 - __DD_SETTING_DISK_CHANGED = 2 - __DD_SETTING_DRIVE_RETAIL = 3 - __DD_SETTING_DRIVE_DEVELOPMENT = 4 - __DD_SETTING_SET_BLOCK_READY = 5 + __CHUNK_SIZE = (64 * 1024) def __init__(self) -> None: - self.__serial = None - self.__progress_init = None - self.__progress_value = None - self.__progress_finish = None - self.__fsd_file = None - self.__disk_file = None - self.__disk_lba_table = [] - self.__find_sc64() - - - def __del__(self) -> None: - if (self.__serial): - self.__serial.close() - if (self.__fsd_file): - self.__fsd_file.close() - - - def __set_progress_init(self, value: int, label: str) -> None: - if (self.__progress_init != None): - self.__progress_init(value, label) - - - def __set_progress_value(self, value: int) -> None: - if (self.__progress_value != None): - self.__progress_value(value) - - - def __set_progress_finish(self) -> None: - if (self.__progress_finish != None): - self.__progress_finish() - - - def __align(self, value: int, align: int) -> int: - return (value + (align - 1)) & ~(align - 1) - - - def __escape(self, data: bytes) -> bytes: - return re.sub(b"\x1B", b"\x1B\x1B", data) - - - def reset_link(self) -> None: - self.__serial.write(b"\x1BR") - while (self.__serial.in_waiting): - self.__serial.read_all() - time.sleep(0.1) - - - def __read(self, bytes: int) -> bytes: - return self.__serial.read(bytes) - - - def __write(self, data: bytes) -> None: - self.__serial.write(self.__escape(data)) - - - def __read_long(self, length: int) -> bytes: - data = bytearray() - while (len(data) < length): - data += self.__read(length - len(data)) - return bytes(data) - - - def __write_dummy(self, length: int) -> None: - self.__write(bytes(length)) - - - def __read_int(self) -> int: - return int.from_bytes(self.__read(4), byteorder="big") - - - def __write_int(self, value: int) -> None: - self.__write(value.to_bytes(4, byteorder="big")) - - - def __read_cmd_status(self, cmd: str) -> None: - if (self.__read(4) != f"CMP{cmd[0]}".encode(encoding="ascii")): - raise SC64Exception("Wrong command response") - - - def __write_cmd(self, cmd: str, arg1: int, arg2: int) -> None: - self.__write(f"CMD{cmd[0]}".encode()) - self.__write_int(arg1) - self.__write_int(arg2) - - - def __find_sc64(self) -> None: ports = list_ports.comports() device_found = False - if (self.__serial != None and self.__serial.isOpen()): - self.__serial.close() + if (self.__serial != None and self.__serial.is_open): + raise ConnectionException('Serial port is already open') for p in ports: - if (p.vid == 0x0403 and p.pid == 0x6014 and p.serial_number.startswith("SC64")): + if (p.vid == self.__VID and p.pid == self.__PID and p.serial_number.startswith('SC64')): try: - self.__serial = Serial(p.device, timeout=1.0, write_timeout=1.0) - self.__serial.flushOutput() - self.reset_link() - self.__probe_device() - except (SerialException, SC64Exception): + self.__serial = serial.Serial(p.device, timeout=1.0, write_timeout=1.0) + self.__reset_link() + except (serial.SerialException, ConnectionException): if (self.__serial): self.__serial.close() continue @@ -164,543 +54,705 @@ class SC64: break if (not device_found): - raise SC64Exception("No SummerCart64 device was found") + raise ConnectionException('No SC64 device was found') + + self.__thread_read = Thread(target=self.__serial_process_input, daemon=True) + self.__thread_write = Thread(target=self.__serial_process_output, daemon=True) + + self.__thread_read.start() + self.__thread_write.start() + + def __del__(self) -> None: + self.__disconnect = True + if (self.__thread_read != None and self.__thread_read.is_alive()): + self.__thread_read.join(1) + if (self.__thread_write != None and self.__thread_write.is_alive()): + self.__thread_write.join(1) + if (self.__serial != None and self.__serial.is_open): + self.__serial.close() + + def __reset_link(self) -> None: + self.__serial.reset_output_buffer() + + retry_counter = 0 + self.__serial.dtr = 1 + while (self.__serial.dsr == 0): + time.sleep(0.1) + retry_counter += 1 + if (retry_counter >= 10): + raise ConnectionException('Could not reset SC64 device') + + self.__serial.reset_input_buffer() + + retry_counter = 0 + self.__serial.dtr = 0 + while (self.__serial.dsr == 1): + time.sleep(0.1) + retry_counter += 1 + if (retry_counter >= 10): + raise ConnectionException('Could not reset SC64 device') + + def __write(self, data: bytes) -> None: + try: + if (self.__disconnect): + raise ConnectionException + for offset in range(0, len(data), self.__CHUNK_SIZE): + self.__serial.write(data[offset:offset + self.__CHUNK_SIZE]) + self.__serial.flush() + except (serial.SerialException, serial.SerialTimeoutException): + raise ConnectionException + + def __read(self, length: int) -> bytes: + try: + data = b'' + while (len(data) < length and not self.__disconnect): + data += self.__serial.read(length - len(data)) + if (self.__disconnect): + raise ConnectionException + return data + except serial.SerialException: + raise ConnectionException + + def __read_int(self) -> int: + return int.from_bytes(self.__read(4), byteorder='big') + + def __serial_process_output(self) -> None: + while (not self.__disconnect and self.__serial != None and self.__serial.is_open): + try: + packet: bytes = self.__queue_output.get(timeout=0.1) + self.__write(packet) + self.__queue_output.task_done() + except queue.Empty: + continue + except ConnectionException: + break + + def __serial_process_input(self) -> None: + while (not self.__disconnect and self.__serial != None and self.__serial.is_open): + try: + token = self.__read(4) + if (len(token) == 4): + identifier = token[0:3] + command = token[3:4] + if (identifier == b'PKT'): + data = self.__read(self.__read_int()) + self.__queue_packet.put((command, data)) + elif (identifier == b'CMP' or identifier == b'ERR'): + data = self.__read(self.__read_int()) + success = identifier == b'CMP' + self.__queue_input.put((command, data, success)) + else: + raise ConnectionException + except ConnectionException: + break + + def __check_threads(self) -> None: + if (not (self.__thread_write.is_alive() and self.__thread_read.is_alive())): + raise ConnectionException('Serial link is closed') + + def __queue_cmd(self, cmd: bytes, args: list[int]=[0, 0], data: bytes=b'') -> None: + if (len(cmd) != 1): + raise ValueError('Length of command is different than 1 byte') + if (len(args) != 2): + raise ValueError('Number of arguments is different than 2') + packet: bytes = b'CMD' + packet += cmd[0:1] + for arg in args: + packet += arg.to_bytes(4, byteorder='big') + packet += data + self.__queue_output.put(packet) + + def __pop_response(self, cmd: bytes, timeout: float) -> bytes: + try: + (response_cmd, data, success) = self.__queue_input.get(timeout=timeout) + self.__queue_input.task_done() + if (cmd != response_cmd): + raise ConnectionException('CMD wrong command response') + if (success == False): + raise ConnectionException('CMD response error') + return data + except queue.Empty: + raise ConnectionException('CMD response timeout') + + def execute_cmd(self, cmd: bytes, args: list[int]=[0, 0], data: bytes=b'', response: bool=True, timeout: float=5.0) -> Optional[bytes]: + self.__check_threads() + self.__queue_cmd(cmd, args, data) + if (response): + return self.__pop_response(cmd, timeout) + return None + + def get_packet(self, timeout: float=0.1) -> Optional[tuple[bytes, bytes]]: + self.__check_threads() + try: + packet = self.__queue_packet.get(timeout=timeout) + self.__queue_packet.task_done() + return packet + except queue.Empty: + return None - def __probe_device(self) -> None: - self.__write_cmd("V", 0, 0) - version = self.__read_int() - self.__read_cmd_status("V") - if (version != self.__SC64_VERSION_V2): - raise SC64Exception(f"Unknown hardware version: {hex(version)}") +class SC64: + class __Address(IntEnum): + MEMORY = 0x0000_0000 + SDRAM = 0x0000_0000 + FLASH = 0x0400_0000 + BUFFER = 0x0500_0000 + EEPROM = 0x0500_2000 + FIRMWARE = 0x0200_0000 + DDIPL = 0x03BC_0000 + SAVE = 0x03FE_0000 + EXTENDED = 0x0400_0000 + BOOTLOADER = 0x04E0_0000 + SHADOW = 0x04FE_0000 + class __Length(IntEnum): + MEMORY = 0x0500_2980 + SDRAM = (64 * 1024 * 1024) + FLASH = (16 * 1024 * 1024) + BUFFER = (8 * 1024) + EEPROM = (2 * 1024) + DDIPL = (4 * 1024 * 1024) + SAVE = (128 * 1024) + EXTENDED = (14 * 1024 * 1024) + BOOTLOADER = (1920 * 1024) + SHADOW = (128 * 1024) - def __query_config(self, id: int) -> int: - self.__write_cmd("Q", id, 0) - value = self.__read_int() - self.__read_cmd_status("Q") - return value + class __SaveLength(IntEnum): + NONE = 0 + EEPROM_4K = 512 + EEPROM_16K = (2 * 1024) + SRAM = (32 * 1024) + FLASHRAM = (128 * 1024) + SRAM_3X = (3 * 32 * 1024) + class __CfgId(IntEnum): + BOOTLOADER_SWITCH = 0 + ROM_WRITE_ENABLE = 1 + ROM_SHADOW_ENABLE = 2 + DD_MODE = 3 + ISV_ADDRESS = 4 + BOOT_MODE = 5 + SAVE_TYPE = 6 + CIC_SEED = 7 + TV_TYPE = 8 + DD_SD_ENABLE = 9 + DD_DRIVE_TYPE = 10 + DD_DISK_STATE = 11 + BUTTON_STATE = 12 + BUTTON_MODE = 13 + ROM_EXTENDED_ENABLE = 14 - def __change_config(self, id: int, arg: int = 0, ignore_response: bool = False) -> None: - self.__write_cmd("C", id, arg) - if (not ignore_response): - self.__read_cmd_status("C") + class __UpdateError(IntEnum): + OK = 0 + TOKEN = 1 + CHECKSUM = 2 + SIZE = 3 + UNKNOWN_CHUNK = 4 + READ = 5 + class __UpdateStatus(IntEnum): + MCU = 1 + FPGA = 2 + BOOTLOADER = 3 + DONE = 0x80 + ERROR = 0xFF - def __debug_write(self, type: int, data: bytes) -> None: - self.__write_cmd("D", type, len(data)) - self.__write(data) + class __DDMode(IntEnum): + NONE = 0 + REGS = 1 + DDIPL = 2 + FULL = 3 + class __DDDriveType(IntEnum): + RETAIL = 0 + DEVELOPMENT = 1 - def __read_file_from_sdram(self, file: str, offset: int, length: int, align: int = 2) -> None: - with open(file, "wb") as f: - transfer_size = self.__align(length, align) - self.__set_progress_init(transfer_size, os.path.basename(f.name)) - self.__write_cmd("R", offset, transfer_size) - while (f.tell() < length): - chunk_size = min(self.__CHUNK_SIZE, length - f.tell()) - f.write(self.__read(chunk_size)) - self.__set_progress_value(f.tell()) - if (transfer_size != length): - self.__read(transfer_size - length) - self.__read_cmd_status("R") - self.__set_progress_finish() + class __DDDiskState(IntEnum): + EJECTED = 0 + INSERTED = 1 + CHANGED = 2 + class __ButtonMode(IntEnum): + NONE = 0 + N64_IRQ = 1 + USB_PACKET = 2 + DD_DISK_SWAP = 3 - def __write_file_to_sdram(self, file: str, offset: int, align: int = 2, min_length: int = 0) -> None: - with open(file, "rb") as f: - length = os.fstat(f.fileno()).st_size - transfer_size = self.__align(max(length, min_length), align) - self.__set_progress_init(transfer_size, os.path.basename(f.name)) - self.__write_cmd("W", offset, transfer_size) - while (f.tell() < length): - self.__write(f.read(min(self.__CHUNK_SIZE, length - f.tell()))) - self.__set_progress_value(f.tell()) - if (transfer_size != length): - self.__write_dummy(transfer_size - length) - self.__read_cmd_status("W") - self.__set_progress_finish() + class BootMode(IntEnum): + MENU = 0 + ROM = 1 + DDIPL = 2 + DIRECT = 3 + class SaveType(IntEnum): + NONE = 0 + EEPROM_4K = 1 + EEPROM_16K = 2 + SRAM = 3 + FLASHRAM = 4 + SRAM_3X = 5 - def __get_save_length(self) -> None: - save_type = self.__query_config(self.__CFG_ID_SAVE_TYPE) - return { - 0: 0, - 1: 512, - 2: 2048, - 3: (32 * 1024), - 4: (128 * 1024), - 5: (3 * 32 * 1024), - 6: (128 * 1024) - }[save_type] + class CICSeed(IntEnum): + ALECK = 0xAC + X101 = 0x13F + X102 = 0x3F + X103 = 0x78 + X105 = 0x91 + X106 = 0x85 + DD_JP = 0xDD + DD_US = 0xDE + AUTO = 0xFFFF + class TVType(IntEnum): + PAL = 0 + NTSC = 1 + MPAL = 2 + AUTO = 3 - def __reconfigure(self) -> None: - magic = self.__query_config(self.__CFG_ID_RECONFIGURE) - self.__change_config(self.__CFG_ID_RECONFIGURE, magic, ignore_response=True) - time.sleep(0.2) + class __DebugDatatype(IntEnum): + TEXT = 1 + RAWBINARY = 2 + HEADER = 3 + SCREENSHOT = 4 + __isv_line_buffer: bytes = b'' + __debug_header: Optional[bytes] = None - def backup_firmware(self, file: str) -> None: - length = self.__query_config(self.__CFG_ID_FLASH_SIZE) - self.__change_config(self.__CFG_ID_FLASH_READ, self.__UPDATE_OFFSET) - self.__read_file_from_sdram(file, self.__UPDATE_OFFSET, length) + def __init__(self) -> None: + self.__link = SC64Serial() + version = self.__link.execute_cmd(cmd=b'v') + if (version != b'SCv2'): + raise ConnectionException('Unknown SC64 API version') + def __get_int(self, data: bytes) -> int: + return int.from_bytes(data[:4], byteorder='big') - def update_firmware(self, file: str) -> None: - self.__write_file_to_sdram(file, self.__UPDATE_OFFSET) - saved_timeout = self.__serial.timeout - self.__serial.timeout = 20.0 - self.__change_config(self.__CFG_ID_FLASH_PROGRAM, self.__UPDATE_OFFSET) - self.__serial.timeout = saved_timeout - self.__reconfigure() - self.__find_sc64() + def __set_config(self, config: __CfgId, value: int) -> None: + try: + self.__link.execute_cmd(cmd=b'C', args=[config, value]) + except ConnectionException: + raise ValueError(f'Could not set config {config.name} to {value:08X}') + def __get_config(self, config: __CfgId) -> int: + try: + data = self.__link.execute_cmd(cmd=b'c', args=[config, 0]) + except ConnectionException: + raise ValueError(f'Could not get config {config.name}') + return self.__get_int(data) - def set_boot_mode(self, mode: int) -> None: - if (mode >= 0 and mode <= 3): - self.__change_config(self.__CFG_ID_BOOT_MODE, mode) - else: - raise SC64Exception("Boot mode outside of supported values") + def __write_memory(self, address: int, data: bytes) -> None: + if (len(data) > 0): + self.__link.execute_cmd(cmd=b'M', args=[address, len(data)], data=data, timeout=20.0) - - def get_boot_mode_label(self, mode: int) -> None: - if (mode < 0 or mode > 3): - return "Unknown" - return { - 0: "Load menu from SD card", - 1: "Load ROM from SDRAM through bootloader", - 2: "Load DDIPL from SDRAM", - 3: "Load ROM from SDRAM directly without bootloader" - }[mode] - - - def set_tv_type(self, type: int = None) -> None: - if (type == None or type == 3): - self.__change_config(self.__CFG_ID_TV_TYPE, 3) - elif (type >= 0 and type <= 2): - self.__change_config(self.__CFG_ID_TV_TYPE, type) - else: - raise SC64Exception("TV type outside of supported values") - - - def get_tv_type_label(self, type: int) -> None: - if (type < 0 or type > 2): - return "Unknown" - return { - 0: "PAL", - 1: "NTSC", - 2: "MPAL" - }[type] - - - def set_cic_seed(self, seed: int = None) -> None: - if (seed == None or seed == 0xFFFF): - self.__change_config(self.__CFG_ID_CIC_SEED, 0xFFFF) - elif (seed >= 0 and seed <= 0x1FF): - self.__change_config(self.__CFG_ID_CIC_SEED, seed) - else: - raise SC64Exception("CIC seed outside of supported values") - - - def download_rom(self, file: str, length: int, offset: int = 0) -> None: - self.__read_file_from_sdram(file, offset, length) - - - def upload_rom(self, file: str, offset: int = 0) -> None: - self.__write_file_to_sdram(file, offset, min_length=self.__MIN_ROM_LENGTH) - - - def set_save_type(self, type: int) -> None: - if (type >= 0 and type <= 6): - self.__change_config(self.__CFG_ID_SAVE_TYPE, type) - else: - raise SC64Exception("Save type outside of supported values") - - - def get_save_type_label(self, type: int) -> None: - if (type < 0 or type > 6): - return "Unknown" - return { - 0: "No save", - 1: "EEPROM 4Kb", - 2: "EEPROM 16Kb", - 3: "SRAM 256Kb", - 4: "FlashRAM 1Mb", - 5: "SRAM 768Kb", - 6: "FlashRAM 1Mb (Pokemon Stadium 2 special case)" - }[type] - - - def download_save(self, file: str) -> None: - length = self.__get_save_length() + def __read_memory(self, address: int, length: int) -> bytes: if (length > 0): - offset = self.__query_config(self.__CFG_ID_SAVE_OFFEST) - self.__read_file_from_sdram(file, offset, length) - else: - raise SC64Exception("Can't read save data - no save type is set") + return self.__link.execute_cmd(cmd=b'm', args=[address, length], timeout=20.0) + return bytes([]) + def __dd_set_block_ready(self, error: int) -> None: + self.__link.execute_cmd(cmd=b'D', args=[error, 0]) - def upload_save(self, file: str) -> None: - length = self.__get_save_length() - save_length = os.path.getsize(file) - if (length <= 0): - raise SC64Exception("Can't write save data - no save type is set") - elif (length != save_length): - raise SC64Exception("Can't write save data - save file size is different than expected") - else: - offset = self.__query_config(self.__CFG_ID_SAVE_OFFEST) - self.__write_file_to_sdram(file, offset) + def __flash_wait_busy(self) -> int: + data = self.__link.execute_cmd(cmd=b'p') + return self.__get_int(data[0:4]) + def __flash_erase_block(self, address: int) -> None: + self.__link.execute_cmd(cmd=b'P', args=[address, 0]) - def set_dd_enable(self, enable: bool) -> None: - self.__change_config(self.__CFG_ID_DD_ENABLE, 1 if enable else 0) + def __erase_flash_region(self, address: int, length: int) -> None: + if (address < self.__Address.FLASH): + raise ValueError('Flash erase address or length outside of possible range') + if ((address + length) > (self.__Address.FLASH + self.__Length.FLASH)): + raise ValueError('Flash erase address or length outside of possible range') + erase_block_size = self.__flash_wait_busy() + if (address % erase_block_size != 0): + raise ValueError('Flash erase address not aligned to block size') + for offset in range(address, address + length, erase_block_size): + self.__flash_erase_block(offset) + self.__flash_wait_busy() + def __program_flash(self, address: int, data: bytes): + program_chunk_size = (128 * 1024) + if (self.__read_memory(address, len(data)) != data): + self.__erase_flash_region(address, len(data)) + for offset in range(0, len(data), program_chunk_size): + self.__write_memory(address + offset, data[offset:offset + program_chunk_size]) + if (self.__read_memory(address, len(data)) != data): + raise ConnectionException('Flash memory program failure') - def download_dd_ipl(self, file: str) -> None: - dd_ipl_offset = self.__query_config(self.__CFG_ID_DDIPL_OFFEST) - self.__read_file_from_sdram(file, dd_ipl_offset, length=self.__DDIPL_ROM_LENGTH) + def reset_state(self) -> None: + self.__link.execute_cmd(cmd=b'R') + def get_state(self): + return { + 'bootloader_switch': bool(self.__get_config(self.__CfgId.BOOTLOADER_SWITCH)), + 'rom_write_enable': bool(self.__get_config(self.__CfgId.ROM_WRITE_ENABLE)), + 'rom_shadow_enable': bool(self.__get_config(self.__CfgId.ROM_SHADOW_ENABLE)), + 'dd_mode': self.__DDMode(self.__get_config(self.__CfgId.DD_MODE)), + 'isv_address': self.__get_config(self.__CfgId.ISV_ADDRESS), + 'boot_mode': self.BootMode(self.__get_config(self.__CfgId.BOOT_MODE)), + 'save_type': self.SaveType(self.__get_config(self.__CfgId.SAVE_TYPE)), + 'cic_seed': self.CICSeed(self.__get_config(self.__CfgId.CIC_SEED)), + 'tv_type': self.TVType(self.__get_config(self.__CfgId.TV_TYPE)), + 'dd_sd_enable': bool(self.__get_config(self.__CfgId.DD_SD_ENABLE)), + 'dd_drive_type': self.__DDDriveType(self.__get_config(self.__CfgId.DD_DRIVE_TYPE)), + 'dd_disk_state': self.__DDDiskState(self.__get_config(self.__CfgId.DD_DISK_STATE)), + 'button_state': bool(self.__get_config(self.__CfgId.BUTTON_STATE)), + 'button_mode': self.__ButtonMode(self.__get_config(self.__CfgId.BUTTON_MODE)), + 'rom_extended_enable': bool(self.__get_config(self.__CfgId.ROM_EXTENDED_ENABLE)), + } - def upload_dd_ipl(self, file: str, offset: int = None) -> None: - if (offset != None): - self.__change_config(self.__CFG_ID_DDIPL_OFFEST, offset) - dd_ipl_offset = self.__query_config(self.__CFG_ID_DDIPL_OFFEST) - self.__write_file_to_sdram(file, dd_ipl_offset, min_length=self.__DDIPL_ROM_LENGTH) + def debug_send(self, datatype: __DebugDatatype, data: bytes) -> None: + if (len(data) > (8 * 1024 * 1024)): + raise ValueError('Debug data size too big') + self.__link.execute_cmd(cmd=b'U', args=[datatype, len(data)], data=data, response=False) + def download_memory(self) -> bytes: + return self.__read_memory(self.__Address.MEMORY, self.__Length.MEMORY) - def set_dd_disk_state(self, state: int) -> None: - if (state == "ejected"): - self.__change_config(self.__CFG_ID_DD_SETTING, self.__DD_SETTING_DISK_EJECTED) - elif (state == "inserted"): - self.__change_config(self.__CFG_ID_DD_SETTING, self.__DD_SETTING_DISK_INSERTED) - elif (state == "changed"): - self.__change_config(self.__CFG_ID_DD_SETTING, self.__DD_SETTING_DISK_CHANGED) - else: - raise SC64Exception("DD disk state outside of supported values") + def upload_rom(self, data: bytes, use_shadow: bool=True) -> None: + rom_length = len(data) + if (rom_length > (self.__Length.SDRAM + self.__Length.EXTENDED)): + raise ValueError('ROM size too big') + sdram_length = self.__Length.SDRAM + shadow_enabled = use_shadow and rom_length > (self.__Length.SDRAM - self.__Length.SHADOW) + extended_enabled = rom_length > self.__Length.SDRAM + if (shadow_enabled): + sdram_length = (self.__Length.SDRAM - self.__Length.SHADOW) + shadow_data = data[sdram_length:sdram_length + self.__Length.SHADOW] + self.__program_flash(self.__Address.SHADOW, shadow_data) + self.__set_config(self.__CfgId.ROM_SHADOW_ENABLE, shadow_enabled) + if (extended_enabled): + extended_data = data[self.__Length.SDRAM:] + self.__program_flash(self.__Address.EXTENDED, extended_data) + self.__set_config(self.__CfgId.ROM_EXTENDED_ENABLE, extended_enabled) + self.__write_memory(self.__Address.SDRAM, data[:sdram_length]) + def upload_ddipl(self, data: bytes) -> None: + if (len(data) > self.__Length.DDIPL): + raise ValueError('DDIPL size too big') + self.__write_memory(self.__Address.DDIPL, data) - def __dd_create_configuration(self, handle: TextIOWrapper) -> tuple[str, int, list[tuple[int, int]]]: - DISK_HEADS = 2 - DISK_TRACKS = 1175 - DISK_BLOCKS_PER_TRACK = 2 - DISK_SECTORS_PER_BLOCK = 85 - DISK_BAD_TRACKS_PER_ZONE = 12 - DISK_SYSTEM_SECTOR_SIZE = 232 + def upload_save(self, data: bytes) -> None: + save_type = self.SaveType(self.__get_config(self.__CfgId.SAVE_TYPE)) + if (save_type == self.SaveType.NONE): + raise ValueError('No save type set inside SC64 device') + if (len(data) != self.__SaveLength[save_type.name]): + raise ValueError('Wrong save data length') + address = self.__Address.SAVE + if (save_type == self.SaveType.EEPROM_4K or save_type == self.SaveType.EEPROM_16K): + address = self.__Address.EEPROM + self.__write_memory(address, data) - DISK_ZONES = [ - (0, 232, 158, 0), - (0, 216, 158, 158), - (0, 208, 149, 316), - (0, 192, 149, 465), - (0, 176, 149, 614), - (0, 160, 149, 763), - (0, 144, 149, 912), - (0, 128, 114, 1061), - (1, 216, 158, 157), - (1, 208, 158, 315), - (1, 192, 149, 464), - (1, 176, 149, 613), - (1, 160, 149, 762), - (1, 144, 149, 911), - (1, 128, 149, 1060), - (1, 112, 114, 1174), - ] + def download_save(self) -> bytes: + save_type = self.SaveType(self.__get_config(self.__CfgId.SAVE_TYPE)) + if (save_type == self.SaveType.NONE): + raise ValueError('No save type set inside SC64 device') + address = self.__Address.SAVE + length = self.__SaveLength[save_type.name] + if (save_type == self.SaveType.EEPROM_4K or save_type == self.SaveType.EEPROM_16K): + address = self.__Address.EEPROM + return self.__read_memory(address, length) - DISK_VZONE_TO_PZONE = [ - [0, 1, 2, 9, 8, 3, 4, 5, 6, 7, 15, 14, 13, 12, 11, 10], - [0, 1, 2, 3, 10, 9, 8, 4, 5, 6, 7, 15, 14, 13, 12, 11], - [0, 1, 2, 3, 4, 11, 10, 9, 8, 5, 6, 7, 15, 14, 13, 12], - [0, 1, 2, 3, 4, 5, 12, 11, 10, 9, 8, 6, 7, 15, 14, 13], - [0, 1, 2, 3, 4, 5, 6, 13, 12, 11, 10, 9, 8, 7, 15, 14], - [0, 1, 2, 3, 4, 5, 6, 7, 14, 13, 12, 11, 10, 9, 8, 15], - [0, 1, 2, 3, 4, 5, 6, 7, 15, 14, 13, 12, 11, 10, 9, 8], - ] + def upload_bootloader(self, data: bytes) -> None: + if (len(data) > self.__Length.BOOTLOADER): + raise ValueError('Bootloader size too big') + self.__program_flash(self.__Address.BOOTLOADER, data) - DISK_DRIVE_TYPES = [( - "development", - 192, - [11, 10, 3, 2], - [0, 1, 8, 9, 16, 17, 18, 19, 20, 21, 22, 23], - ), ( - "retail", - 232, - [9, 8, 1, 0], - [2, 3, 10, 11, 12, 16, 17, 18, 19, 20, 21, 22, 23], - )] + def set_rtc(self, t: datetime) -> None: + to_bcd = lambda v: ((int((v / 10) % 10) << 4) | int(int(v) % 10)) + data = bytes([ + to_bcd(t.weekday() + 1), + to_bcd(t.hour), + to_bcd(t.minute), + to_bcd(t.second), + 0, + to_bcd(t.year), + to_bcd(t.month), + to_bcd(t.day), + ]) + self.__link.execute_cmd(cmd=b'T', args=[self.__get_int(data[0:4]), self.__get_int(data[4:8])]) - def __check_system_block(lba: int, sector_size: int, check_disk_type: bool) -> tuple[bool, bytes]: - handle.seek(lba * DISK_SYSTEM_SECTOR_SIZE * DISK_SECTORS_PER_BLOCK) - system_block_data = handle.read(sector_size * DISK_SECTORS_PER_BLOCK) - system_data = system_block_data[:sector_size] - for sector in range(1, DISK_SECTORS_PER_BLOCK): - sector_data = system_block_data[(sector * sector_size):][:sector_size] - if (system_data != sector_data): - return (False, None) - if (check_disk_type): - if (system_data[4] != 0x10): - return (False, None) - if ((system_data[5] & 0xF0) != 0x10): - return (False, None) - return (True, system_data) + def set_boot_mode(self, mode: BootMode) -> None: + self.__set_config(self.__CfgId.BOOT_MODE, mode) - disk_drive_type = None - disk_system_data = None - disk_id_data = None - disk_bad_lbas = [] + def set_cic_seed(self, seed: int) -> None: + if (seed != self.CICSeed.AUTO): + if (seed < 0 or seed > 0x1FF): + raise ValueError('CIC seed outside of allowed values') + self.__set_config(self.__CfgId.CIC_SEED, seed) - drive_index = 0 - while (disk_system_data == None) and (drive_index < len(DISK_DRIVE_TYPES)): - (drive_type, system_sector_size, system_data_lbas, bad_lbas) = DISK_DRIVE_TYPES[drive_index] - disk_bad_lbas.clear() - disk_bad_lbas.extend(bad_lbas) - for system_lba in system_data_lbas: - (valid, system_data) = __check_system_block(system_lba, system_sector_size, check_disk_type=True) - if (valid): - disk_drive_type = drive_type - disk_system_data = system_data + def set_tv_type(self, type: TVType) -> None: + self.__set_config(self.__CfgId.TV_TYPE, type) + + def set_save_type(self, type: SaveType) -> None: + self.__set_config(self.__CfgId.SAVE_TYPE, type) + + def set_cic_parameters(self, disabled=False, dd_mode: bool=False, seed: int=0x3F, checksum: bytes=bytes([0xA5, 0x36, 0xC0, 0xF1, 0xD8, 0x59])) -> None: + if (seed < 0 or seed > 0xFF): + raise ValueError('CIC seed outside of allowed values') + if (len(checksum) != 6): + raise ValueError('CIC checksum length outside of allowed values') + mode = (1 << 1) if disabled else 0 + mode |= (1 << 0) if dd_mode else 0 + data = bytes([mode, seed]) + data = [*data, *checksum] + self.__link.execute_cmd(cmd=b'B', args=[self.__get_int(data[0:4]), self.__get_int(data[4:8])]) + + def update_firmware(self, data: bytes, status_callback: Optional[Callable[[str], None]]=None) -> None: + address = self.__Address.FIRMWARE + self.__write_memory(address, data) + response = self.__link.execute_cmd(cmd=b'F', args=[address, len(data)]) + error = self.__UpdateError(self.__get_int(response[0:4])) + if (error != self.__UpdateError.OK): + raise ConnectionException(f'Bad update image [{error.name}]') + status = None + while status != self.__UpdateStatus.DONE: + packet = self.__link.get_packet(timeout=60.0) + if (packet == None): + raise ConnectionException('Update timeout') + (cmd, data) = packet + if (cmd != b'F'): + raise ConnectionException('Wrong update status packet') + status = self.__UpdateStatus(self.__get_int(data)) + if (status_callback): + status_callback(status.name) + if (status == self.__UpdateStatus.ERROR): + raise ConnectionException('Update error, device is most likely bricked') + time.sleep(2) + + def backup_firmware(self) -> bytes: + address = self.__Address.FIRMWARE + info = self.__link.execute_cmd(cmd=b'f', args=[address, 0], timeout=60.0) + error = self.__UpdateError(self.__get_int(info[0:4])) + length = self.__get_int(info[4:8]) + if (error != self.__UpdateError.OK): + raise ConnectionException('Error while getting firmware backup') + return self.__read_memory(address, length) + + def __generate_filename(self, prefix: str, extension: str) -> str: + return f'{prefix}-{datetime.now().strftime("%y%m%d%H%M%S.%f")}.{extension}' + + def __handle_dd_packet(self, dd: Optional[DD64Image], data: bytes) -> None: + CMD_READ_BLOCK = 1 + CMD_WRITE_BLOCK = 2 + cmd = self.__get_int(data[0:]) + address = self.__get_int(data[4:]) + track_head_block = self.__get_int(data[8:]) + track = (track_head_block >> 2) & 0xFFF + head = (track_head_block >> 1) & 0x1 + block = track_head_block & 0x1 + try: + if (not dd or not dd.loaded): + raise BadBlockError + if (cmd == CMD_READ_BLOCK): + block_data = dd.read_block(track, head, block) + self.__write_memory(address, block_data) + self.__dd_set_block_ready(0) + elif (cmd == CMD_WRITE_BLOCK): + block_data = data[12:] + dd.write_block(track, head, block, block_data) + self.__dd_set_block_ready(0) + else: + self.__dd_set_block_ready(1) + except BadBlockError: + self.__dd_set_block_ready(1) + + def __handle_isv_packet(self, data: bytes) -> None: + self.__isv_line_buffer += data + while (b'\n' in self.__isv_line_buffer): + (line, self.__isv_line_buffer) = self.__isv_line_buffer.split(b'\n', 1) + print(line.decode('EUC-JP', errors='backslashreplace')) + + def __handle_usb_packet(self, data: bytes) -> None: + header = self.__get_int(data[0:4]) + datatype = self.__DebugDatatype((header >> 24) & 0xFF) + length = (header & 0xFFFFFF) + packet = data[4:] + if (len(packet) != length): + print(f'Debug packet length and data length did not match') + elif (datatype == self.__DebugDatatype.TEXT): + print(packet.decode('UTF-8', errors='backslashreplace'), end='') + elif (datatype == self.__DebugDatatype.RAWBINARY): + filename = self.__generate_filename('binaryout', 'bin') + with open(filename, 'wb') as f: + f.write(packet) + print(f'Wrote {len(packet)} bytes to {filename}') + elif (datatype == self.__DebugDatatype.HEADER): + if (len(packet) == 16): + self.__debug_header = packet + else: + print(f'Size of header packet is invalid: {len(packet)}') + elif (datatype == self.__DebugDatatype.SCREENSHOT): + filename = self.__generate_filename('screenshot', 'png') + if (self.__debug_header != None): + header_datatype = self.__get_int(self.__debug_header[0:4]) + pixel_format = self.__get_int(self.__debug_header[4:8]) + image_w = self.__get_int(self.__debug_header[8:12]) + image_h = self.__get_int(self.__debug_header[12:16]) + if (header_datatype == 0x04 and pixel_format != 0 and image_w != 0 and image_h != 0): + mode = 'RGBA' if pixel_format == 4 else 'I;16' + screenshot = Image.frombytes(mode, (image_w, image_h), packet) + screenshot.save(filename) + print(f'Wrote {image_w}x{image_h} pixels to {filename}') else: - disk_bad_lbas.append(system_lba) - drive_index += 1 - - for id_lba in [15, 14]: - (valid, id_data) = __check_system_block(id_lba, DISK_SYSTEM_SECTOR_SIZE, check_disk_type=False) - if (valid): - disk_id_data = id_data + print('Screenshot header data is invalid') else: - disk_bad_lbas.append(id_lba) + print('Got screenshot packet without header data') - if not (disk_system_data and disk_id_data): - raise SC64Exception("Provided 64DD disk file is not valid") + def __handle_debug_input(self) -> None: + running = True + while (running): + try: + command = input() + if (len(command) > 0): + data = b'' + datatype = self.__DebugDatatype.TEXT + if (command.count('@') != 2): + data += f'{command}\0'.encode() + else: + start = command.index('@') + end = command.rindex('@') + filename = command[(start + 1):end] + if (len(filename) == 0): + raise FileNotFoundError + with open(filename, 'rb') as f: + file_data = f.read() + if (command.startswith('@') and command.endswith('@')): + datatype = self.__DebugDatatype.RAWBINARY + data += file_data + else: + data += f'{command[:start]}@{len(file_data)}@'.encode() + data += file_data + data += b'\0' + self.debug_send(datatype, data) + except ValueError as e: + print(f'Error: {e}') + except FileNotFoundError as e: + print(f'Error: Cannot open file {e.filename}') + except EOFError: + running = False - disk_zone_bad_tracks = [] + def debug_loop(self, isv: int=0, disks: Optional[list[str]]=None) -> None: + dd = None + current_image = 0 + next_image = 0 - for zone in range(len(DISK_ZONES)): - zone_bad_tracks = [] - start = 0 if zone == 0 else system_data[0x07 + zone] - stop = system_data[0x07 + zone + 1] - for offset in range(start, stop): - zone_bad_tracks.append(system_data[0x20 + offset]) - for ignored_track in range(DISK_BAD_TRACKS_PER_ZONE - len(zone_bad_tracks)): - zone_bad_tracks.append(DISK_ZONES[zone][2] - ignored_track - 1) - disk_zone_bad_tracks.append(zone_bad_tracks) + self.__set_config(self.__CfgId.ROM_WRITE_ENABLE, isv) + self.__set_config(self.__CfgId.ISV_ADDRESS, isv) + if (isv != 0): + print(f'IS-Viewer64 support set to [ENABLED] at ROM offset [0x{(isv):08X}]') + if (self.__get_config(self.__CfgId.ROM_SHADOW_ENABLE)): + print('ROM shadow enabled - IS-Viewer64 will NOT work (use --no-shadow option to disable it)') - thb_lba_table = [(0xFFFFFFFF, -1)] * (DISK_HEADS * DISK_TRACKS * DISK_BLOCKS_PER_TRACK) + if (disks): + dd = DD64Image() + drive_type = None + for path in disks: + try: + dd.load(path) + if (drive_type == None): + drive_type = dd.get_drive_type() + elif (drive_type != dd.get_drive_type()): + raise ValueError('Disk drive type mismatch') + dd.unload() + except ValueError as e: + dd = None + print(f'64DD disabled, incorrect disk images provided: {e}') + break + if (dd): + self.__set_config(self.__CfgId.DD_MODE, self.__DDMode.FULL) + self.__set_config(self.__CfgId.DD_SD_ENABLE, False) + self.__set_config(self.__CfgId.DD_DRIVE_TYPE, { + 'retail': self.__DDDriveType.RETAIL, + 'development': self.__DDDriveType.DEVELOPMENT + }[drive_type]) + self.__set_config(self.__CfgId.DD_DISK_STATE, self.__DDDiskState.EJECTED) + self.__set_config(self.__CfgId.BUTTON_MODE, self.__ButtonMode.USB_PACKET) + print('64DD enabled, loaded disks:') + for disk in disks: + print(f' - {os.path.basename(disk)}') + print('Press button on SC64 device to cycle through provided disks') - disk_type = disk_system_data[5] & 0x0F + print('\nDebug loop started, press Ctrl-C to exit\n') - current_lba = 0 - starting_block = 0 - disk_file_offset = 0 + try: + thread_input = Thread(target=self.__handle_debug_input, daemon=True) + thread_input.start() + while (thread_input.is_alive()): + packet = self.__link.get_packet() + if (packet != None): + (cmd, data) = packet + if (cmd == b'D'): + self.__handle_dd_packet(dd, data) + if (cmd == b'I'): + self.__handle_isv_packet(data) + if (cmd == b'U'): + self.__handle_usb_packet(data) + if (cmd == b'B'): + if (not dd.loaded): + dd.load(disks[next_image]) + self.__set_config(self.__CfgId.DD_DISK_STATE, self.__DDDiskState.INSERTED) + current_image = next_image + next_image += 1 + if (next_image >= len(disks)): + next_image = 0 + print(f'64DD disk inserted - {os.path.basename(disks[current_image])}') + else: + self.__set_config(self.__CfgId.DD_DISK_STATE, self.__DDDiskState.EJECTED) + dd.unload() + print(f'64DD disk ejected - {os.path.basename(disks[current_image])}') + except KeyboardInterrupt: + pass + finally: + print('\nDebug loop stopped\n') - for zone in DISK_VZONE_TO_PZONE[disk_type]: - (head, sector_size, tracks, track) = DISK_ZONES[zone] - - for zone_track in range(tracks): - current_zone_track = ((tracks - 1) - zone_track) if head else zone_track - - if (current_zone_track in disk_zone_bad_tracks[zone]): - track += (-1) if head else 1 - continue - - for block in range(DISK_BLOCKS_PER_TRACK): - if (current_lba not in disk_bad_lbas): - index = (track << 2) | (head << 1) | (starting_block ^ block) - thb_lba_table[index] = (disk_file_offset, current_lba) - disk_file_offset += sector_size * DISK_SECTORS_PER_BLOCK - current_lba += 1 - - track += (-1) if head else 1 - starting_block ^= 1 - - return (disk_drive_type, thb_lba_table) + if (dd and dd.loaded): + self.__set_config(self.__CfgId.DD_DISK_STATE, self.__DDDiskState.EJECTED) + if (isv != 0): + self.__set_config(self.__CfgId.ISV_ADDRESS, 0) - def set_dd_configuration_for_disk(self, file: str = None) -> None: - if (file): - with open(file, "rb+") as handle: - (disk_drive_type, thb_lba_table) = self.__dd_create_configuration(handle) - thb_table_offset = self.__query_config(self.__CFG_ID_DD_THB_TABLE_OFFSET) - data = bytearray() - self.__disk_lba_table = [0xFFFFFFFF] * len(thb_lba_table) - for (offset, lba) in thb_lba_table: - data += struct.pack(">I", offset) - self.__disk_lba_table[lba] = offset - self.__write_cmd("W", thb_table_offset, len(data)) - self.__write(data) - self.__read_cmd_status("W") - if (disk_drive_type == "retail"): - self.__change_config(self.__CFG_ID_DD_SETTING, self.__DD_SETTING_DRIVE_RETAIL) - elif (disk_drive_type == "development"): - self.__change_config(self.__CFG_ID_DD_SETTING, self.__DD_SETTING_DRIVE_DEVELOPMENT) - else: - raise SC64Exception("No DD disk file provided for disk info creation") +class EnumAction(argparse.Action): + def __init__(self, **kwargs): + type = kwargs.pop('type', None) + if type is None: + raise ValueError('No type was provided') + if not issubclass(type, Enum): + raise TypeError('Provided type is not an Enum subclass') + items = (choice.lower().replace('_', '-') for (choice, _) in type.__members__.items()) + kwargs.setdefault('choices', tuple(items)) + super(EnumAction, self).__init__(**kwargs) + self.__enum = type - - def __debug_process_fsd_set_sector(self, data: bytes) -> None: - sector = int.from_bytes(data[0:4], byteorder='big') - if (self.__fsd_file): - self.__fsd_file.seek(sector * 512) - - - def __debug_process_fsd_read(self, data: bytes) -> None: - length = int.from_bytes(data[0:4], byteorder='big') - if (self.__fsd_file): - self.__debug_write(self.__DEBUG_ID_FSD_READ, self.__fsd_file.read(length)) - else: - self.__debug_write(self.__DEBUG_ID_FSD_READ, bytes(length)) - - - def __debug_process_fsd_write(self, data: bytes) -> None: - if (self.__fsd_file): - self.__fsd_file.write(data) - - - def __debug_process_dd_block(self, data: bytes) -> None: - transfer_mode = int.from_bytes(data[0:4], byteorder='big') - sdram_offset = int.from_bytes(data[4:8], byteorder='big') - disk_file_offset = int.from_bytes(data[8:12], byteorder='big') - block_length = int.from_bytes(data[12:16], byteorder='big') - - print(f"64DD Block {'R' if transfer_mode else 'W'} - LBA: {self.__disk_lba_table.index(disk_file_offset):4}, Offset: 0x{disk_file_offset:08X}") - - if (self.__disk_file): - self.__disk_file.seek(disk_file_offset) - if (transfer_mode): - self.__write_cmd("W", sdram_offset, block_length) - self.__write(self.__disk_file.read(block_length)) - self.__read_cmd_status("W") - else: - self.__write_cmd("R", sdram_offset, block_length) - self.__disk_file.write(self.__read_long(block_length)) - self.__read_cmd_status("R") - - self.__change_config(self.__CFG_ID_DD_SETTING, self.__DD_SETTING_SET_BLOCK_READY) - - - def debug_loop(self, fsd_file: str = None, disk_file: str = None) -> None: - print("\r\n\033[34m --- Debug server started --- \033[0m\r\n") - - if (fsd_file): - self.__fsd_file = open(fsd_file, "rb+") - - if (disk_file): - self.__disk_file = open(disk_file, "rb+") - - start_indicator = bytearray() - dropped_bytes = 0 - - while (True): - while (start_indicator != b"DMA@"): - start_indicator.append(self.__read_long(1)[0]) - if (len(start_indicator) > 4): - dropped_bytes += 1 - start_indicator.pop(0) - start_indicator.clear() - - if (dropped_bytes): - print(f"\033[35mWarning - dropped {dropped_bytes} bytes from stream\033[0m", file=sys.stderr) - dropped_bytes = 0 - - header = self.__read_long(4) - id = int(header[0]) - length = int.from_bytes(header[1:4], byteorder="big") - data = self.__read_long(length) - self.__read_long(self.__align(length, 4) - length) - end_indicator = self.__read_long(4) - - if (end_indicator != b"CMPH"): - print(f"\033[35mGot unknown end indicator: {end_indicator.decode(encoding='ascii', errors='backslashreplace')}\033[0m", file=sys.stderr) - else: - if (id == self.__DEBUG_ID_TEXT): - print(data.decode(encoding="ascii", errors="backslashreplace"), end="") - elif (id == self.__DEBUG_ID_FSD_READ): - self.__debug_process_fsd_read(data) - elif (id == self.__DEBUG_ID_FSD_WRITE): - self.__debug_process_fsd_write(data) - elif (id == self.__DEBUG_ID_FSD_SECTOR): - self.__debug_process_fsd_set_sector(data) - elif (id == self.__DEBUG_ID_DD_BLOCK): - self.__debug_process_dd_block(data) - else: - print(f"\033[35mGot unknown id: {id}, length: {length}\033[0m", file=sys.stderr) + def __call__(self, parser, namespace, values, option_string): + key = str(values).upper().replace('-', '_') + value = self.__enum[key] + setattr(namespace, self.dest, value) -class SC64ProgressBar: - __LABEL_LENGTH = 30 - - - def __init__(self, sc64: SC64) -> None: - self.__sc64 = sc64 - self.__widgets = [ - "[ ", - progressbar.FormatLabel("{variables.label}", new_style=True), - " | ", - progressbar.Bar(left="", right=""), - " ", - progressbar.Percentage(), - " | ", - progressbar.DataSize(prefixes=(" ", "Ki", "Mi")), - " | ", - progressbar.AdaptiveTransferSpeed(), - " ]" - ] - self.__variables = {"label": ""} - self.__bar = None - - - def __enter__(self) -> None: - if (self.__sc64): - self.__sc64._SC64__progress_init = self.__progress_init - self.__sc64._SC64__progress_value = self.__progress_value - self.__sc64._SC64__progress_finish = self.__progress_finish - - - def __exit__(self, exc_type, exc_val, exc_tb) -> None: - if (self.__sc64): - self.__sc64._SC64__progress_init = None - self.__sc64._SC64__progress_value = None - self.__sc64._SC64__progress_finish = None - - - def __progress_init(self, value: int, label: str) -> None: - if (self.__bar == None): - self.__bar = progressbar.ProgressBar(widgets=self.__widgets, variables=self.__variables) - justified_label = label.ljust(self.__LABEL_LENGTH) - if (len(justified_label) > self.__LABEL_LENGTH): - justified_label = f"{justified_label[:self.__LABEL_LENGTH - 3]}..." - self.__bar.variables.label = justified_label - self.__bar.start(max_value=value) - - - def __progress_value(self, value: int) -> None: - self.__bar.update(value) - - - def __progress_finish(self) -> None: - self.__bar.finish(end="") - print() - - - -if __name__ == "__main__": - parser = argparse.ArgumentParser(description="SummerCart64 one stop control center") - parser.add_argument("-b", metavar="boot_mode", default="1", required=False, help="set boot mode (0 - 3)") - parser.add_argument("-t", metavar="tv_type", default="3", required=False, help="set TV type (0 - 2)") - parser.add_argument("-c", metavar="cic_seed", default="0xFFFF", required=False, help="set CIC seed") - parser.add_argument("-s", metavar="save_type", default="0", required=False, help="set save type (0 - 6)") - parser.add_argument("-d", default=False, action="store_true", required=False, help="enable 64DD emulation") - parser.add_argument("-r", default=False, action="store_true", required=False, help="perform reading operation instead of writing") - parser.add_argument("-l", metavar="length", default="0x101000", required=False, help="specify ROM length to read") - parser.add_argument("-u", metavar="update_path", default=None, required=False, help="path to update file") - parser.add_argument("-e", metavar="save_path", default=None, required=False, help="path to save file") - parser.add_argument("-i", metavar="ddipl_path", default=None, required=False, help="path to DDIPL file") - parser.add_argument("-q", default=None, action="store_true", required=False, help="start debug server") - parser.add_argument("-f", metavar="sd_path", default=None, required=False, help="path to disk or file for fake SD card emulation") - parser.add_argument("-k", metavar="disk_path", default=None, required=False, help="path to 64DD disk file") - parser.add_argument("rom", metavar="rom_path", default=None, help="path to ROM file", nargs="?") +if __name__ == '__main__': + parser = argparse.ArgumentParser(description='SC64 control software') + parser.add_argument('--backup-firmware', metavar='file', help='backup SC64 firmware and write it to specified file') + parser.add_argument('--update-firmware', metavar='file', help='update SC64 firmware from specified file') + parser.add_argument('--bootloader', metavar='file', help='update SC64 bootloader (not recommended, use --update-firmware instead)') + parser.add_argument('--reset-state', action='store_true', help='reset SC64 internal state') + parser.add_argument('--print-state', action='store_true', help='print SC64 internal state') + parser.add_argument('--boot', type=SC64.BootMode, action=EnumAction, help='set boot mode') + parser.add_argument('--tv', type=SC64.TVType, action=EnumAction, help='force TV type to set value') + parser.add_argument('--cic', type=SC64.CICSeed, action=EnumAction, help='force CIC seed to set value') + parser.add_argument('--rtc', action='store_true', help='update clock in SC64 to system time') + parser.add_argument('--no-shadow', action='store_false', help='do not put last 128 kB of ROM inside flash memory (can corrupt non EEPROM saves)') + parser.add_argument('--rom', metavar='file', help='upload ROM from specified file') + parser.add_argument('--save-type', type=SC64.SaveType, action=EnumAction, help='set save type') + parser.add_argument('--save', metavar='file', help='upload save from specified file') + parser.add_argument('--backup-save', metavar='file', help='download save and write it to specified file') + parser.add_argument('--ddipl', metavar='file', help='upload 64DD IPL from specified file') + parser.add_argument('--disk', metavar='file', action='append', help='path to 64DD disk (.ndd format), can be specified multiple times') + parser.add_argument('--isv', type=lambda x: int(x, 0), default=0, help='enable IS-Viewer64 support at provided ROM offset') + parser.add_argument('--debug', action='store_true', help='run debug loop (required for 64DD and IS-Viewer64)') + parser.add_argument('--download-memory', metavar='file', help='download whole memory space and write it to specified file') if (len(sys.argv) <= 1): parser.print_help() @@ -711,97 +763,91 @@ if __name__ == "__main__": try: sc64 = SC64() - boot_mode = int(args.b) - save_type = int(args.s) - tv_type = int(args.t) - cic_seed = int(args.c, 0) - dd_enable = args.d - is_read = args.r - rom_length = int(args.l, 0) - update_file = args.u - save_file = args.e - dd_ipl_file = args.i - rom_file = args.rom - debug_server = args.q - sd_file = args.f - disk_file = args.k + if (args.backup_firmware): + with open(args.backup_firmware, 'wb') as f: + print('Generating backup, this might take a while... ', end='', flush=True) + f.write(sc64.backup_firmware()) + print('done') - firmware_backup_file = "sc64firmware.bin.bak" + if (args.update_firmware): + with open(args.update_firmware, 'rb') as f: + print('Updating firmware, this might take a while... ', end='', flush=True) + status_callback = lambda status: print(f'{status} ', end='', flush=True) + sc64.update_firmware(f.read(), status_callback) + print('done') + + if (args.bootloader): + with open(args.bootloader, 'rb') as f: + print('Uploading Bootloader... ', end='', flush=True) + sc64.upload_bootloader(f.read()) + print('done') - with SC64ProgressBar(sc64): - if (update_file): - if (is_read): - sc64.backup_firmware(update_file) - else: - sc64.backup_firmware(firmware_backup_file) - if (not filecmp.cmp(update_file, firmware_backup_file)): - print("Update file different than contents of flash - updating SummerCart64") - sc64.update_firmware(update_file) - else: - print("SummerCart64 is already updated to latest version") - os.remove(firmware_backup_file) + if (args.reset_state): + sc64.reset_state() + print('SC64 internal state reset') - if (not is_read): - if (boot_mode != 1): - print(f"Setting boot mode to [{sc64.get_boot_mode_label(boot_mode)}]") - sc64.set_boot_mode(boot_mode) + if (args.print_state): + state = sc64.get_state() + print('Current SC64 internal state:') + for key, value in state.items(): + if (hasattr(value, 'name')): + value = getattr(value, 'name') + print(f' {key}: {value}') - if (save_type): - print(f"Setting save type to [{sc64.get_save_type_label(save_type)}]") - sc64.set_save_type(save_type) + if (args.boot != None): + sc64.set_boot_mode(args.boot) + print(f'Boot mode set to [{args.boot.name}]') - if (tv_type != 3): - print(f"Setting TV type to [{sc64.get_tv_type_label(tv_type)}]") - sc64.set_tv_type(tv_type) + if (args.tv != None): + sc64.set_tv_type(args.tv) + print(f'TV type set to [{args.tv.name}]') - if (cic_seed != 0xFFFF): - print(f"Setting CIC seed to [{hex(cic_seed) if cic_seed != 0xFFFF else 'Unknown'}]") - sc64.set_cic_seed(cic_seed) + if (args.cic != None): + sc64.set_cic_seed(args.cic) + print(f'CIC seed set to [0x{args.cic:X}]') - if (dd_enable): - print(f"Setting 64DD emulation to [{'Enabled' if dd_enable else 'Disabled'}]") - sc64.set_dd_enable(dd_enable) + if (args.rtc): + value = datetime.now() + sc64.set_rtc(value) + print(f'RTC set to [{value.strftime("%Y-%m-%d %H:%M:%S")}]') - if (rom_file): - if (is_read): - if (rom_length > 0): - sc64.download_rom(rom_file, rom_length) - else: - raise SC64Exception("ROM length should be larger than 0") - else: - sc64.upload_rom(rom_file) + if (args.rom): + with open(args.rom, 'rb') as f: + print('Uploading ROM... ', end='', flush=True) + sc64.upload_rom(f.read(), use_shadow=args.no_shadow) + print('done') - if (dd_ipl_file): - if (is_read): - sc64.download_dd_ipl(dd_ipl_file) - else: - sc64.upload_dd_ipl(dd_ipl_file) + if (args.save_type != None): + sc64.set_save_type(args.save_type) + print(f'Save type set to [{args.save_type.name}]') - if (save_file): - if (is_read): - sc64.download_save(save_file) - else: - sc64.upload_save(save_file) + if (args.save): + with open(args.save, 'rb') as f: + print('Uploading save... ', end='', flush=True) + sc64.upload_save(f.read()) + print('done') - if (debug_server): - if (sd_file): - print(f"Using fake SD emulation file [{sd_file}]") - if (disk_file): - print(f"Using 64DD disk image file [{disk_file}]") - sc64.set_dd_configuration_for_disk(disk_file) - if (disk_file): - print(f"Setting 64DD disk state to [Changed]") - sc64.set_dd_disk_state("changed" if disk_file else "ejected") - sc64.debug_loop(sd_file, disk_file) + if (args.ddipl): + with open(args.ddipl, 'rb') as f: + print('Uploading 64DD IPL... ', end='', flush=True) + sc64.upload_ddipl(f.read()) + print('done') - except SC64Exception as e: - print(f"Error: {e}") - parser.exit(1) - except KeyboardInterrupt: - pass - finally: - sc64.reset_link() - if (disk_file): - print(f"Setting 64DD disk state to [Ejected]") - sc64.set_dd_disk_state("ejected") - sys.stdout.write("\033[0m") + if (args.debug): + sc64.debug_loop(isv=args.isv, disks=args.disk) + + if (args.backup_save): + with open(args.backup_save, 'wb') as f: + print('Downloading save... ', end='', flush=True) + f.write(sc64.download_save()) + print('done') + + if (args.download_memory): + with open(args.download_memory, 'wb') as f: + print('Downloading memory... ', end='', flush=True) + f.write(sc64.download_memory()) + print('done') + except ValueError as e: + print(f'\nValue error: {e}') + except ConnectionException as e: + print(f'\nSC64 error: {e}') diff --git a/sw/riscv/.gitignore b/sw/riscv/.gitignore deleted file mode 100644 index 3543521..0000000 --- a/sw/riscv/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/build diff --git a/sw/riscv/SC64.ld b/sw/riscv/SC64.ld deleted file mode 100644 index bae2abd..0000000 --- a/sw/riscv/SC64.ld +++ /dev/null @@ -1,49 +0,0 @@ -MEMORY { - ram (rwx) : org = 0x00000000, len = 16k - rom (rx) : org = 0x10035800, len = 16k -} - -ENTRY(reset_handler) - -SECTIONS { - .text.reset_handler : { - *(.text.reset_handler) - } > rom - - .text : { - _sitext = LOADADDR(.text); - . = ALIGN(4); - _stext = .; - *(.text .text.* .gnu.linkonce.t.*) - *(.rodata .rodata.* .gnu.linkonce.r.*) - . = ALIGN(4); - _etext = .; - } > ram AT > rom - - .data : { - _sidata = LOADADDR(.data); - . = ALIGN(4); - _sdata = .; - *(.data .data.* .gnu.linkonce.d.*) - . = ALIGN(4); - _ssdata = .; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) - *(.sdata .sdata.* .gnu.linkonce.s.*) - . = ALIGN(4); - _edata = .; - } > ram AT > rom - - .bss : { - . = ALIGN(4); - _sbss = .; - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon .scommon.*) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } > ram - - __global_pointer$ = MIN(_ssdata + 0x800, MAX(_sdata + 0x800, _ebss - 0x800)); - __stack_pointer$ = ORIGIN(ram) + LENGTH(ram); -} diff --git a/sw/riscv/src/cfg.c b/sw/riscv/src/cfg.c deleted file mode 100644 index 1232c05..0000000 --- a/sw/riscv/src/cfg.c +++ /dev/null @@ -1,324 +0,0 @@ -#include "cfg.h" -#include "dd.h" -#include "flash.h" -#include "joybus.h" -#include "usb.h" - - -#define SAVE_SIZE_EEPROM_4K (512) -#define SAVE_SIZE_EEPROM_16K (2048) -#define SAVE_SIZE_SRAM (32 * 1024) -#define SAVE_SIZE_FLASHRAM (128 * 1024) -#define SAVE_SIZE_SRAM_BANKED (3 * 32 * 1024) - -#define SAVE_OFFSET_PKST2 (0x01608000UL) - -#define DEFAULT_SAVE_OFFSET (0x03FE0000UL) -#define DEFAULT_DDIPL_OFFSET (0x03BE0000UL) - - -enum cfg_id { - CFG_ID_SCR, - CFG_ID_SDRAM_SWITCH, - CFG_ID_SDRAM_WRITABLE, - CFG_ID_DD_ENABLE, - CFG_ID_SAVE_TYPE, - CFG_ID_CIC_SEED, - CFG_ID_TV_TYPE, - CFG_ID_SAVE_OFFEST, - CFG_ID_DDIPL_OFFEST, - CFG_ID_BOOT_MODE, - CFG_ID_FLASH_SIZE, - CFG_ID_FLASH_READ, - CFG_ID_FLASH_PROGRAM, - CFG_ID_RECONFIGURE, - CFG_ID_DD_SETTING, - CFG_ID_DD_THB_TABLE_OFFSET, -}; - -enum save_type { - SAVE_TYPE_NONE = 0, - SAVE_TYPE_EEPROM_4K = 1, - SAVE_TYPE_EEPROM_16K = 2, - SAVE_TYPE_SRAM = 3, - SAVE_TYPE_FLASHRAM = 4, - SAVE_TYPE_SRAM_BANKED = 5, - SAVE_TYPE_FLASHRAM_PKST2 = 6, -}; - -enum boot_mode { - BOOT_MODE_MENU = 0, - BOOT_MODE_ROM = 1, - BOOT_MODE_DD = 2, - BOOT_MODE_DIRECT = 3, -}; - -enum dd_setting { - DD_SETTING_DISK_EJECTED = 0, - DD_SETTING_DISK_INSERTED = 1, - DD_SETTING_DISK_CHANGED = 2, - DD_SETTING_DRIVE_RETAIL = 3, - DD_SETTING_DRIVE_DEVELOPMENT = 4, - DD_SETTING_SET_BLOCK_READY = 5, -}; - - -struct process { - enum save_type save_type; - uint16_t cic_seed; - uint8_t tv_type; - enum boot_mode boot_mode; -}; - -static struct process p; - - -static void change_scr_bits (uint32_t mask, bool value) { - if (value) { - CFG->SCR |= mask; - } else { - CFG->SCR &= ~(mask); - } -} - -static void set_save_type (enum save_type save_type) { - uint32_t save_offset = DEFAULT_SAVE_OFFSET; - - change_scr_bits(CFG_SCR_FLASHRAM_EN | CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_EN, false); - joybus_set_eeprom(EEPROM_NONE); - - switch (save_type) { - case SAVE_TYPE_NONE: - break; - case SAVE_TYPE_EEPROM_4K: - save_offset = SDRAM_SIZE - SAVE_SIZE_EEPROM_4K; - joybus_set_eeprom(EEPROM_4K); - break; - case SAVE_TYPE_EEPROM_16K: - save_offset = SDRAM_SIZE - SAVE_SIZE_EEPROM_16K; - joybus_set_eeprom(EEPROM_16K); - break; - case SAVE_TYPE_SRAM: - save_offset = SDRAM_SIZE - SAVE_SIZE_SRAM; - change_scr_bits(CFG_SCR_SRAM_EN, true); - break; - case SAVE_TYPE_FLASHRAM: - save_offset = SDRAM_SIZE - SAVE_SIZE_FLASHRAM; - change_scr_bits(CFG_SCR_FLASHRAM_EN, true); - break; - case SAVE_TYPE_SRAM_BANKED: - save_offset = SDRAM_SIZE - SAVE_SIZE_SRAM_BANKED; - change_scr_bits(CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_EN, true); - break; - case SAVE_TYPE_FLASHRAM_PKST2: - save_offset = SAVE_OFFSET_PKST2; - change_scr_bits(CFG_SCR_FLASHRAM_EN, true); - break; - default: - save_type = SAVE_TYPE_NONE; - break; - } - - p.save_type = save_type; - - CFG->SAVE_OFFSET = save_offset; -} - -static void set_dd_setting (enum dd_setting setting) { - switch (setting) { - case DD_SETTING_DISK_EJECTED: - dd_set_disk_state(DD_DISK_EJECTED); - break; - case DD_SETTING_DISK_INSERTED: - dd_set_disk_state(DD_DISK_INSERTED); - break; - case DD_SETTING_DISK_CHANGED: - dd_set_disk_state(DD_DISK_CHANGED); - break; - case DD_SETTING_DRIVE_RETAIL: - dd_set_drive_type_development(false); - break; - case DD_SETTING_DRIVE_DEVELOPMENT: - dd_set_drive_type_development(true); - break; - case DD_SETTING_SET_BLOCK_READY: - dd_set_block_ready(true); - break; - } -} - - -uint32_t cfg_get_version (void) { - return CFG->VERSION; -} - -void cfg_update (uint32_t *args) { - switch (args[0]) { - case CFG_ID_SCR: - CFG->SCR = args[1]; - break; - case CFG_ID_SDRAM_SWITCH: - change_scr_bits(CFG_SCR_SDRAM_SWITCH, args[1]); - break; - case CFG_ID_SDRAM_WRITABLE: - change_scr_bits(CFG_SCR_SDRAM_WRITABLE, args[1]); - break; - case CFG_ID_DD_ENABLE: - change_scr_bits(CFG_SCR_DD_EN, args[1]); - break; - case CFG_ID_SAVE_TYPE: - set_save_type((enum save_type) (args[1])); - break; - case CFG_ID_CIC_SEED: - p.cic_seed = (uint16_t) (args[1] & 0xFFFF); - break; - case CFG_ID_TV_TYPE: - p.tv_type = (uint8_t) (args[1] & 0x03); - break; - case CFG_ID_SAVE_OFFEST: - CFG->SAVE_OFFSET = args[1]; - break; - case CFG_ID_DDIPL_OFFEST: - CFG->DDIPL_OFFSET = args[1]; - break; - case CFG_ID_BOOT_MODE: - p.boot_mode = args[1]; - change_scr_bits(CFG_SCR_SKIP_BOOTLOADER, args[1] == BOOT_MODE_DIRECT); - break; - case CFG_ID_FLASH_READ: - flash_read(args[1]); - break; - case CFG_ID_FLASH_PROGRAM: - flash_program(args[1]); - break; - case CFG_ID_RECONFIGURE: - if (args[1] == CFG->RECONFIGURE) { - CFG->RECONFIGURE = args[1]; - asm volatile ( - "ebreak \n" - ); - } - break; - case CFG_ID_DD_SETTING: - set_dd_setting(args[1]); - break; - } -} - -void cfg_query (uint32_t *args) { - switch (args[0]) { - case CFG_ID_SCR: - args[1] = CFG->SCR; - break; - case CFG_ID_SDRAM_SWITCH: - args[1] = CFG->SCR & CFG_SCR_SDRAM_SWITCH; - break; - case CFG_ID_SDRAM_WRITABLE: - args[1] = CFG->SCR & CFG_SCR_SDRAM_WRITABLE; - break; - case CFG_ID_DD_ENABLE: - args[1] = CFG->SCR & CFG_SCR_DD_EN; - break; - case CFG_ID_SAVE_TYPE: - args[1] = (uint32_t) (p.save_type); - break; - case CFG_ID_CIC_SEED: - args[1] = (uint32_t) (p.cic_seed); - break; - case CFG_ID_TV_TYPE: - args[1] = (uint32_t) (p.tv_type); - break; - case CFG_ID_SAVE_OFFEST: - args[1] = CFG->SAVE_OFFSET; - break; - case CFG_ID_DDIPL_OFFEST: - args[1] = CFG->DDIPL_OFFSET; - break; - case CFG_ID_BOOT_MODE: - args[1] = p.boot_mode; - break; - case CFG_ID_FLASH_SIZE: - args[1] = flash_size(); - break; - case CFG_ID_RECONFIGURE: - args[1] = CFG->RECONFIGURE; - break; - case CFG_ID_DD_THB_TABLE_OFFSET: - args[1] = dd_get_thb_table_offset(); - break; - } -} - - -void cfg_init (void) { - set_save_type(SAVE_TYPE_NONE); - - CFG->DDIPL_OFFSET = DEFAULT_DDIPL_OFFSET; - CFG->SCR = CFG_SCR_CPU_READY | CFG_SCR_SDRAM_SWITCH; - - p.cic_seed = 0xFFFF; - p.tv_type = 0x03; - p.boot_mode = BOOT_MODE_MENU; -} - - -void process_cfg (void) { - uint32_t args[2]; - - if (CFG->SCR & CFG_SCR_CPU_BUSY) { - change_scr_bits(CFG_SCR_CMD_ERROR, false); - - args[0] = CFG->DATA[0]; - args[1] = CFG->DATA[1]; - - switch (CFG->CMD) { - case 'C': - cfg_update(args); - break; - - case 'Q': - cfg_query(args); - break; - - case 'S': - args[0] = usb_debug_tx_ready(); - break; - - case 'D': - if (!usb_debug_tx_data(args[0], (size_t) args[1])) { - change_scr_bits(CFG_SCR_CMD_ERROR, true); - } - break; - - case 'A': - if (!usb_debug_rx_ready(&args[0], (size_t *) (&args[1]))) { - args[0] = 0; - args[1] = 0; - } - break; - - case 'F': - args[0] = usb_debug_rx_busy(); - break; - - case 'E': - if (!usb_debug_rx_data(args[0], (size_t) args[1])) { - change_scr_bits(CFG_SCR_CMD_ERROR, true); - } - break; - - case 'B': - usb_debug_reset(); - break; - - default: - change_scr_bits(CFG_SCR_CMD_ERROR, true); - break; - } - - CFG->DATA[0] = args[0]; - CFG->DATA[1] = args[1]; - - change_scr_bits(CFG_SCR_CPU_BUSY, false); - } -} diff --git a/sw/riscv/src/cfg.h b/sw/riscv/src/cfg.h deleted file mode 100644 index 1312835..0000000 --- a/sw/riscv/src/cfg.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef CFG_H__ -#define CFG_H__ - - -#include "sys.h" - - -uint32_t cfg_get_version (void); -void cfg_update (uint32_t *args); -void cfg_query (uint32_t *args); -void cfg_init (void); -void process_cfg (void); - - -#endif diff --git a/sw/riscv/src/dd.c b/sw/riscv/src/dd.c deleted file mode 100644 index 8ea156c..0000000 --- a/sw/riscv/src/dd.c +++ /dev/null @@ -1,440 +0,0 @@ -#include "dd.h" -#include "rtc.h" -#include "usb.h" - - -#define DD_USER_SECTORS_PER_BLOCK (85) - -#define DD_BUFFERS_OFFSET (SDRAM_BASE + 0x03BD0000UL) -#define DD_THB_TABLE_OFFSET (DD_BUFFERS_OFFSET + 0x0000) -#define DD_USB_BUFFER_OFFSET (DD_BUFFERS_OFFSET + 0x5000) -#define DD_BLOCK_BUFFER_OFFSET (DD_BUFFERS_OFFSET + 0x6000) - -#define USB_DEBUG_ID_DD_BLOCK (0xF5) - -#define DD_DRIVE_ID_RETAIL (0x0003) -#define DD_DRIVE_ID_DEVELOPMENT (0x0004) -#define DD_VERSION_RETAIL (0x0114) - -#define DD_POWER_UP_DELAY_TICKS (200000000UL) // 2 s -#define DD_TRACK_SEEK_TIME_TICKS (10000) // 0.1 ms - - -typedef enum { - DD_CMD_SEEK_READ = 0x01, - DD_CMD_SEEK_WRITE = 0x02, - DD_CMD_CLEAR_DISK_CHANGE = 0x08, - DD_CMD_CLEAR_RESET_STATE = 0x09, - DD_CMD_READ_VERSION = 0x0A, - DD_CMD_SET_DISK_TYPE = 0x0B, - DD_CMD_REQUEST_STATUS = 0x0C, - DD_CMD_SET_RTC_YEAR_MONTH = 0x0F, - DD_CMD_SET_RTC_DAY_HOUR = 0x10, - DD_CMD_SET_RTC_MINUTE_SECOND = 0x11, - DD_CMD_GET_RTC_YEAR_MONTH = 0x12, - DD_CMD_GET_RTC_DAY_HOUR = 0x13, - DD_CMD_GET_RTC_MINUTE_SECOND = 0x14, - DD_CMD_READ_PROGRAM_VERSION = 0x1B, -} dd_cmd_t; - - -enum state { - STATE_IDLE, - STATE_START, - STATE_BLOCK_READ, - STATE_BLOCK_READ_WAIT, - STATE_SECTOR_READ, - STATE_SECTOR_WRITE, - STATE_BLOCK_WRITE, - STATE_BLOCK_WRITE_WAIT, - STATE_NEXT_BLOCK, - STATE_STOP, -}; - -struct process { - enum state state; - uint32_t track_seek_time; - uint32_t next_seek_time; - bool power_up_delay; - bool deffered_cmd_ready; - bool bm_running; - bool transfer_mode; - bool full_track_transfer; - bool starting_block; - uint8_t current_sector; - bool is_dev_disk; - rtc_time_t time; - io32_t *thb_table; - io32_t *usb_buffer; - io32_t *block_buffer; - bool block_ready; -}; - -static struct process p; - - -static uint16_t dd_track_head_block (void) { - uint32_t head_track = DD->HEAD_TRACK; - uint16_t track = ((head_track & DD_TRACK_MASK) << 2); - uint16_t head = (((head_track & DD_HEAD_MASK) ? 1 : 0) << 1); - uint16_t block = (p.starting_block ? 1 : 0); - - return (track | head | block); -} - -static bool dd_block_valid (void) { - return (p.thb_table[dd_track_head_block()] != 0xFFFFFFFF); -} - -static bool dd_block_request (void) { - if (!usb_debug_tx_ready()) { - return false; - } - - if (!(DD->SCR & DD_SCR_DISK_INSERTED)) { - return true; - } - - const char *dma = "DMA@"; - const char *cmp = "CMPH"; - - io32_t offset = p.thb_table[dd_track_head_block()]; - uint32_t length = ((DD->SECTOR_SIZE + 1) * DD_USER_SECTORS_PER_BLOCK); - - io32_t *dst = p.usb_buffer; - - *dst++ = *((uint32_t *) (dma)); - *dst++ = swap32((USB_DEBUG_ID_DD_BLOCK << 24) | 16); - *dst++ = swap32(p.transfer_mode); - *dst++ = swap32((uint32_t) (p.block_buffer)); - *dst++ = offset; - *dst++ = swap32(length); - *dst++ = *((uint32_t *) (cmp)); - - usb_debug_tx_data((uint32_t) (p.usb_buffer), 28); - - p.block_ready = false; - - return true; -} - -static bool dd_block_ready (void) { - return p.block_ready || (!(DD->SCR & DD_SCR_DISK_INSERTED)); -} - -static void dd_sector_read (void) { - io32_t *src = p.block_buffer; - io32_t *dst = DD->SECTOR_BUFFER; - - uint8_t sector_size = ((DD->SECTOR_SIZE + 1) / sizeof(io32_t)); - - src += (sector_size * p.current_sector); - - for (int i = 0; i < sector_size; i++) { - *dst++ = *src++; - } -} - -static void dd_sector_write (void) { - io32_t *src = DD->SECTOR_BUFFER; - io32_t *dst = p.block_buffer; - - uint8_t sector_size = ((DD->SECTOR_SIZE + 1) / sizeof(io32_t)); - - dst += (sector_size * p.current_sector); - - for (int i = 0; i < sector_size; i++) { - *dst++ = *src++; - } -} - - -void dd_set_disk_state (disk_state_t disk_state) { - uint32_t scr = (DD->SCR & (~(DD_SCR_DISK_CHANGED | DD_SCR_DISK_INSERTED))); - - switch (disk_state) { - case DD_DISK_EJECTED: - break; - case DD_DISK_INSERTED: - scr |= DD_SCR_DISK_INSERTED; - break; - case DD_DISK_CHANGED: - scr |= (DD_SCR_DISK_CHANGED | DD_SCR_DISK_INSERTED); - break; - } - - DD->SCR = scr; -} - -void dd_set_drive_type_development (bool value) { - if (value) { - DD->DRIVE_ID = DD_DRIVE_ID_DEVELOPMENT; - p.is_dev_disk = true; - } else { - DD->DRIVE_ID = DD_DRIVE_ID_RETAIL; - p.is_dev_disk = false; - } -} - -void dd_set_block_ready (bool value) { - p.block_ready = value; -} - -uint32_t dd_get_thb_table_offset (void) { - return (((uint32_t) (p.thb_table)) & 0x0FFFFFFF); -} - - -void dd_init (void) { - DD->SCR = 0; - DD->HEAD_TRACK = 0; - DD->DRIVE_ID = DD_DRIVE_ID_RETAIL; - p.state = STATE_IDLE; - p.track_seek_time = DD_TRACK_SEEK_TIME_TICKS; - p.power_up_delay = true; - p.deffered_cmd_ready = false; - p.bm_running = false; - p.is_dev_disk = false; - p.thb_table = (io32_t *) (DD_THB_TABLE_OFFSET); - p.usb_buffer = (io32_t *) (DD_USB_BUFFER_OFFSET); - p.block_buffer = (io32_t *) (DD_BLOCK_BUFFER_OFFSET); -} - - -void process_dd (void) { - uint32_t scr = DD->SCR; - - if (scr & DD_SCR_HARD_RESET) { - DD->SCR &= ~(DD_SCR_DISK_CHANGED); - DD->HEAD_TRACK = 0; - p.state = STATE_IDLE; - p.power_up_delay = true; - p.deffered_cmd_ready = false; - p.bm_running = false; - } - - if (scr & DD_SCR_CMD_PENDING) { - dd_cmd_t cmd = DD->CMD; - uint16_t data = DD->DATA; - - DD->DATA = data; - - if (p.deffered_cmd_ready) { - if (DD->SEEK_TIMER >= p.next_seek_time) { - p.deffered_cmd_ready = false; - DD->HEAD_TRACK = DD_HEAD_TRACK_INDEX_LOCK | data; - DD->SCR |= DD_SCR_CMD_READY; - } - } else if ((cmd == DD_CMD_SEEK_READ) || (cmd == DD_CMD_SEEK_WRITE)) { - int track_distance = abs((DD->HEAD_TRACK & DD_TRACK_MASK) - (data & DD_TRACK_MASK)); - if (p.power_up_delay) { - p.power_up_delay = false; - p.next_seek_time = DD_POWER_UP_DELAY_TICKS; - } else { - p.next_seek_time = (track_distance * p.track_seek_time); - } - p.deffered_cmd_ready = true; - DD->HEAD_TRACK &= ~(DD_HEAD_TRACK_INDEX_LOCK); - DD->SCR |= DD_SCR_SEEK_TIMER_RESET; - } else { - switch (cmd) { - case DD_CMD_CLEAR_DISK_CHANGE: - DD->SCR &= ~(DD_SCR_DISK_CHANGED); - break; - - case DD_CMD_CLEAR_RESET_STATE: - DD->SCR &= ~(DD_SCR_DISK_CHANGED); - DD->SCR |= DD_SCR_HARD_RESET_CLEAR; - break; - - case DD_CMD_READ_VERSION: - DD->DATA = DD_VERSION_RETAIL; - break; - - case DD_CMD_SET_DISK_TYPE: - break; - - case DD_CMD_REQUEST_STATUS: - DD->DATA = 0; - break; - - case DD_CMD_SET_RTC_YEAR_MONTH: - p.time.year = ((data >> 8) & 0xFF); - p.time.month = (data & 0xFF); - break; - - case DD_CMD_SET_RTC_DAY_HOUR: - p.time.day = ((data >> 8) & 0xFF); - p.time.hour = (data & 0xFF); - break; - - case DD_CMD_SET_RTC_MINUTE_SECOND: - p.time.minute = ((data >> 8) & 0xFF); - p.time.second = (data & 0xFF); - rtc_set_time(&p.time); - break; - - case DD_CMD_GET_RTC_YEAR_MONTH: - DD->DATA = ((p.time.year << 8) | p.time.month); - break; - - case DD_CMD_GET_RTC_DAY_HOUR: - DD->DATA = ((p.time.day << 8) | p.time.hour); - break; - - case DD_CMD_GET_RTC_MINUTE_SECOND: - p.time = *rtc_get_time(); - DD->DATA = ((p.time.minute << 8) | p.time.second); - break; - - case DD_CMD_READ_PROGRAM_VERSION: - DD->DATA = 0; - break; - - default: - break; - } - - DD->SCR |= DD_SCR_CMD_READY; - } - } else { - if (scr & DD_SCR_BM_STOP) { - DD->SCR |= DD_SCR_BM_STOP_CLEAR; - DD->SCR &= ~(DD_SCR_BM_MICRO_ERROR | DD_SCR_BM_TRANSFER_C2 | DD_SCR_BM_TRANSFER_DATA); - p.state = STATE_STOP; - } else if (scr & DD_SCR_BM_START) { - DD->SCR |= DD_SCR_BM_CLEAR | DD_SCR_BM_ACK_CLEAR | DD_SCR_BM_START_CLEAR; - DD->SCR &= ~(DD_SCR_BM_MICRO_ERROR | DD_SCR_BM_TRANSFER_C2 | DD_SCR_BM_TRANSFER_DATA); - p.state = STATE_START; - p.transfer_mode = (scr & DD_SCR_BM_TRANSFER_MODE); - p.full_track_transfer = (scr & DD_SCR_BM_TRANSFER_BLOCKS); - p.starting_block = (DD->SECTOR_NUM == (DD->SECTORS_IN_BLOCK + 1)); - } else if (p.bm_running) { - if (scr & DD_SCR_BM_PENDING) { - DD->SCR |= DD_SCR_BM_CLEAR; - if (p.transfer_mode) { - if (p.current_sector < (DD->SECTORS_IN_BLOCK - 4)) { - p.state = STATE_SECTOR_READ; - } else if (p.current_sector == (DD->SECTORS_IN_BLOCK - 4)) { - p.current_sector += 1; - DD->SCR &= ~(DD_SCR_BM_TRANSFER_DATA); - DD->SCR |= DD_SCR_BM_READY; - } else if (p.current_sector == DD->SECTORS_IN_BLOCK) { - p.state = STATE_NEXT_BLOCK; - } - } else { - if (p.current_sector < (DD->SECTORS_IN_BLOCK - 4)) { - p.state = STATE_SECTOR_WRITE; - } - } - } - if (scr & DD_SCR_BM_ACK) { - DD->SCR |= DD_SCR_BM_ACK_CLEAR; - if (p.transfer_mode) { - if ((p.current_sector <= (DD->SECTORS_IN_BLOCK - 4))) { - } else if (p.current_sector < (DD->SECTORS_IN_BLOCK - 1)) { - p.current_sector += 1; - DD->SCR |= DD_SCR_BM_READY; - } else if (p.current_sector < DD->SECTORS_IN_BLOCK) { - p.current_sector += 1; - DD->SCR |= DD_SCR_BM_TRANSFER_C2 | DD_SCR_BM_READY; - } - } else { - if (p.current_sector == (DD->SECTORS_IN_BLOCK - 4)) { - p.state = STATE_STOP; - } - } - } - } - } - - switch (p.state) { - case STATE_IDLE: - break; - - case STATE_START: - p.bm_running = true; - p.current_sector = 0; - if (p.transfer_mode) { - if (dd_block_valid()) { - p.state = STATE_BLOCK_READ; - DD->SCR |= DD_SCR_BM_TRANSFER_DATA; - } else { - p.state = STATE_SECTOR_READ; - DD->SCR |= DD_SCR_BM_MICRO_ERROR; - } - } else { - p.state = STATE_IDLE; - if (dd_block_valid()) { - DD->SCR |= DD_SCR_BM_TRANSFER_DATA | DD_SCR_BM_READY; - } else { - DD->SCR |= DD_SCR_BM_MICRO_ERROR | DD_SCR_BM_READY; - } - } - break; - - case STATE_BLOCK_READ: - if (dd_block_request()) { - p.state = STATE_BLOCK_READ_WAIT; - } - break; - - case STATE_BLOCK_READ_WAIT: - if (dd_block_ready()) { - p.state = STATE_SECTOR_READ; - } - break; - - case STATE_SECTOR_READ: - dd_sector_read(); - p.state = STATE_IDLE; - p.current_sector += 1; - DD->SCR |= DD_SCR_BM_READY; - break; - - case STATE_SECTOR_WRITE: - dd_sector_write(); - p.current_sector += 1; - if (p.current_sector < (DD->SECTORS_IN_BLOCK - 4)) { - p.state = STATE_IDLE; - DD->SCR |= DD_SCR_BM_READY; - } else { - p.state = STATE_BLOCK_WRITE; - } - break; - - case STATE_BLOCK_WRITE: - if (dd_block_request()) { - p.state = STATE_BLOCK_WRITE_WAIT; - } - break; - - case STATE_BLOCK_WRITE_WAIT: - if (dd_block_ready()) { - p.state = STATE_NEXT_BLOCK; - } - break; - - case STATE_NEXT_BLOCK: - if (p.full_track_transfer) { - p.state = STATE_START; - p.full_track_transfer = false; - p.starting_block = !p.starting_block; - DD->SCR &= ~(DD_SCR_BM_TRANSFER_C2); - } else { - if (p.transfer_mode) { - p.state = STATE_STOP; - } else { - p.state = STATE_IDLE; - DD->SCR &= ~(DD_SCR_BM_TRANSFER_C2 | DD_SCR_BM_TRANSFER_DATA); - DD->SCR |= DD_SCR_BM_READY; - } - } - break; - - case STATE_STOP: - p.state = STATE_IDLE; - p.bm_running = false; - break; - } -} diff --git a/sw/riscv/src/dd.h b/sw/riscv/src/dd.h deleted file mode 100644 index 18a79c0..0000000 --- a/sw/riscv/src/dd.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef DD_H__ -#define DD_H__ - - -#include "sys.h" - - -typedef enum { - DD_DISK_EJECTED, - DD_DISK_INSERTED, - DD_DISK_CHANGED, -} disk_state_t; - - -void dd_set_disk_state (disk_state_t disk_state); -void dd_set_drive_type_development (bool value); -void dd_set_block_ready (bool value); -uint32_t dd_get_thb_table_offset (void); -void dd_init (void); -void process_dd (void); - - -#endif diff --git a/sw/riscv/src/dma.c b/sw/riscv/src/dma.c deleted file mode 100644 index 243a558..0000000 --- a/sw/riscv/src/dma.c +++ /dev/null @@ -1,21 +0,0 @@ -#include "dma.h" - - -bool dma_busy (void) { - return DMA->SCR & DMA_SCR_BUSY; -} - -void dma_start (uint32_t memory_address, size_t length, enum dma_id id, enum dma_dir dir) { - DMA->MADDR = memory_address; - DMA->ID_LEN = ((id & 0x03) << 30) | (length & 0x3FFFFFFF); - DMA->SCR = ((dir == DMA_DIR_TO_SDRAM) ? DMA_SCR_DIR : 0) | DMA_SCR_START; -} - -void dma_stop (void) { - DMA->SCR = DMA_SCR_STOP; -} - - -void dma_init (void) { - dma_stop(); -} diff --git a/sw/riscv/src/dma.h b/sw/riscv/src/dma.h deleted file mode 100644 index 75462a7..0000000 --- a/sw/riscv/src/dma.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef DMA_H__ -#define DMA_H__ - - -#include "sys.h" - - -enum dma_dir { - DMA_DIR_TO_SDRAM, - DMA_DIR_FROM_SDRAM, -}; - -enum dma_id { - DMA_ID_USB = 0, - DMA_ID_SD = 1, -}; - - -bool dma_busy (void); -void dma_start (uint32_t memory_address, size_t length, enum dma_id id, enum dma_dir dir); -void dma_stop (void); -void dma_init (void); - - -#endif diff --git a/sw/riscv/src/flash.c b/sw/riscv/src/flash.c deleted file mode 100644 index 4c7e957..0000000 --- a/sw/riscv/src/flash.c +++ /dev/null @@ -1,62 +0,0 @@ -#include "flash.h" - - -uint32_t flash_size (void) { - return FLASH_SIZE; -} - -void flash_read (uint32_t sdram_offset) { - io32_t *flash = (io32_t *) (FLASH_BASE); - io32_t *sdram = (io32_t *) (SDRAM_BASE + sdram_offset); - - for (size_t i = 0; i < FLASH_SIZE; i += 4) { - *sdram++ = *flash++; - } -} - -void flash_program (uint32_t sdram_offset) { - uint32_t cr; - - io32_t *flash = (io32_t *) (FLASH_BASE); - io32_t *sdram = (io32_t *) (SDRAM_BASE + sdram_offset); - - cr = FLASH_CONFIG->CR; - for (size_t sector = 0; sector < FLASH_NUM_SECTORS; sector++) { - cr &= ~(1 << (FLASH_CR_WRITE_PROTECT_BIT + sector)); - } - FLASH_CONFIG->CR = cr; - - while ((FLASH_CONFIG->SR & FLASH_SR_STATUS_MASK) != FLASH_SR_STATUS_IDLE); - - for (size_t sector = 0; sector < FLASH_NUM_SECTORS; sector++) { - cr = FLASH_CONFIG->CR; - cr &= ~(FLASH_CR_SECTOR_ERASE_MASK); - cr |= ((sector + 1) << FLASH_CR_SECTOR_ERASE_BIT); - FLASH_CONFIG->CR = cr; - - while ((FLASH_CONFIG->SR & FLASH_SR_STATUS_MASK) == FLASH_SR_STATUS_BUSY_ERASE); - - if (!(FLASH_CONFIG->SR & FLASH_SR_ERASE_SUCCESSFUL)) { - break; - } - } - - if (FLASH_CONFIG->SR & FLASH_SR_ERASE_SUCCESSFUL) { - for (size_t word = 0; word < FLASH_SIZE; word += 4) { - *flash++ = *sdram++; - - if (!(FLASH_CONFIG->SR & FLASH_SR_WRITE_SUCCESSFUL)) { - break; - } - } - } - - cr = FLASH_CONFIG->CR; - cr |= FLASH_CR_SECTOR_ERASE_MASK; - for (size_t sector = 0; sector < FLASH_NUM_SECTORS; sector++) { - cr |= (1 << (FLASH_CR_WRITE_PROTECT_BIT + sector)); - } - FLASH_CONFIG->CR = cr; - - return; -} diff --git a/sw/riscv/src/flash.h b/sw/riscv/src/flash.h deleted file mode 100644 index 89de167..0000000 --- a/sw/riscv/src/flash.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef FLASH_H__ -#define FLASH_H__ - - -#include "sys.h" - - -uint32_t flash_size(void); -void flash_read (uint32_t sdram_offset); -void flash_program (uint32_t sdram_offset); - - -#endif diff --git a/sw/riscv/src/flashram.c b/sw/riscv/src/flashram.c deleted file mode 100644 index 02c5b5a..0000000 --- a/sw/riscv/src/flashram.c +++ /dev/null @@ -1,92 +0,0 @@ -#include "flashram.h" - - -#define FLASHRAM_SIZE (128 * 1024) -#define FLASHRAM_SECTOR_SIZE (16 * 1024) -#define FLASHRAM_PAGE_SIZE (128) -#define FLASHRAM_ERASE_VALUE (0xFFFFFFFF) - -enum operation { - OP_NONE, - OP_ERASE_ALL, - OP_ERASE_SECTOR, - OP_WRITE_PAGE -}; - - -struct process { - bool save_in_progress; - enum operation op; - io32_t *save_pointer; - uint32_t num_words; - uint32_t current_word; -}; - -static struct process p; - - -static enum operation get_operation_type (void) { - uint32_t scr = FLASHRAM->SCR; - - if (!(scr & FLASHRAM_OPERATION_PENDING)) { - return OP_NONE; - } - - if (scr & FLASHRAM_WRITE_OR_ERASE) { - if (scr & FLASHRAM_SECTOR_OR_ALL) { - return OP_ERASE_ALL; - } else { - return OP_ERASE_SECTOR; - } - } else { - return OP_WRITE_PAGE; - } -} - -static size_t get_operation_length (enum operation op) { - switch (op) { - case OP_ERASE_ALL: return FLASHRAM_SIZE; - case OP_ERASE_SECTOR: return FLASHRAM_SECTOR_SIZE; - case OP_WRITE_PAGE: return FLASHRAM_PAGE_SIZE; - default: return 0; - } -} - - -void flashram_init (void) { - FLASHRAM->SCR = FLASHRAM_OPERATION_DONE; - - p.save_in_progress = false; -} - - -void process_flashram (void) { - if (!p.save_in_progress) { - p.op = get_operation_type(); - - if (p.op != OP_NONE) { - uint32_t sdram_address = SDRAM_BASE + CFG->SAVE_OFFSET; - - p.save_in_progress = true; - if (p.op != OP_ERASE_ALL) { - sdram_address += (FLASHRAM->SCR >> FLASHRAM_PAGE_BIT) * FLASHRAM_PAGE_SIZE; - } - p.save_pointer = (io32_t *) (sdram_address); - p.num_words = get_operation_length(p.op) / sizeof(uint32_t); - p.current_word = 0; - } - } else { - if (p.op == OP_WRITE_PAGE) { - *p.save_pointer++ &= FLASHRAM->BUFFER[p.current_word]; - } else { - *p.save_pointer++ = FLASHRAM_ERASE_VALUE; - } - - p.current_word += 1; - - if (p.current_word >= p.num_words) { - p.save_in_progress = false; - FLASHRAM->SCR = FLASHRAM_OPERATION_DONE; - } - } -} diff --git a/sw/riscv/src/i2c.c b/sw/riscv/src/i2c.c deleted file mode 100644 index fd34472..0000000 --- a/sw/riscv/src/i2c.c +++ /dev/null @@ -1,113 +0,0 @@ -#include "i2c.h" - - -enum phase { - PHASE_START, - PHASE_ADDRESS, - PHASE_DATA, - PHASE_STOP, -}; - -struct process { - enum phase phase; - uint8_t address; - uint8_t *data; - uint8_t length; - bool write; - bool generate_stop; - bool first_byte_transferred; - bool busy; - bool done; - bool failed; -}; - -static struct process p; - - -bool i2c_busy (void) { - return p.busy; -} - -bool i2c_done (void) { - return p.done; -} - -bool i2c_failed (void) { - return p.failed; -} - -void i2c_trx (uint8_t address, uint8_t *data, uint8_t length, bool write, bool generate_stop) { - p.phase = PHASE_START; - p.address = address; - p.data = data; - p.length = length; - p.write = write; - p.generate_stop = generate_stop; - p.first_byte_transferred = false; - p.busy = true; - p.done = false; - p.failed = false; -} - - -void i2c_init (void) { - I2C->SCR = I2C_SCR_STOP; - p.busy = false; - p.done = false; - p.failed = false; -} - - -void process_i2c (void) { - if (p.busy && (!(I2C->SCR & I2C_SCR_BUSY))) { - switch (p.phase) { - case PHASE_START: - I2C->SCR = I2C_SCR_START; - p.phase = PHASE_ADDRESS; - break; - - case PHASE_ADDRESS: - I2C->SCR = 0; - I2C->DR = p.address | (p.write ? 0 : (1 << 0)); - p.phase = PHASE_DATA; - break; - - case PHASE_DATA: - if (p.write) { - p.failed |= (!(I2C->SCR & I2C_SCR_ACK)); - I2C->DR = *p.data++; - if (p.length == 1) { - if (p.generate_stop) { - p.phase = PHASE_STOP; - } else { - p.busy = false; - p.done = true; - } - } - } else { - if (p.first_byte_transferred) { - *(p.data++) = I2C->DR; - } - if (p.length >= 1) { - I2C->SCR = (p.length > 1) ? I2C_SCR_MACK : 0; - I2C->DR = 0xFF; - p.first_byte_transferred = true; - } - if (p.length == 0) { - p.phase = PHASE_STOP; - } - } - p.length -= 1; - break; - - case PHASE_STOP: - if (p.write) { - p.failed |= (!(I2C->SCR & I2C_SCR_ACK)); - } - I2C->SCR = I2C_SCR_STOP; - p.busy = false; - p.done = true; - break; - } - } -} diff --git a/sw/riscv/src/i2c.h b/sw/riscv/src/i2c.h deleted file mode 100644 index 8869685..0000000 --- a/sw/riscv/src/i2c.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef I2C_H__ -#define I2C_H__ - - -#include "sys.h" - - -bool i2c_busy (void); -bool i2c_done (void); -bool i2c_failed (void); -void i2c_trx (uint8_t address, uint8_t *data, uint8_t length, bool write, bool generate_stop); -void i2c_init (void); -void process_i2c (void); - - -#endif diff --git a/sw/riscv/src/joybus.c b/sw/riscv/src/joybus.c deleted file mode 100644 index 2e93af1..0000000 --- a/sw/riscv/src/joybus.c +++ /dev/null @@ -1,160 +0,0 @@ -#include "joybus.h" -#include "rtc.h" - - -#define CMD_EEPROM_STATUS (0x00) -#define CMD_EEPROM_READ (0x04) -#define CMD_EEPROM_WRITE (0x05) -#define CMD_RTC_STATUS (0x06) -#define CMD_RTC_READ (0x07) -#define CMD_RTC_WRITE (0x08) - -#define EEPROM_ID_4K (0x80) -#define EEPROM_ID_16K (0xC0) -#define RTC_ID (0x10) - -#define EEPROM_PAGE_SIZE (8) - -#define RTC_STATUS_STOPPED (0x80) -#define RTC_STATUS_RUNNING (0x00) -#define RTC_STATUS(running) (running ? RTC_STATUS_RUNNING : RTC_STATUS_STOPPED) - -#define RTC_BLOCK_CFG (0) -#define RTC_BLOCK_BACKUP (1) -#define RTC_BLOCK_TIME (2) - -#define RTC_WP_BACKUP (1 << 0) -#define RTC_WP_TIME (1 << 1) -#define RTC_WP_MASK (RTC_WP_TIME | RTC_WP_BACKUP) -#define RTC_ST (1 << 2) -#define RTC_CENTURY_20XX (0x01) - - -static void joybus_rx (uint8_t *data) { - size_t rx_length = (JOYBUS->SCR & JOYBUS_SCR_RX_LENGTH_MASK) >> JOYBUS_SCR_RX_LENGTH_BIT; - for (size_t i = 0; i < rx_length; i++) { - data[i] = ((uint8_t *) (JOYBUS->DATA))[(10 - rx_length) + i]; - } -} - -static void joybus_tx (uint8_t *data, size_t length) { - for (size_t i = 0; i < ((length + 3) / 4); i++) { - JOYBUS->DATA[i] = ((uint32_t *) (data))[i]; - } - JOYBUS->SCR = ((length * 8) << JOYBUS_SCR_TX_LENGTH_BIT) | JOYBUS_SCR_TX_START; -} - - -struct process { - enum eeprom_type eeprom_type; - bool rtc_running; - uint8_t rtc_write_protect; -}; - -static struct process p; - - -void joybus_set_eeprom (enum eeprom_type eeprom_type) { - p.eeprom_type = eeprom_type; -} - - -void joybus_init (void) { - JOYBUS->SCR = JOYBUS_SCR_TX_RESET | JOYBUS_SCR_RX_RESET; - - p.eeprom_type = EEPROM_NONE; - p.rtc_running = true; - p.rtc_write_protect = RTC_WP_MASK; -} - - -void process_joybus (void) { - uint8_t rx_data[10]; - uint8_t tx_data[12]; - io32_t *save_data; - uint32_t *data_offset; - - if (JOYBUS->SCR & JOYBUS_SCR_RX_READY) { - if (JOYBUS->SCR & JOYBUS_SCR_RX_STOP_BIT) { - joybus_rx(rx_data); - - for (size_t i = 0; i < sizeof(tx_data); i++) { - tx_data[i] = 0x00; - } - - if (p.eeprom_type != EEPROM_NONE) { - save_data = (io32_t *) (SDRAM_BASE + CFG->SAVE_OFFSET + (rx_data[1] * EEPROM_PAGE_SIZE)); - switch (rx_data[0]) { - case CMD_EEPROM_STATUS: - tx_data[1] = p.eeprom_type == EEPROM_16K ? EEPROM_ID_16K : EEPROM_ID_4K; - joybus_tx(tx_data, 3); - break; - - case CMD_EEPROM_READ: - data_offset = (uint32_t *) (&tx_data[0]); - data_offset[0] = save_data[0]; - data_offset[1] = save_data[1]; - joybus_tx(tx_data, 8); - break; - - case CMD_EEPROM_WRITE: - data_offset = (uint32_t *) (&rx_data[2]); - save_data[0] = data_offset[0]; - save_data[1] = data_offset[1]; - joybus_tx(tx_data, 1); - break; - } - } - - switch (rx_data[0]) { - case CMD_RTC_STATUS: - tx_data[1] = RTC_ID; - tx_data[2] = RTC_STATUS(p.rtc_running); - joybus_tx(tx_data, 3); - break; - - case CMD_RTC_READ: - if (rx_data[1] == RTC_BLOCK_CFG) { - tx_data[0] = p.rtc_write_protect; - if (!p.rtc_running) { - tx_data[1] = RTC_ST; - } - } else if (rx_data[1] == RTC_BLOCK_TIME) { - rtc_time_t *rtc_time = rtc_get_time(); - tx_data[0] = rtc_time->second; - tx_data[1] = rtc_time->minute; - tx_data[2] = rtc_time->hour | 0x80; - tx_data[4] = rtc_time->weekday - 1; - tx_data[3] = rtc_time->day; - tx_data[5] = rtc_time->month; - tx_data[6] = rtc_time->year; - tx_data[7] = RTC_CENTURY_20XX; - } - tx_data[8] = RTC_STATUS(p.rtc_running); - joybus_tx(tx_data, 9); - break; - - case CMD_RTC_WRITE: - if (rx_data[1] == RTC_BLOCK_CFG) { - p.rtc_write_protect = rx_data[2] & RTC_WP_MASK; - p.rtc_running = (!(rx_data[3] & RTC_ST)); - } else if (rx_data[1] == RTC_BLOCK_TIME && (!(p.rtc_write_protect & RTC_WP_TIME))) { - rtc_time_t rtc_time; - rtc_time.second = rx_data[2]; - rtc_time.minute = rx_data[3]; - rtc_time.hour = rx_data[4] & 0x7F; - rtc_time.weekday = rx_data[6] + 1; - rtc_time.day = rx_data[5]; - rtc_time.month = rx_data[7]; - rtc_time.year = rx_data[8]; - rtc_set_time(&rtc_time); - } - tx_data[0] = RTC_STATUS(p.rtc_running); - joybus_tx(tx_data, 1); - break; - } - } - - JOYBUS->SCR = JOYBUS_SCR_RX_RESET; - } -} diff --git a/sw/riscv/src/joybus.h b/sw/riscv/src/joybus.h deleted file mode 100644 index ef2d21f..0000000 --- a/sw/riscv/src/joybus.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef JOYBUS_H__ -#define JOYBUS_H__ - - -#include "sys.h" - - -enum eeprom_type { - EEPROM_NONE, - EEPROM_4K, - EEPROM_16K, -}; - - -void joybus_init (void); -void joybus_set_eeprom (enum eeprom_type eeprom_type); -void process_joybus (void); - - -#endif diff --git a/sw/riscv/src/process.c b/sw/riscv/src/process.c deleted file mode 100644 index 5e899d7..0000000 --- a/sw/riscv/src/process.c +++ /dev/null @@ -1,45 +0,0 @@ -#include "process.h" -#include "usb.h" -#include "cfg.h" -#include "dma.h" -#include "joybus.h" -#include "rtc.h" -#include "i2c.h" -#include "flashram.h" -#include "dd.h" -#include "uart.h" - - -static const void (*process_table[])(void) = { - process_usb, - process_cfg, - process_rtc, - process_i2c, - process_flashram, - process_dd, - process_uart, - NULL, -}; - - -__attribute__((naked)) void process_loop (void) { - void (**process_func)(void) = process_table; - - usb_init(); - cfg_init(); - dma_init(); - joybus_init(); - rtc_init(); - i2c_init(); - flashram_init(); - dd_init(); - uart_init(); - - while (1) { - process_joybus(); - (*process_func++)(); - if (*process_func == NULL) { - process_func = process_table; - } - } -} diff --git a/sw/riscv/src/process.h b/sw/riscv/src/process.h deleted file mode 100644 index e0df2a1..0000000 --- a/sw/riscv/src/process.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef PROCESS_H__ -#define PROCESS_H__ - - -void process_init (void); -void process_loop (void); - - -#endif diff --git a/sw/riscv/src/rtc.c b/sw/riscv/src/rtc.c deleted file mode 100644 index 4c203c2..0000000 --- a/sw/riscv/src/rtc.c +++ /dev/null @@ -1,231 +0,0 @@ -#include "rtc.h" -#include "i2c.h" - - -enum rtc_regs { - RTCSEC, - RTCMIN, - RTCHOUR, - RTCWKDAY, - RTCDATE, - RTCMTH, - RTCYEAR, -}; - -#define RTC_I2C_ADDR (0xDE) - -#define RTCSEC_ST (1 << 7) -#define RTCWKDAY_OSCRUN (1 << 5) -#define RTCWKDAY_VBAT (1 << 3) - - -enum rtc_phase { - RTC_PHASE_READ_START, - RTC_PHASE_READ_READY, - RTC_PHASE_STOP, - RTC_PHASE_WAIT_STOP, - RTC_PHASE_UPDATE, - RTC_PHASE_START, - RTC_PHASE_WAIT_START, -}; - -enum i2c_phase { - I2C_PHASE_IDLE, - I2C_PHASE_ADDR, - I2C_PHASE_DATA, - I2C_PHASE_READY, -}; - - -struct process { - enum rtc_phase rtc_phase; - uint8_t data[7]; - bool running; - rtc_time_t time; - bool time_valid; - bool new_time_valid; - - enum i2c_phase i2c_phase; - bool i2c_pending; - bool i2c_write; - uint8_t i2c_address; - uint8_t i2c_length; - bool i2c_first_read_done; -}; - -static struct process p; - - -static const uint8_t rtc_regs_bit_mask[7] = { - 0b01111111, - 0b01111111, - 0b00111111, - 0b00000111, - 0b00111111, - 0b00011111, - 0b11111111 -}; - -static void sanitize_time (uint8_t *data) { - for (int i = 0; i < 7; i++) { - data[i] &= rtc_regs_bit_mask[i]; - } -} - - -rtc_time_t *rtc_get_time (void) { - return &p.time; -} - -bool rtc_is_time_valid (void) { - return p.time_valid; -} - -bool rtc_is_time_running (void) { - return p.running; -} - -void rtc_set_time (rtc_time_t *time) { - p.time.second = time->second; - p.time.minute = time->minute; - p.time.hour = time->hour; - p.time.weekday = time->weekday; - p.time.day = time->day; - p.time.month = time->month; - p.time.year = time->year; - p.new_time_valid = true; -} - - -void rtc_init (void) { - p.rtc_phase = RTC_PHASE_READ_START; - p.running = false; - p.time_valid = false; - p.new_time_valid = false; - - p.i2c_phase = I2C_PHASE_IDLE; - p.i2c_pending = false; -} - - -void process_rtc (void) { - if (p.i2c_phase == I2C_PHASE_IDLE) { - switch (p.rtc_phase) { - case RTC_PHASE_READ_START: - p.i2c_pending = true; - p.i2c_write = false; - p.i2c_address = RTCSEC; - p.i2c_length = sizeof(p.data); - p.rtc_phase = RTC_PHASE_READ_READY; - break; - - case RTC_PHASE_READ_READY: - p.time_valid = (!i2c_failed()); - if (p.new_time_valid) { - p.rtc_phase = RTC_PHASE_STOP; - break; - } else if (p.time_valid) { - p.running = p.data[RTCSEC] & RTCSEC_ST; - sanitize_time(p.data); - p.time.second = p.data[RTCSEC]; - p.time.minute = p.data[RTCMIN]; - p.time.hour = p.data[RTCHOUR]; - p.time.weekday = p.data[RTCWKDAY]; - p.time.day = p.data[RTCDATE]; - p.time.month = p.data[RTCMTH]; - p.time.year = p.data[RTCYEAR]; - } - p.rtc_phase = RTC_PHASE_READ_START; - break; - - case RTC_PHASE_STOP: - p.i2c_pending = true; - p.i2c_write = true; - p.i2c_length = 2; - p.i2c_first_read_done = false; - p.data[0] = RTCSEC; - p.data[1] = 0x00; - p.rtc_phase = RTC_PHASE_WAIT_STOP; - break; - - case RTC_PHASE_WAIT_STOP: - if (p.i2c_first_read_done) { - if (!(p.data[0] & RTCWKDAY_OSCRUN)) { - p.rtc_phase = RTC_PHASE_UPDATE; - break; - } - } - p.i2c_pending = true; - p.i2c_write = false; - p.i2c_address = RTCWKDAY; - p.i2c_length = 1; - p.i2c_first_read_done = true; - break; - - case RTC_PHASE_UPDATE: - sanitize_time((uint8_t *)(&p.time)); - p.i2c_pending = true; - p.i2c_write = true; - p.i2c_length = 7; - p.data[0] = RTCMIN; - p.data[1] = p.time.minute; - p.data[2] = p.time.hour; - p.data[3] = p.time.weekday | RTCWKDAY_VBAT; - p.data[4] = p.time.day; - p.data[5] = p.time.month; - p.data[6] = p.time.year; - p.rtc_phase = RTC_PHASE_START; - break; - - case RTC_PHASE_START: - p.i2c_pending = true; - p.i2c_write = true; - p.i2c_length = 2; - p.i2c_first_read_done = false; - p.data[0] = RTCSEC; - p.data[1] = p.time.second | RTCSEC_ST; - p.rtc_phase = RTC_PHASE_WAIT_START; - break; - - case RTC_PHASE_WAIT_START: - if (p.i2c_first_read_done) { - if (p.data[0] & RTCWKDAY_OSCRUN) { - p.new_time_valid = false; - p.rtc_phase = RTC_PHASE_READ_START; - break; - } - } - p.i2c_pending = true; - p.i2c_write = false; - p.i2c_address = RTCWKDAY; - p.i2c_length = 1; - p.i2c_first_read_done = true; - break; - } - } - - if (!i2c_busy()) { - switch (p.i2c_phase) { - case I2C_PHASE_IDLE: - if (p.i2c_pending) { - p.i2c_pending = false; - p.i2c_phase = p.i2c_write ? I2C_PHASE_DATA : I2C_PHASE_ADDR; - } - break; - - case I2C_PHASE_ADDR: - i2c_trx(RTC_I2C_ADDR, &p.i2c_address, 1, true, false); - p.i2c_phase = I2C_PHASE_DATA; - break; - - case I2C_PHASE_DATA: - i2c_trx(RTC_I2C_ADDR, p.data, p.i2c_length, p.i2c_write, true); - p.i2c_phase = I2C_PHASE_READY; - break; - - case I2C_PHASE_READY: - p.i2c_phase = I2C_PHASE_IDLE; - break; - } - } -} diff --git a/sw/riscv/src/startup.S b/sw/riscv/src/startup.S deleted file mode 100644 index c7ccf90..0000000 --- a/sw/riscv/src/startup.S +++ /dev/null @@ -1,47 +0,0 @@ -.section .text.reset_handler -reset_handler: - .global reset_handler - - .option push - .option norelax - la gp, __global_pointer$ - .option pop - - la sp, __stack_pointer$ - -init_text: - la a0, _sitext - la a1, _stext - la a2, _etext - call copy_section - -init_data: - la a0, _sidata - la a1, _sdata - la a2, _edata - call copy_section - -init_bss: - la a0, _sbss - la a1, _ebss - bge a0, a1, 2f -1: - sw zero, 0(a0) - addi a0, a0, 4 - blt a0, a1, 1b -2: - -run_in_ram: - la ra, process_loop - jalr zero, 0(ra) - -copy_section: - bge a1, a2, 2f -1: - lw a3, 0(a0) - sw a3, 0(a1) - addi a0, a0, 4 - addi a1, a1, 4 - blt a1, a2, 1b -2: - ret diff --git a/sw/riscv/src/sys.h b/sw/riscv/src/sys.h deleted file mode 100644 index f0ed845..0000000 --- a/sw/riscv/src/sys.h +++ /dev/null @@ -1,251 +0,0 @@ -#ifndef SYS_H__ -#define SYS_H__ - - -#include -#include -#include -#include - - -#define swap32(x) ((((x) & 0xFF000000UL) >> 24) | \ - (((x) & 0x00FF0000UL) >> 8) | \ - (((x) & 0x0000FF00UL) << 8) | \ - (((x) & 0x000000FFUL) << 24)) - -typedef volatile uint8_t io8_t; -typedef volatile uint16_t io16_t; -typedef volatile uint32_t io32_t; - - -#define RAM_BASE (0x00000000UL) -#define RAM (*((io32_t *) RAM_BASE)) -#define RAM_SIZE (16 * 1024) - - -#define FLASH_BASE (0x10000000UL) -#define FLASH (*((io32_t *) FLASH_BASE)) - -#define FLASH_SIZE (0x39800) -#define FLASH_NUM_SECTORS (4) - - -typedef volatile struct flash_config_regs { - io32_t SR; - io32_t CR; -} flash_config_regs_t; - -#define FLASH_CONFIG_BASE (0x18000000UL) -#define FLASH_CONFIG ((flash_config_regs_t *) FLASH_CONFIG_BASE) - -#define FLASH_SR_STATUS_MASK (3 << 0) -#define FLASH_SR_STATUS_IDLE (0) -#define FLASH_SR_STATUS_BUSY_ERASE (1) -#define FLASH_SR_STATUS_BUSY_WRITE (2) -#define FLASH_SR_STATUS_BUSY_READ (3) -#define FLASH_SR_READ_SUCCESSFUL (1 << 2) -#define FLASH_SR_WRITE_SUCCESSFUL (1 << 3) -#define FLASH_SR_ERASE_SUCCESSFUL (1 << 4) -#define FLASH_SR_WRITE_PROTECT_BIT (5) - -#define FLASH_CR_PAGE_ERASE_BIT (0) -#define FLASH_CR_SECTOR_ERASE_BIT (20) -#define FLASH_CR_SECTOR_ERASE_MASK (7 << FLASH_CR_SECTOR_ERASE_BIT) -#define FLASH_CR_WRITE_PROTECT_BIT (23) - - -typedef volatile struct gpio_regs { - io8_t ODR; - io8_t IDR; - io8_t OER; - io8_t __padding; -} gpio_regs_t; - -#define GPIO_BASE (0x20000000UL) -#define GPIO ((gpio_regs_t *) GPIO_BASE) - - -typedef volatile struct i2c_regs { - io32_t SCR; - io32_t DR; -} i2c_regs_t; - -#define I2C_BASE (0x30000000UL) -#define I2C ((i2c_regs_t *) I2C_BASE) - -#define I2C_SCR_START (1 << 0) -#define I2C_SCR_STOP (1 << 1) -#define I2C_SCR_MACK (1 << 2) -#define I2C_SCR_ACK (1 << 3) -#define I2C_SCR_BUSY (1 << 4) - - -typedef volatile struct usb_regs { - io32_t SCR; - io8_t DR; - io8_t __padding_1[3]; - io8_t ESCAPE; - io8_t __padding_2[3]; -} usb_regs_t; - -#define USB_BASE (0x40000000UL) -#define USB ((usb_regs_t *) USB_BASE) - -#define USB_SCR_RXNE (1 << 0) -#define USB_SCR_TXE (1 << 1) -#define USB_SCR_FLUSH_RX (1 << 2) -#define USB_SCR_FLUSH_TX (1 << 3) -#define USB_SCR_ENABLED (1 << 4) -#define USB_SCR_PWREN (1 << 5) -#define USB_SCR_ESCAPE_PENDING (1 << 6) -#define USB_SCR_ESCAPE_ACK (1 << 7) - - -typedef volatile struct uart_regs { - io32_t SCR; - io8_t DR; - io8_t __padding[3]; -} uart_regs_t; - -#define UART_BASE (0x50000000UL) -#define UART ((uart_regs_t *) UART_BASE) - -#define UART_SCR_RXNE (1 << 0) -#define UART_SCR_TXE (1 << 1) - - -typedef volatile struct dma_regs { - io32_t SCR; - io32_t MADDR; - io32_t ID_LEN; -} dma_regs_t; - -#define DMA_BASE (0x60000000UL) -#define DMA ((dma_regs_t *) DMA_BASE) - -#define DMA_SCR_START (1 << 0) -#define DMA_SCR_STOP (1 << 1) -#define DMA_SCR_DIR (1 << 2) -#define DMA_SCR_BUSY (1 << 3) - - -typedef volatile struct cfg_regs { - io32_t SCR; - io32_t DDIPL_OFFSET; - io32_t SAVE_OFFSET; - io8_t CMD; - io8_t __padding[3]; - io32_t DATA[2]; - io32_t VERSION; - io32_t RECONFIGURE; -} cfg_regs_t; - -#define CFG_BASE (0x70000000UL) -#define CFG ((cfg_regs_t *) CFG_BASE) - -#define CFG_SCR_SDRAM_SWITCH (1 << 0) -#define CFG_SCR_SDRAM_WRITABLE (1 << 1) -#define CFG_SCR_DD_EN (1 << 2) -#define CFG_SCR_SRAM_EN (1 << 3) -#define CFG_SCR_SRAM_BANKED (1 << 4) -#define CFG_SCR_FLASHRAM_EN (1 << 5) -#define CFG_SCR_SKIP_BOOTLOADER (1 << 6) -#define CFG_SCR_CMD_ERROR (1 << 28) -#define CFG_SCR_USB_WAITING (1 << 29) -#define CFG_SCR_CPU_BUSY (1 << 30) -#define CFG_SCR_CPU_READY (1 << 31) - - -#define SDRAM_BASE (0x80000000UL) -#define SDRAM (*((io32_t *) SDRAM_BASE)) -#define SDRAM_SIZE (64 * 1024 * 1024) - - -typedef volatile struct flashram_regs { - io32_t SCR; - io32_t __padding[31]; - io32_t BUFFER[32]; -} flashram_regs_t; - -#define FLASHRAM_BASE (0x90000000UL) -#define FLASHRAM ((flashram_regs_t *) FLASHRAM_BASE) - -#define FLASHRAM_OPERATION_PENDING (1 << 0) -#define FLASHRAM_OPERATION_DONE (1 << 1) -#define FLASHRAM_WRITE_OR_ERASE (1 << 2) -#define FLASHRAM_SECTOR_OR_ALL (1 << 3) -#define FLASHRAM_PAGE_BIT (8) - - -typedef volatile struct joybus_regs { - io32_t SCR; - io32_t DATA[3]; -} joybus_regs_t; - -#define JOYBUS_BASE (0xA0000000UL) -#define JOYBUS ((joybus_regs_t *) JOYBUS_BASE) - -#define JOYBUS_SCR_RX_READY (1 << 0) -#define JOYBUS_SCR_RX_STOP_BIT (1 << 1) -#define JOYBUS_SCR_TX_START (1 << 2) -#define JOYBUS_SCR_TX_BUSY (1 << 3) -#define JOYBUS_SCR_RX_RESET (1 << 6) -#define JOYBUS_SCR_TX_RESET (1 << 7) -#define JOYBUS_SCR_RX_LENGTH_BIT (8) -#define JOYBUS_SCR_RX_LENGTH_MASK (0x7F << JOYBUS_SCR_RX_LENGTH_BIT) -#define JOYBUS_SCR_TX_LENGTH_BIT (16) - - -typedef volatile struct dd_regs { - io32_t SCR; - io16_t DATA; - io8_t CMD; - io8_t __padding_1; - io16_t HEAD_TRACK; - io16_t __padding_2; - io8_t SECTOR_NUM; - io8_t SECTOR_SIZE; - io8_t SECTOR_SIZE_FULL; - io8_t SECTORS_IN_BLOCK; - io16_t DRIVE_ID; - io16_t __padding_3; - io32_t SEEK_TIMER; - io32_t __padding_4[58]; - io32_t SECTOR_BUFFER[64]; -} dd_regs_t; - -#define DD_BASE (0xB0000000UL) -#define DD ((dd_regs_t *) DD_BASE) - -#define DD_SCR_HARD_RESET (1 << 0) -#define DD_SCR_HARD_RESET_CLEAR (1 << 1) -#define DD_SCR_CMD_PENDING (1 << 2) -#define DD_SCR_CMD_READY (1 << 3) -#define DD_SCR_BM_PENDING (1 << 4) -#define DD_SCR_BM_READY (1 << 5) -#define DD_SCR_DISK_INSERTED (1 << 6) -#define DD_SCR_DISK_CHANGED (1 << 7) -#define DD_SCR_BM_START (1 << 8) -#define DD_SCR_BM_START_CLEAR (1 << 9) -#define DD_SCR_BM_STOP (1 << 10) -#define DD_SCR_BM_STOP_CLEAR (1 << 11) -#define DD_SCR_BM_TRANSFER_MODE (1 << 12) -#define DD_SCR_BM_TRANSFER_BLOCKS (1 << 13) -#define DD_SCR_BM_TRANSFER_DATA (1 << 14) -#define DD_SCR_BM_TRANSFER_C2 (1 << 15) -#define DD_SCR_BM_MICRO_ERROR (1 << 16) -#define DD_SCR_BM_ACK (1 << 17) -#define DD_SCR_BM_ACK_CLEAR (1 << 18) -#define DD_SCR_BM_CLEAR (1 << 19) -#define DD_SCR_SEEK_TIMER_RESET (1 << 20) - -#define DD_TRACK_MASK (0x0FFF) -#define DD_HEAD_MASK (0x1000) -#define DD_HEAD_TRACK_MASK (DD_HEAD_MASK | DD_TRACK_MASK) -#define DD_HEAD_TRACK_INDEX_LOCK (1 << 13) - - -void reset_handler(void); - - -#endif diff --git a/sw/riscv/src/uart.c b/sw/riscv/src/uart.c deleted file mode 100644 index 011b8cd..0000000 --- a/sw/riscv/src/uart.c +++ /dev/null @@ -1,75 +0,0 @@ -#include "uart.h" -#include "rtc.h" - - -#ifdef DEBUG -static const char hex_char_map[16] = { - '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' -}; -#endif - -void uart_print (const char *text) { -#ifdef DEBUG - while (*text != '\0') { - while (!(UART->SCR & UART_SCR_TXE)); - UART->DR = *text++; - } -#endif -} - -void uart_print_02hex (uint8_t number) { -#ifdef DEBUG - char buffer[3]; - buffer[0] = hex_char_map[(number >> 4) & 0x0F]; - buffer[1] = hex_char_map[number & 0x0F]; - buffer[2] = '\0'; - uart_print(buffer); -#endif -} - -void uart_print_08hex (uint32_t number) { -#ifdef DEBUG - uart_print_02hex((number >> 24) & 0xFF); - uart_print_02hex((number >> 16) & 0xFF); - uart_print_02hex((number >> 8) & 0xFF); - uart_print_02hex((number >> 0) & 0xFF); -#endif -} - -void uart_init (void) { -#ifdef DEBUG - uart_print("App ready from flash!\n"); -#endif -} - - -void process_uart (void) { -#ifdef DEBUG - rtc_time_t *time; - - if (UART->SCR & USB_SCR_RXNE) { - switch (UART->DR) { - case '/': - uart_print("Bootloader reset...\n"); - reset_handler(); - break; - - case 't': - time = rtc_get_time(); - uart_print("Current time: "); - if (rtc_is_time_running()) { - uart_print("(running) "); - } - if (rtc_is_time_valid()) { - uart_print("(valid) "); - } - for (int i = 0; i < 7; i++) { - uart_print_02hex(((uint8_t *) (time))[i]); - uart_print(" "); - } - uart_print("\n"); - break; - } - } -#endif -} diff --git a/sw/riscv/src/uart.h b/sw/riscv/src/uart.h deleted file mode 100644 index c690dac..0000000 --- a/sw/riscv/src/uart.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef UART_H__ -#define UART_H__ - - -#include "sys.h" - - -void uart_print (const char *text); -void uart_print_02hex (uint8_t number); -void uart_print_08hex (uint32_t number); -void uart_init (void); -void process_uart (void); - - -#endif diff --git a/sw/riscv/src/usb.c b/sw/riscv/src/usb.c deleted file mode 100644 index bb66172..0000000 --- a/sw/riscv/src/usb.c +++ /dev/null @@ -1,323 +0,0 @@ -#include "usb.h" -#include "dma.h" -#include "cfg.h" - - -static bool rx_byte (uint8_t *data) { - if (!(USB->SCR & USB_SCR_RXNE)) { - return false; - } - - *data = USB->DR; - - return true; -} - -static uint8_t rx_word_current_byte = 0; -static uint32_t rx_word_buffer = 0; - -static bool rx_word (uint32_t *data) { - uint8_t tmp; - - while (rx_byte(&tmp)) { - rx_word_buffer = (rx_word_buffer << 8) | tmp; - rx_word_current_byte += 1; - if (rx_word_current_byte == 4) { - rx_word_current_byte = 0; - *data = rx_word_buffer; - rx_word_buffer = 0; - - return true; - } - } - - return false; -} - -static bool tx_byte (uint8_t data) { - if (!(USB->SCR & USB_SCR_TXE)) { - return false; - } - - USB->DR = data; - - return true; -} - -static uint8_t tx_word_current_byte = 0; - -static bool tx_word (uint32_t data) { - while (tx_byte(data >> ((3 - tx_word_current_byte) * 8))) { - tx_word_current_byte += 1; - if (tx_word_current_byte == 4) { - tx_word_current_byte = 0; - - return true; - } - } - - return false; -} - - -#define USB_CMD_TOKEN (0x434D4400) -#define USB_CMP_TOKEN (0x434D5000) -#define USB_ERR_TOKEN (0x45525200) - -enum state { - STATE_IDLE, - STATE_ARGS, - STATE_DATA, - STATE_RESPONSE, - STATE_DEBUG_TX, -}; - -struct process { - enum state state; - uint8_t counter; - uint8_t cmd; - uint32_t args[2]; - bool error; - bool dma_in_progress; - bool queried; - - bool debug_rx_busy; - uint32_t debug_rx_address; - size_t debug_rx_length; - - bool debug_tx_busy; - uint32_t debug_tx_address; - size_t debug_tx_length; -}; - -static struct process p; - - -bool usb_debug_rx_ready (uint32_t *type, size_t *length) { - if (p.state != STATE_DATA || p.cmd != 'D' || p.debug_rx_busy) { - return false; - } - - *type = p.args[0]; - *length = (size_t) p.args[1]; - - return true; -} - -bool usb_debug_rx_busy (void) { - return p.debug_rx_busy; -} - -bool usb_debug_rx_data (uint32_t address, size_t length) { - if (p.debug_rx_busy) { - return false; - } - - p.debug_rx_busy = true; - p.debug_rx_address = address; - p.debug_rx_length = length; - - return true; -} - -bool usb_debug_tx_ready (void) { - return !p.debug_tx_busy; -} - -bool usb_debug_tx_data (uint32_t address, size_t length) { - if (p.debug_tx_busy) { - return false; - } - - p.debug_tx_busy = true; - p.debug_tx_address = address; - p.debug_tx_length = length; - - return true; -} - -void usb_debug_reset (void) { - uint8_t tmp; - - if (p.state == STATE_DATA && p.cmd == 'D') { - for (size_t i = 0; i < p.args[1]; i++) { - rx_byte(&tmp); - } - p.args[1] = 0; - } - if (p.state == STATE_DEBUG_TX) { - p.state = STATE_IDLE; - } - p.debug_rx_busy = false; - p.debug_tx_busy = false; - - USB->SCR = USB_SCR_ENABLED | USB_SCR_FLUSH_TX | USB_SCR_FLUSH_RX; -} - -static uint8_t rx_cmd_current_byte = 0; -static uint32_t rx_cmd_buffer = 0; - -static bool rx_cmd (uint32_t *data) { - uint8_t tmp; - - while (rx_byte(&tmp)) { - rx_cmd_current_byte += 1; - if ((rx_cmd_current_byte != 4) && (tmp != (USB_CMD_TOKEN >> (8 * (4 - rx_cmd_current_byte)) & 0xFF))) { - rx_cmd_current_byte = 0; - rx_cmd_buffer = 0; - - return false; - } - rx_cmd_buffer = (rx_cmd_buffer << 8) | tmp; - if (rx_cmd_current_byte == 4) { - rx_cmd_current_byte = 0; - *data = rx_cmd_buffer; - rx_cmd_buffer = 0; - - return true; - } - } - - return false; -} - -static void handle_escape (void) { - if (USB->SCR & USB_SCR_ESCAPE_PENDING) { - if (USB->ESCAPE == 'R') { - if (p.dma_in_progress) { - dma_stop(); - while (dma_busy()); - } - usb_init(); - } - USB->SCR |= USB_SCR_ESCAPE_ACK; - } -} - - -void usb_init (void) { - USB->SCR = USB_SCR_ENABLED | USB_SCR_FLUSH_TX | USB_SCR_FLUSH_RX; - - p.state = STATE_IDLE; - p.debug_rx_busy = false; - p.debug_tx_busy = false; - - rx_word_current_byte = 0; - rx_word_buffer = 0; - tx_word_current_byte = 0; - rx_cmd_current_byte = 0; - rx_cmd_buffer = 0; -} - - -void process_usb (void) { - handle_escape(); - - switch (p.state) { - case STATE_IDLE: - if (p.debug_tx_busy) { - p.state = STATE_DEBUG_TX; - p.dma_in_progress = false; - } else if (rx_cmd(&p.args[0])) { - if ((p.args[0] & 0xFFFFFF00) == USB_CMD_TOKEN) { - p.cmd = p.args[0] & 0xFF; - p.counter = 0; - p.error = false; - p.dma_in_progress = false; - p.queried = false; - p.state = STATE_ARGS; - } else { - p.cmd = '!'; - p.error = true; - p.state = STATE_RESPONSE; - } - } - break; - - case STATE_ARGS: - if (rx_word(&p.args[p.counter])) { - p.counter += 1; - if (p.counter == 2) { - p.state = STATE_DATA; - } - } - break; - - case STATE_DATA: - switch (p.cmd) { - case 'V': - if (tx_word(cfg_get_version())) { - p.state = STATE_RESPONSE; - } - break; - - case 'C': - cfg_update(p.args); - p.state = STATE_RESPONSE; - break; - - case 'Q': - if (!p.queried) { - cfg_query(p.args); - p.queried = true; - } - if (tx_word(p.args[1])) { - p.state = STATE_RESPONSE; - } - break; - - case 'R': - case 'W': - if (!dma_busy()) { - if (!p.dma_in_progress) { - enum dma_dir dir = p.cmd == 'W' ? DMA_DIR_TO_SDRAM : DMA_DIR_FROM_SDRAM; - dma_start(p.args[0], p.args[1], DMA_ID_USB, dir); - p.dma_in_progress = true; - } else { - p.state = STATE_RESPONSE; - } - } - break; - - case 'D': - if (!dma_busy() && p.debug_rx_busy && p.args[1] > 0) { - if (!p.dma_in_progress) { - dma_start(p.debug_rx_address, p.debug_rx_length, DMA_ID_USB, DMA_DIR_TO_SDRAM); - p.dma_in_progress = true; - } else { - p.args[1] -= p.debug_rx_length > p.args[1] ? p.args[1] : p.debug_rx_length; - p.dma_in_progress = false; - p.debug_rx_busy = false; - } - } - if (p.args[1] == 0) { - p.state = STATE_IDLE; - } - break; - - default: - p.error = true; - p.state = STATE_RESPONSE; - break; - } - break; - - case STATE_RESPONSE: - if (tx_word((p.error ? USB_ERR_TOKEN : USB_CMP_TOKEN) | p.cmd)) { - p.state = STATE_IDLE; - } - break; - - case STATE_DEBUG_TX: - if (!dma_busy()) { - if (!p.dma_in_progress) { - dma_start(p.debug_tx_address, p.debug_tx_length, DMA_ID_USB, DMA_DIR_FROM_SDRAM); - p.dma_in_progress = true; - } else { - p.debug_tx_busy = false; - p.state = STATE_IDLE; - } - } - break; - } -} diff --git a/sw/riscv/src/usb.h b/sw/riscv/src/usb.h deleted file mode 100644 index 28f3298..0000000 --- a/sw/riscv/src/usb.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef USB_H__ -#define USB_H__ - - -#include "sys.h" - - -bool usb_debug_rx_ready (uint32_t *type, size_t *length); -bool usb_debug_rx_busy (void); -bool usb_debug_rx_data (uint32_t address, size_t length); -bool usb_debug_tx_ready (void); -bool usb_debug_tx_data (uint32_t address, size_t length); -void usb_debug_reset (void); -void usb_init (void); -void process_usb (void); - - -#endif diff --git a/sw/update/.gitignore b/sw/update/.gitignore new file mode 100644 index 0000000..aec73fe --- /dev/null +++ b/sw/update/.gitignore @@ -0,0 +1 @@ +*.upd diff --git a/sw/update/update.py b/sw/update/update.py new file mode 100755 index 0000000..5bd7c5c --- /dev/null +++ b/sw/update/update.py @@ -0,0 +1,228 @@ +#!/usr/bin/env python3 + +import argparse +import math +import os +import platform +import sys +from binascii import crc32 +from datetime import datetime +from io import BufferedRandom + + + +class JedecError(Exception): + pass + + +class JedecFile: + __fuse_length: int = 0 + __fuse_offset: int = 0 + __fuse_data: bytes = b'' + __byte_buffer: int = 0 + + def __handle_q_field(self, f: BufferedRandom) -> None: + type = f.read(1) + if (type == b'F'): + value = b'' + while (True): + data = f.read(1) + if (data == b'*'): + value = value.decode('ascii', errors='backslashreplace') + if (not value.isdecimal()): + raise JedecError('Invalid Q field data') + self.__fuse_length = int(value) + break + else: + value += data + else: + self.__ignore_field(f) + + def __handle_l_field(self, f: BufferedRandom) -> None: + if (self.__fuse_length <= 0): + raise JedecError('Found fuse data before declaring fuse count') + + offset = b'' + while (True): + data = f.read(1) + if (data >= b'0' and data <= b'9'): + offset += data + elif (data == b'\r' or data == b'\n'): + offset = offset.decode('ascii', errors='backslashreplace') + if (not offset.isdecimal()): + raise JedecError('Invalid L field offset data') + offset = int(offset) + if (offset != self.__fuse_offset): + raise JedecError('Fuse data is not continuous') + break + else: + raise JedecError('Unexpected byte inside L field offset data') + + data = b'' + while (True): + data = f.read(1) + if (data == b'0' or data == b'1'): + shift = (7 - (self.__fuse_offset % 8)) + self.__byte_buffer |= (1 if data == b'1' else 0) << shift + if (((self.__fuse_offset % 8) == 7) or (self.__fuse_offset == (self.__fuse_length - 1))): + self.__fuse_data += int.to_bytes(self.__byte_buffer, 1, byteorder='little') + self.__byte_buffer = 0 + self.__fuse_offset += 1 + elif (data == b'\r' or data == b'\n'): + pass + elif (data == b'*'): + break + elif (data == b''): + raise JedecError('Unexpected end of file') + else: + raise JedecError('Unexpected byte inside L field fuse data') + + def __ignore_field(self, f: BufferedRandom) -> None: + data = None + while (data != b'*'): + data = f.read(1) + if (data == b''): + raise JedecError('Unexpected end of file') + + def parse(self, path: str) -> bytes: + self.__fuse_length = 0 + self.__fuse_offset = 0 + self.__fuse_data = b'' + self.__byte_buffer = 0 + + field = None + with open(path, 'rb+') as f: + while (True): + field = f.read(1) + if (field == b'\x02'): + f.seek(-1, os.SEEK_CUR) + break + elif (field == b''): + raise JedecError('Unexpected end of file') + + while (True): + field = f.read(1) + if (field == b'Q'): + self.__handle_q_field(f) + elif (field == b'L'): + self.__handle_l_field(f) + elif (field == b'\r' or field == b'\n'): + pass + elif (field == b'\x03'): + break + elif (field == b''): + raise JedecError('Unexpected end of file') + else: + self.__ignore_field(f) + + if (self.__fuse_length <= 0): + raise JedecError('No fuse data found') + + if (self.__fuse_offset != self.__fuse_length): + raise JedecError('Missing fuse data inside JEDEC file') + + if (len(self.__fuse_data) != math.ceil(self.__fuse_length / 8)): + raise JedecError('Missing fuse data inside JEDEC file') + + return self.__fuse_data + + +class SC64UpdateData: + __UPDATE_TOKEN = b'SC64 Update v2.0' + + __CHUNK_ID_UPDATE_INFO = 1 + __CHUNK_ID_MCU_DATA = 2 + __CHUNK_ID_FPGA_DATA = 3 + __CHUNK_ID_BOOTLOADER_DATA = 4 + + __data = b'' + + def __int_to_bytes(self, value: int) -> bytes: + return value.to_bytes(4, byteorder='little') + + def __align(self, value: int) -> int: + if (value % 16 != 0): + value += (16 - (value % 16)) + return value + + def __add_chunk(self, id: int, data: bytes) -> None: + chunk = b'' + chunk_length = (16 + len(data)) + aligned_length = self.__align(chunk_length) + chunk += self.__int_to_bytes(id) + chunk += self.__int_to_bytes(aligned_length - 8) + chunk += self.__int_to_bytes(crc32(data)) + chunk += self.__int_to_bytes(len(data)) + chunk += data + chunk += bytes([0] * (aligned_length - chunk_length)) + self.__data += chunk + + def create_update_data(self) -> None: + self.__data = self.__UPDATE_TOKEN + + def add_update_info(self, data: bytes) -> None: + self.__add_chunk(self.__CHUNK_ID_UPDATE_INFO, data) + + def add_mcu_data(self, data: bytes) -> None: + self.__add_chunk(self.__CHUNK_ID_MCU_DATA, data) + + def add_fpga_data(self, data: bytes) -> None: + self.__add_chunk(self.__CHUNK_ID_FPGA_DATA, data) + + def add_bootloader_data(self, data: bytes) -> None: + self.__add_chunk(self.__CHUNK_ID_BOOTLOADER_DATA, data) + + def get_update_data(self) -> bytes: + return self.__data + + + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description='SC64 update file generator') + parser.add_argument('--git', metavar='git', required=False, help='git text to embed in update info') + parser.add_argument('--mcu', metavar='mcu_path', required=False, help='path to MCU update data') + parser.add_argument('--fpga', metavar='fpga_path', required=False, help='path to FPGA update data') + parser.add_argument('--boot', metavar='bootloader_path', required=False, help='path to N64 bootloader update data') + parser.add_argument('output', metavar='output_path', help='path to final update data') + + if (len(sys.argv) <= 1): + parser.print_help() + parser.exit() + + args = parser.parse_args() + + try: + update = SC64UpdateData() + update.create_update_data() + + hostname = platform.node() + creation_datetime = datetime.utcnow().strftime('%Y-%m-%d %H:%M:%S') + info = [ + f'build system: [{hostname}]', + f'creation datetime: [{creation_datetime}]', + ] + if (args.git): + info.append(args.git) + update_info = ' '.join(info) + print(update_info) + update.add_update_info(update_info.encode()) + + if (args.mcu): + with open(args.mcu, 'rb+') as f: + update.add_mcu_data(f.read()) + + if (args.fpga): + update.add_fpga_data(JedecFile().parse(args.fpga)) + + if (args.boot): + with open(args.boot, 'rb+') as f: + update.add_bootloader_data(f.read()) + + with open(args.output, 'wb+') as f: + f.write(update.get_update_data()) + except JedecError as e: + print(f'Error while parsing FPGA update data: {e}') + exit(-1) + except IOError as e: + print(f'IOError: {e}') + exit(-1)