4 Commits

Author	SHA1	Message	Date
Polprzewodnikowy	0af8989a82	storage 2	2021-12-10 17:15:43 +01:00
Polprzewodnikowy	3d1daf3fc6	some changes	2021-11-25 23:11:36 +01:00
Mateusz Faderewski	29aca8aea6	[SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12)	2021-11-16 22:37:48 +01:00
Mateusz Faderewski	45fbd53001	[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)	2021-09-25 20:00:36 +02:00