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43 lines
899 B
Systemverilog
43 lines
899 B
Systemverilog
module vendor_reconfigure (
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input clk,
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input reset,
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input trigger_reconfiguration
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);
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logic [1:0] ru_clk;
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logic ru_rconfig;
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logic ru_regout;
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logic pending;
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always_ff @(posedge clk) begin
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if (reset) begin
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ru_clk <= 2'd0;
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ru_rconfig <= 1'b0;
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pending <= 1'b0;
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end else begin
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ru_clk <= ru_clk + 1'd1;
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if (trigger_reconfiguration) begin
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pending <= 1'b1;
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end
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if (ru_clk == 2'd1) begin
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ru_rconfig <= pending;
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end
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end
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end
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fiftyfivenm_rublock fiftyfivenm_rublock_inst (
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.clk(ru_clk[1]),
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.shiftnld(1'b0),
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.captnupdt(1'b0),
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.regin(1'b0),
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.rsttimer(1'b0),
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.rconfig(ru_rconfig),
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.regout(ru_regout)
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);
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endmodule
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