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115 lines
6.1 KiB
Markdown
115 lines
6.1 KiB
Markdown
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PicoSoC - A simple example SoC using PicoRV32
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=============================================
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This is a simple PicoRV32 example design that can run code directly from an SPI
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flash chip. It can be used as a turn-key solution for simple control tasks in
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ASIC and FPGA designs.
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An example implementation targeting the Lattice iCE40-HX8K Breakout Board is
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included.
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The flash is mapped to the memory regions starting at 0x00000000 and
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0x01000000, with the SRAM overlayed for the mapping at 0x00000000. The SRAM
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is just a small scratchpad memory (default 256 words, i.e. 1 kB).
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The reset vector is set to 0x00100000, i.e. at 1MB into in the flash memory.
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See the included demo firmware and linker script for how to build a firmware
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image for this system.
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Run `make hx8ksim` or `make icebsim` to run the test bench (and create `testbench.vcd`).
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Run `make hx8kprog` to build the configuration bit-stream and firmware images
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and upload them to a connected iCE40-HX8K Breakout Board.
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Run `make icebprog` to build the configuration bit-stream and firmware images
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and upload them to a connected iCEBreaker Board.
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| File | Description |
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| ----------------------------------- | --------------------------------------------------------------- |
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| [picosoc.v](picosoc.v) | Top-level PicoSoC Verilog module |
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| [spimemio.v](spimemio.v) | Memory controller that interfaces to external SPI flash |
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| [simpleuart.v](simpleuart.v) | Simple UART core connected directly to SoC TX/RX lines |
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| [start.s](start.s) | Assembler source for firmware.hex/firmware.bin |
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| [firmware.c](firmware.c) | C source for firmware.hex/firmware.bin |
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| [sections.lds](sections.lds) | Linker script for firmware.hex/firmware.bin |
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| [hx8kdemo.v](hx8kdemo.v) | FPGA-based example implementation on iCE40-HX8K Breakout Board |
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| [hx8kdemo.pcf](hx8kdemo.pcf) | Pin constraints for implementation on iCE40-HX8K Breakout Board |
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| [hx8kdemo\_tb.v](hx8kdemo_tb.v) | Testbench for implementation on iCE40-HX8K Breakout Board |
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| [icebreaker.v](icebreaker.v) | FPGA-based example implementation on iCEBreaker Board |
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| [icebreaker.pcf](icebreaker.pcf) | Pin constraints for implementation on iCEBreaker Board |
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| [icebreaker\_tb.v](icebreaker_tb.v) | Testbench for implementation on iCEBreaker Board |
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### Memory map:
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| Address Range | Description |
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| ------------------------ | --------------------------------------- |
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| 0x00000000 .. 0x00FFFFFF | Internal SRAM |
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| 0x01000000 .. 0x01FFFFFF | External Serial Flash |
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| 0x02000000 .. 0x02000003 | SPI Flash Controller Config Register |
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| 0x02000004 .. 0x02000007 | UART Clock Divider Register |
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| 0x02000008 .. 0x0200000B | UART Send/Recv Data Register |
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| 0x03000000 .. 0xFFFFFFFF | Memory mapped user peripherals |
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Reading from the addresses in the internal SRAM region beyond the end of the
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physical SRAM will read from the corresponding addresses in serial flash.
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Reading from the UART Send/Recv Data Register will return the last received
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byte, or -1 (all 32 bits set) when the receive buffer is empty.
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The UART Clock Divider Register must be set to the system clock frequency
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divided by the baud rate.
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The example design (hx8kdemo.v) has the 8 LEDs on the iCE40-HX8K Breakout Board
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mapped to the low byte of the 32 bit word at address 0x03000000.
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### SPI Flash Controller Config Register:
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| Bit(s) | Description |
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| -----: | --------------------------------------------------------- |
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| 31 | MEMIO Enable (reset=1, set to 0 to bit bang SPI commands) |
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| 30:23 | Reserved (read 0) |
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| 22 | DDR Enable bit (reset=0) |
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| 21 | QSPI Enable bit (reset=0) |
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| 20 | CRM Enable bit (reset=0) |
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| 19:16 | Read latency (dummy) cycles (reset=8) |
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| 15:12 | Reserved (read 0) |
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| 11:8 | IO Output enable bits in bit bang mode |
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| 7:6 | Reserved (read 0) |
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| 5 | Chip select (CS) line in bit bang mode |
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| 4 | Serial clock line in bit bang mode |
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| 3:0 | IO data bits in bit bang mode |
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The following settings for CRM/DDR/QSPI modes are valid:
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| CRM | QSPI | DDR | Read Command Byte | Mode Byte |
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| :-: | :--: | :-: | :-------------------- | :-------: |
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| 0 | 0 | 0 | 03h Read | N/A |
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| 0 | 0 | 1 | BBh Dual I/O Read | FFh |
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| 1 | 0 | 1 | BBh Dual I/O Read | A5h |
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| 0 | 1 | 0 | EBh Quad I/O Read | FFh |
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| 1 | 1 | 0 | EBh Quad I/O Read | A5h |
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| 0 | 1 | 1 | EDh DDR Quad I/O Read | FFh |
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| 1 | 1 | 1 | EDh DDR Quad I/O Read | A5h |
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The following plot visualizes the relative performance of the different configurations:
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Consult the datasheet for your SPI flash to learn which configurations are supported
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by the chip and what the maximum clock frequencies are for each configuration.
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For Quad I/O mode the QUAD flag in CR1V must be set before enabling Quad I/O in the
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SPI master. Either set it by writing the corresponding bit in CR1NV once, or by writing
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it from your device firmware at every bootup. (See `set_flash_qspi_flag()` in
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`firmware.c` for an example for the latter.)
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Note that some changes to the Lattice iCE40-HX8K Breakout Board are required to support
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the faster configurations: (1) The flash chip must be replaced with one that supports the
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faster read commands and (2) the IO2 and IO3 pins on the flash chip must be connected to
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the FPGA IO pins T9 and T8 (near the center of J3).
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