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43 lines
1.0 KiB
Systemverilog
43 lines
1.0 KiB
Systemverilog
module cpu_gpio (
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if_system.sys sys,
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if_cpu_bus bus,
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input [7:0] gpio_i,
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output [7:0] gpio_o,
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output [7:0] gpio_oe
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);
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logic [1:0][7:0] gpio_i_ff;
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logic [7:0] gpio_o_value;
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logic [7:0] gpio_oe_value;
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always_ff @(posedge sys.clk) begin
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bus.ack <= 1'b0;
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if (bus.request) begin
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bus.ack <= 1'b1;
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end
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end
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always_comb begin
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bus.rdata = 32'd0;
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if (bus.ack) begin
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bus.rdata = {8'd0, gpio_oe_value, gpio_i_ff[1], gpio_o_value};
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end
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end
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always_ff @(posedge sys.clk) begin
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gpio_i_ff <= {gpio_i_ff[0], gpio_i};
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gpio_o <= gpio_o_value;
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gpio_oe <= gpio_oe_value;
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if (sys.reset) begin
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gpio_o_value <= 8'd0;
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gpio_oe_value <= 8'd0;
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end else if (bus.request) begin
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if (bus.wmask[0]) gpio_o_value <= bus.wdata[7:0];
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if (bus.wmask[2]) gpio_oe_value <= bus.wdata[23:16];
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end
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end
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endmodule
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