mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-27 13:31:53 +01:00
5b85b0f661
* [SC64][SW] Added board bring-up via UART header * [SC64][SW] Made I2C in primer stable * [SC64][SW] LCMXO2 primer fixes * [SC64][SW] SC64 primer PC software * [SC64][SW] Added primer.py to release package * [SC64][SW] Fixed FPGA refresh * [SC64][SW] Changed release package contents
101 lines
1.6 KiB
ArmAsm
101 lines
1.6 KiB
ArmAsm
.syntax unified
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.cpu cortex-m0plus
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.fpu softvfp
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.thumb
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.section .text.Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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.global Reset_Handler
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init_text:
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ldr r0, =_stext
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ldr r1, =_etext
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ldr r2, =_sitext
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bl copy_section
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init_rodata:
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ldr r0, =_srodata
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ldr r1, =_erodata
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ldr r2, =_sirodata
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bl copy_section
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init_data:
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ldr r0, =_sdata
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ldr r1, =_edata
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ldr r2, =_sidata
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bl copy_section
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init_bss:
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ldr r2, =_sbss
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ldr r4, =_ebss
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movs r3, #0
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b 2f
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1:
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str r3, [r2]
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adds r2, r2, #4
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2:
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cmp r2, r4
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bcc 1b
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run:
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bl loader
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boot:
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ldr r0, =_app_magic
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ldr r0, [r0]
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ldr r1, =0x34364353
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cmp r0, r1
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bne empty_image
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ldr r0, =_app_header
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push {r0}
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bl hw_set_vector_table
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pop {r0}
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ldr r1, [r0, #0]
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msr MSP, r1
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ldr r1, [r0, #4]
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blx r1
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empty_image:
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bl no_valid_image
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loop:
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b loop
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copy_section:
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movs r3, #0
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b 2f
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1:
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ldr r4, [r2, r3]
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str r4, [r0, r3]
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adds r3, r3, #4
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2:
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adds r4, r0, r3
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cmp r4, r1
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bcc 1b
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bx lr
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.section .text.Default_Handler, "ax", %progbits
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Default_Handler:
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.global Default_Handler
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b Default_Handler
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.section .isr_vector, "a", %progbits
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.type g_pfnVectors, %object
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g_pfnVectors:
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.global g_pfnVectors
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.weak NMI_Handler
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.thumb_set NMI_Handler, Default_Handler
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.weak HardFault_Handler
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.thumb_set HardFault_Handler, Default_Handler
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