mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-25 15:16:53 +01:00
187 lines
9.2 KiB
XML
187 lines
9.2 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<BaliProject version="3.2" title="sc64" device="LCMXO2-7000HC-6TG144C" default_implementation="impl1">
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<Options/>
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<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="release">
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<Options VerilogStandard="System Verilog" def_top="top" top="top"/>
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<Options VerilogStandard="System Verilog"/>
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<Source name="../../rtl/memory/mem_bus.sv" type="Verilog" type_short="Verilog">
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<Options VerilogStandard="System Verilog"/>
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</Source>
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<Source name="../../rtl/n64/n64_scb.sv" type="Verilog" type_short="Verilog">
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<Options VerilogStandard="System Verilog"/>
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</Source>
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<Source name="../../rtl/sd/sd_scb.sv" type="Verilog" type_short="Verilog">
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<Options VerilogStandard="System Verilog"/>
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<Options VerilogStandard="System Verilog"/>
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<Options VerilogStandard="System Verilog"/>
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<Source name="../../rtl/fifo/fifo_junction.sv" type="Verilog" type_short="Verilog">
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<Options VerilogStandard="System Verilog"/>
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<Source name="../../rtl/mcu/mcu_spi.sv" type="Verilog" type_short="Verilog">
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<Options VerilogStandard="System Verilog"/>
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<Source name="../../rtl/mcu/mcu_top.sv" type="Verilog" type_short="Verilog">
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<Options VerilogStandard="System Verilog"/>
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<Options VerilogStandard="System Verilog"/>
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<Source name="../../rtl/memory/memory_bram.sv" type="Verilog" type_short="Verilog">
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<Options VerilogStandard="System Verilog"/>
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<Source name="../../rtl/memory/memory_dma.sv" type="Verilog" type_short="Verilog">
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<Options VerilogStandard="System Verilog"/>
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<Source name="../../rtl/memory/memory_flash.sv" type="Verilog" type_short="Verilog">
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<Options VerilogStandard="System Verilog"/>
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<Options VerilogStandard="System Verilog"/>
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<Options VerilogStandard="System Verilog"/>
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<Options VerilogStandard="System Verilog"/>
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<Source name="../../rtl/vendor/lcmxo2/fifo_8kb.sv" type="Verilog" type_short="Verilog">
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<Options VerilogStandard="System Verilog"/>
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<Source name="../../rtl/vendor/lcmxo2/pll.sv" type="Verilog" type_short="Verilog">
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<Options VerilogStandard="System Verilog"/>
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<Options VerilogStandard="System Verilog"/>
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<Options/>
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</Source>
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<Source name="../../rtl/vendor/lcmxo2/generated/fifo_8kb_lattice_generated.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../rtl/vendor/lcmxo2/generated/pll_lattice_generated.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../rtl/serv/serv_aligner.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../rtl/serv/serv_alu.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../rtl/serv/serv_bufreg.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../rtl/serv/serv_bufreg2.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../rtl/serv/serv_compdec.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../rtl/serv/serv_csr.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../rtl/serv/serv_ctrl.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../rtl/serv/serv_decode.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../rtl/serv/serv_immdec.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../rtl/serv/serv_mem_if.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../rtl/serv/serv_rf_if.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../rtl/serv/serv_rf_ram.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../rtl/serv/serv_rf_ram_if.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../rtl/serv/serv_rf_top.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../rtl/serv/serv_state.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../rtl/serv/serv_top.v" type="Verilog" type_short="Verilog">
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<Options/>
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<Source name="../../rtl/top.sv" type="Verilog" type_short="Verilog">
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<Options VerilogStandard="System Verilog" top_module="top"/>
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</Source>
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<Source name="impl1/sc64.xcf" type="Programming Project File" type_short="Programming">
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<Options/>
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<Source name="sc64.lpf" type="Logic Preference" type_short="LPF">
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<Source name="si.rva" type="Reveal Analyzer Project File" type_short="RVA" excluded="TRUE">
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<Source name="si.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
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<Options/>
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</Implementation>
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<Strategy name="debug" file="debug.sty"/>
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<Strategy name="release" file="release.sty"/>
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</BaliProject>
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