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24 lines
470 B
Systemverilog
24 lines
470 B
Systemverilog
bus.rdata
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module cpu_bootloader (
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if_system.sys sys,
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if_cpu_bus bus
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);
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always_ff @(posedge sys.clk) begin
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bus.ack <= 1'b0;
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if (bus.request) begin
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bus.ack <= 1'b1;
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end
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end
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always_comb begin
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bus.rdata = 32'd0;
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if (bus.ack) begin
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case (bus.address[6:2]){rom_formatted}
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default: bus.rdata = 32'd0;
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endcase
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end
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end
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endmodule
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