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https://github.com/Polprzewodnikowy/SummerCart64.git
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76 lines
2.5 KiB
Systemverilog
76 lines
2.5 KiB
Systemverilog
module n64_cfg (
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if_system sys,
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if_n64_bus bus,
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if_config.n64 cfg
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);
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typedef enum bit [0:0] {
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S_IDLE,
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S_WAIT
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} e_state;
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e_state state;
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always_comb begin
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bus.rdata = 16'd0;
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if (bus.ack) begin
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case (bus.address[4:1])
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0: bus.rdata = {cfg.cpu_bootstrapped, cfg.cpu_busy, 14'd0};
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// ...
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3: bus.rdata = {8'd0, cfg.command};
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4: bus.rdata = cfg.arg[0][31:16];
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5: bus.rdata = cfg.arg[0][15:0];
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6: bus.rdata = cfg.arg[1][31:16];
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7: bus.rdata = cfg.arg[1][15:0];
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8: bus.rdata = cfg.response[31:16];
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9: bus.rdata = cfg.response[15:0];
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10: bus.rdata = cfg.arg[0][31:16];
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11: bus.rdata = cfg.arg[0][15:0];
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endcase
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end
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end
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always_ff @(posedge sys.clk) begin
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bus.ack <= 1'b0;
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cfg.request <= 1'b0;
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cfg.boot_write <= 1'b0;
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if (sys.reset) begin
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state <= S_IDLE;
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end else begin
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case (state)
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S_IDLE: begin
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if (bus.request) begin
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state <= S_WAIT;
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bus.ack <= 1'b1;
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if (bus.write) begin
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case (bus.address[4:1])
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// ...
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3: begin
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cfg.command <= bus.wdata[7:0];
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cfg.request <= 1'b1;
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end
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4: cfg.arg[0][31:16] <= bus.wdata;
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5: cfg.arg[0][15:0] <= bus.wdata;
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6: cfg.arg[1][31:16] <= bus.wdata;
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7: cfg.arg[1][15:0] <= bus.wdata;
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// ...
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10: cfg.arg[0][31:16] <= bus.wdata;
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11: begin
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cfg.arg[0][15:0] <= bus.wdata;
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cfg.boot_write <= 1'b1;
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end
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endcase
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end
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end
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end
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S_WAIT: begin
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state <= S_IDLE;
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end
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endcase
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end
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end
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endmodule
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