mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-30 01:04:13 +01:00
71 lines
1.6 KiB
Systemverilog
71 lines
1.6 KiB
Systemverilog
interface if_config ();
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logic cpu_ready;
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logic cpu_busy;
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logic usb_waiting;
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logic cmd_error;
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logic cmd_request;
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logic [7:0] cmd;
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logic [31:0] data [0:1];
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logic [1:0] data_write;
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logic [31:0] wdata;
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logic sdram_switch;
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logic sdram_writable;
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logic dd_enabled;
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logic sram_enabled;
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logic sram_banked;
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logic flashram_enabled;
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logic flashram_read_mode;
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logic [25:0] dd_offset;
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logic [25:0] save_offset;
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modport pi (
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input sdram_switch,
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input sdram_writable,
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input dd_enabled,
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input sram_enabled,
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input sram_banked,
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input flashram_enabled,
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input flashram_read_mode,
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input dd_offset,
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input save_offset
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);
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modport flashram (
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output flashram_read_mode
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);
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modport n64 (
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input cpu_ready,
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input cpu_busy,
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input usb_waiting,
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input cmd_error,
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output cmd_request,
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output cmd,
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output data,
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input data_write,
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input wdata
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);
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modport cpu (
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output cpu_ready,
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output cpu_busy,
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output usb_waiting,
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output cmd_error,
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input cmd_request,
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input cmd,
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input data,
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output data_write,
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output wdata,
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output sdram_switch,
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output sdram_writable,
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output dd_enabled,
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output sram_enabled,
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output sram_banked,
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output flashram_enabled,
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output dd_offset,
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output save_offset
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);
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endinterface
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