mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-28 05:51:53 +01:00
386 lines
12 KiB
Systemverilog
386 lines
12 KiB
Systemverilog
module n64_pi (
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if_system.sys sys,
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if_config.pi cfg,
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if_n64_bus.n64 bus,
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input n64_pi_alel,
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input n64_pi_aleh,
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input n64_pi_read,
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input n64_pi_write,
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inout [15:0] n64_pi_ad
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);
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// FIFOs
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logic read_fifo_flush;
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logic read_fifo_full;
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logic read_fifo_write;
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logic [15:0] read_fifo_wdata;
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logic read_fifo_empty;
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logic read_fifo_read;
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logic [15:0] read_fifo_rdata;
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n64_pi_fifo read_fifo_inst (
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.sys(sys),
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.flush(read_fifo_flush),
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.full(read_fifo_full),
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.write(read_fifo_write),
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.wdata(read_fifo_wdata),
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.empty(read_fifo_empty),
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.read(read_fifo_read),
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.rdata(read_fifo_rdata)
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);
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logic write_fifo_flush;
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logic write_fifo_full;
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logic write_fifo_write;
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logic [15:0] write_fifo_wdata;
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logic write_fifo_empty;
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logic write_fifo_read;
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logic [15:0] write_fifo_rdata;
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n64_pi_fifo write_fifo_inst (
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.sys(sys),
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.flush(write_fifo_flush),
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.full(write_fifo_full),
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.write(write_fifo_write),
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.wdata(write_fifo_wdata),
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.empty(write_fifo_empty),
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.read(write_fifo_read),
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.rdata(write_fifo_rdata)
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);
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// Control signals and input synchronization
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logic [2:0] n64_pi_alel_ff;
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logic [2:0] n64_pi_aleh_ff;
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logic [2:0] n64_pi_read_ff;
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logic [2:0] n64_pi_write_ff;
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always_ff @(posedge sys.clk) begin
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n64_pi_aleh_ff <= {n64_pi_aleh_ff[1:0], n64_pi_aleh};
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n64_pi_alel_ff <= {n64_pi_alel_ff[1:0], n64_pi_alel};
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n64_pi_read_ff <= {n64_pi_read_ff[1:0], n64_pi_read};
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n64_pi_write_ff <= {n64_pi_write_ff[1:0], n64_pi_write};
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end
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logic pi_reset;
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logic pi_aleh;
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logic pi_alel;
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logic pi_read;
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logic pi_write;
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always_comb begin
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pi_reset = sys.n64_hard_reset;
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pi_aleh = n64_pi_aleh_ff[2];
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pi_alel = n64_pi_alel_ff[2];
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pi_read = n64_pi_read_ff[1];
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pi_write = n64_pi_write_ff[2];
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end
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// PI bus state and event generator
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typedef enum bit [1:0] {
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PI_MODE_IDLE = 2'b10,
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PI_MODE_HIGH = 2'b11,
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PI_MODE_LOW = 2'b01,
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PI_MODE_VALID = 2'b00
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} e_pi_mode;
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e_pi_mode pi_mode;
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e_pi_mode last_pi_mode;
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logic last_read;
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logic last_write;
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always_comb begin
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pi_mode = e_pi_mode'({pi_aleh, pi_alel});
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end
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always_ff @(posedge sys.clk) begin
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last_pi_mode <= pi_mode;
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last_read <= pi_read;
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last_write <= pi_write;
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end
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logic aleh_op;
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logic alel_op;
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logic read_op;
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logic write_op;
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logic end_op;
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always_comb begin
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aleh_op = !pi_reset && last_pi_mode != PI_MODE_HIGH && pi_mode == PI_MODE_HIGH;
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alel_op = !pi_reset && last_pi_mode == PI_MODE_HIGH && pi_mode == PI_MODE_LOW;
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read_op = !pi_reset && pi_mode == PI_MODE_VALID && last_read && !pi_read;
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write_op = !pi_reset && pi_mode == PI_MODE_VALID && last_write && !pi_write;
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end_op = !pi_reset && last_pi_mode == PI_MODE_VALID && pi_mode != PI_MODE_VALID;
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end
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// Input and output data sampling
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logic [15:0] n64_pi_ad_input;
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logic [15:0] n64_pi_ad_output;
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logic [15:0] n64_pi_ad_output_data;
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logic n64_pi_ad_output_enable;
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logic n64_pi_ad_output_enable_data;
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logic n64_pi_address_valid;
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logic pending_operation;
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logic pending_write;
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always_comb begin
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n64_pi_ad = n64_pi_ad_output_enable ? n64_pi_ad_output : 16'hZZZZ;
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n64_pi_ad_output_enable_data = !pi_reset && pi_mode == PI_MODE_VALID && n64_pi_address_valid && !n64_pi_read_ff[2];
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end
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always_ff @(posedge sys.clk) begin
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n64_pi_ad_input <= n64_pi_ad;
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n64_pi_ad_output <= n64_pi_ad_output_data;
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n64_pi_ad_output_enable <= n64_pi_ad_output_enable_data;
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end
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logic wait_for_read_fifo;
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logic wait_for_write_fifo;
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always_comb begin
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read_fifo_write = bus.ack && !bus.write;
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read_fifo_wdata = bus.rdata;
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write_fifo_wdata = n64_pi_ad_input;
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end
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always_ff @(posedge sys.clk) begin
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read_fifo_read <= 1'b0;
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write_fifo_write <= 1'b0;
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if (sys.reset || sys.n64_hard_reset) begin
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wait_for_read_fifo <= 1'b0;
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wait_for_write_fifo <= 1'b0;
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end else if (n64_pi_address_valid) begin
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if (read_op || wait_for_read_fifo) begin
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if (read_fifo_empty) begin
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wait_for_read_fifo <= 1'b1;
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end else begin
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n64_pi_ad_output_data <= read_fifo_rdata;
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read_fifo_read <= 1'b1;
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wait_for_read_fifo <= 1'b0;
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end
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end
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if (write_op || wait_for_write_fifo) begin
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if (write_fifo_full) begin
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wait_for_write_fifo <= 1'b1;
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end else begin
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write_fifo_write <= 1'b1;
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wait_for_write_fifo <= 1'b0;
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end
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end
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end
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end
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always_comb begin
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bus.n64_active = !pi_reset && pi_mode != PI_MODE_IDLE;
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bus.read_op = read_op;
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bus.write_op = write_op;
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end
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always_ff @(posedge sys.clk) begin
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if (aleh_op) begin
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bus.real_address[31:16] <= n64_pi_ad_input;
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end
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if (alel_op) begin
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bus.real_address[15:0] <= {n64_pi_ad_input[15:1], 1'b0};
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end
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if (read_op || write_op) begin
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bus.real_address <= bus.real_address + 2'd2;
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end
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end
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// Address decoding
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logic load_next;
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sc64::e_n64_id next_id;
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logic [31:0] next_offset;
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logic sram_selected;
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logic isv_selected;
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always_ff @(posedge sys.clk) begin
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load_next <= 1'b0;
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if (aleh_op) begin
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n64_pi_address_valid <= 1'b0;
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next_id <= sc64::__ID_N64_END;
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next_offset <= 32'd0;
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sram_selected <= 1'b0;
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isv_selected <= 1'b0;
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if (cfg.dd_enabled) begin
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if (n64_pi_ad_input == 16'h0500) begin
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n64_pi_address_valid <= 1'b1;
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next_id <= sc64::ID_N64_DD;
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next_offset <= cfg.ddipl_offset - 32'h0500_0000;
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end
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if (n64_pi_ad_input >= 16'h0600 && n64_pi_ad_input < 16'h0640) begin
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n64_pi_address_valid <= 1'b1;
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next_id <= sc64::ID_N64_SDRAM;
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next_offset <= cfg.ddipl_offset - 32'h0600_0000;
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end
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end
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if (cfg.flashram_enabled) begin
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if (n64_pi_ad_input >= 16'h0800 && n64_pi_ad_input < 16'h0802) begin
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n64_pi_address_valid <= 1'b1;
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next_id <= sc64::ID_N64_FLASHRAM;
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if (cfg.flashram_read_mode) begin
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next_offset <= cfg.save_offset - 32'h0800_0000;
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end
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end
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end else if (cfg.sram_enabled) begin
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if (cfg.sram_banked) begin
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if (n64_pi_ad_input >= 16'h0800 && n64_pi_ad_input < 16'h0810) begin
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if (n64_pi_ad_input[3:2] != 2'b11 && n64_pi_ad_input[1:0] == 2'b00) begin
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n64_pi_address_valid <= 1'b1;
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next_id <= sc64::ID_N64_SDRAM;
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next_offset <= cfg.save_offset - {n64_pi_ad_input[3:2], 18'd0} + {n64_pi_ad_input[3:2], 15'd0} - 32'h0800_0000;
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sram_selected <= 1'b1;
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end
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end
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end else begin
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if (n64_pi_ad_input == 16'h0800) begin
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n64_pi_address_valid <= 1'b1;
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next_id <= sc64::ID_N64_SDRAM;
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next_offset <= cfg.save_offset - 32'h0800_0000;
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sram_selected <= 1'b1;
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end
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end
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end
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if (n64_pi_ad_input >= 16'h1000 && n64_pi_ad_input < 16'h1400) begin
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n64_pi_address_valid <= 1'b1;
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next_id <= cfg.sdram_switch ? sc64::ID_N64_SDRAM : sc64::ID_N64_BOOTLOADER;
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next_offset <= (-32'h1000_0000);
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if (cfg.isv_enabled) begin
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if (n64_pi_ad_input == 16'h13FF) begin
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next_id <= sc64::ID_N64_SDRAM;
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next_offset <= cfg.isv_offset - 32'h13FF_0000;
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isv_selected <= 1'b1;
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end
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end
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end
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if (n64_pi_ad_input == 16'h1FFF) begin
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n64_pi_address_valid <= 1'b1;
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next_id <= sc64::ID_N64_CFG;
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end
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end
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if (alel_op) begin
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if (next_id == sc64::ID_N64_DD) begin
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if (|n64_pi_ad_input[15:11]) begin
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n64_pi_address_valid <= 1'b0;
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end
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end
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if (sram_selected) begin
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if (n64_pi_ad_input[15]) begin
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n64_pi_address_valid <= 1'b0;
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end
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end
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if (isv_selected) begin
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if (n64_pi_ad_input < 16'h0020) begin
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next_offset <= (-32'h13FF_0000) + 32'h0000_C000;
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next_id <= sc64::ID_N64_CFG;
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end
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end
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load_next <= 1'b1;
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end
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end
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// Bus controller
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logic can_read;
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logic first_write_op;
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logic load_starting_address;
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sc64::e_n64_id starting_id;
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logic [31:0] starting_address;
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always_ff @(posedge sys.clk) begin
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read_fifo_flush <= 1'b0;
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write_fifo_read <= 1'b0;
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if (sys.reset || sys.n64_hard_reset) begin
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bus.request <= 1'b0;
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read_fifo_flush <= 1'b1;
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write_fifo_flush <= 1'b1;
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end else begin
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write_fifo_flush <= starting_id == sc64::ID_N64_SDRAM && !cfg.sdram_writable && !sram_selected && !isv_selected;
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if (aleh_op) begin
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starting_address[31:16] <= n64_pi_ad_input;
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end
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if (load_next) begin
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read_fifo_flush <= 1'b1;
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can_read <= 1'b1;
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first_write_op <= 1'b1;
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load_starting_address <= 1'b1;
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starting_id <= next_id;
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starting_address <= {starting_address[31:16], n64_pi_ad_input[15:1], 1'b0};
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end
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if (write_op) begin
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can_read <= 1'b0;
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if (first_write_op) begin
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first_write_op <= 1'b0;
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load_starting_address <= 1'b1;
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end
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end
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if (!bus.request) begin
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if (!write_fifo_empty) begin
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bus.request <= 1'b1;
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bus.write <= 1'b1;
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if (load_starting_address) begin
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bus.id <= starting_id;
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bus.address <= starting_address + next_offset;
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if (starting_id == sc64::ID_N64_FLASHRAM) begin
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bus.address <= starting_address;
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end
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load_starting_address <= 1'b0;
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end
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bus.wdata <= write_fifo_rdata;
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write_fifo_read <= 1'b1;
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end else if (!read_fifo_full && can_read) begin
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bus.request <= 1'b1;
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bus.write <= 1'b0;
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if (load_starting_address) begin
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bus.id <= starting_id;
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bus.address <= starting_address + next_offset;
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if (starting_id == sc64::ID_N64_FLASHRAM && cfg.flashram_read_mode) begin
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bus.id <= sc64::ID_N64_SDRAM;
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end
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load_starting_address <= 1'b0;
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end
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end
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end else if (bus.ack) begin
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bus.request <= 1'b0;
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bus.address <= bus.address + 2'd2;
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end
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if (end_op) begin
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can_read <= 1'b0;
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end
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end
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end
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endmodule
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