mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-25 23:24:15 +01:00
72 lines
1.9 KiB
Verilog
72 lines
1.9 KiB
Verilog
module cart_config (
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input i_clk,
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input i_reset,
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input i_n64_reset,
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input i_n64_nmi,
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input i_select,
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input i_read_rq,
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input i_write_rq,
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output reg o_ack,
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input [31:0] i_address,
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input [31:0] i_data,
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output [31:0] o_data,
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input i_n64_disabled,
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output o_flash_enable,
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output o_sdram_enable
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);
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reg [1:0] r_cart_config;
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reg [7:0] r_cic_type;
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wire [31:0] w_regs [1:0];
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assign w_regs[0] = {30'd0, r_cart_config};
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assign w_regs[1] = {24'd0, r_cic_type};
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assign o_data = w_regs[i_address[2]];
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assign o_flash_enable = r_cart_config[0];
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assign o_sdram_enable = r_cart_config[1];
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reg r_last_n64_reset;
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reg r_last_n64_nmi;
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wire w_n64_reset_op = !i_n64_disabled && !r_last_n64_reset && i_n64_reset;
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wire w_n64_nmi_op = !i_n64_disabled && !r_last_n64_nmi && i_n64_nmi;
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always @(posedge i_clk or posedge i_reset) begin
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if (i_reset) begin
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r_last_n64_reset <= 1'b0;
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r_last_n64_nmi <= 1'b0;
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end else begin
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r_last_n64_reset <= i_n64_reset;
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r_last_n64_nmi <= i_n64_nmi;
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end
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end
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always @(posedge i_clk or posedge i_reset or posedge w_n64_reset_op or posedge w_n64_nmi_op) begin
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if (i_reset || w_n64_reset_op || w_n64_nmi_op) begin
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r_cart_config <= 2'b01;
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end else begin
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if (i_select && i_write_rq && !i_address[2]) r_cart_config <= i_data[1:0];
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end
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end
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always @(posedge i_clk or posedge i_reset) begin
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if (i_reset) begin
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r_cic_type <= 8'd0;
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end else begin
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if (i_select && i_write_rq && i_address[2]) r_cic_type <= i_data[7:0];
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end
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end
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always @(posedge i_clk) begin
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o_ack <= 1'b0;
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if (i_select && (i_read_rq || i_write_rq)) o_ack <= 1'b1;
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end
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endmodule
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