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https://github.com/Polprzewodnikowy/SummerCart64.git
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80 lines
2.1 KiB
Verilog
80 lines
2.1 KiB
Verilog
module flash (
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input i_clk,
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input i_reset,
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output o_flash_clk,
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output o_flash_cs,
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input [3:0] i_flash_dq,
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output [3:0] o_flash_dq,
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output [1:0] o_flash_dq_mode,
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input i_select,
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input i_cfg_select,
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input i_read_rq,
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input i_write_rq,
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output o_ack,
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input [31:0] i_address,
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input [31:0] i_data,
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output [31:0] o_data
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);
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reg r_wb_cyc;
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wire w_wb_cyc;
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wire w_stb;
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wire w_wb_stb;
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wire w_cfg_stb;
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wire w_wb_ack;
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wire w_wb_stall;
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assign w_wb_cyc = w_wb_stb || w_cfg_stb || r_wb_cyc;
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assign w_stb = !w_wb_stall && (i_read_rq || i_write_rq);
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assign w_wb_stb = i_select && w_stb;
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assign w_cfg_stb = i_cfg_select && w_stb;
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assign o_ack = w_wb_ack;
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always @(posedge i_clk or posedge i_reset) begin
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if (i_reset) begin
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r_wb_cyc <= 1'b0;
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end else begin
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if (w_wb_stb || w_cfg_stb) begin
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r_wb_cyc <= 1'b1;
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end else if (w_wb_ack) begin
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r_wb_cyc <= 1'b0;
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end
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end
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end
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qflexpress qflexpress_inst(
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.i_clk(i_clk),
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.i_reset(i_reset),
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.i_wb_cyc(w_wb_cyc),
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.i_wb_stb(w_wb_stb), // FIXME: Currently strobe can be missed when w_wb_stall is high
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.i_cfg_stb(w_cfg_stb),
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.i_wb_we(i_write_rq),
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.i_wb_addr(i_address[31:1]),
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.i_wb_data(i_data),
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.o_wb_ack(w_wb_ack),
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.o_wb_stall(w_wb_stall),
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.o_wb_data(o_data),
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.o_qspi_sck(o_flash_clk),
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.o_qspi_cs_n(o_flash_cs),
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.o_qspi_mod(o_flash_dq_mode),
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.o_qspi_dat(o_flash_dq),
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.i_qspi_dat(i_flash_dq)
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);
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defparam
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qflexpress_inst.LGFLASHSZ = 24,
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qflexpress_inst.OPT_PIPE = 0,
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qflexpress_inst.OPT_CFG = 1,
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qflexpress_inst.OPT_STARTUP = 1,
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qflexpress_inst.OPT_CLKDIV = 1,
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qflexpress_inst.OPT_ENDIANSWAP = 0,
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qflexpress_inst.RDDELAY = 0,
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qflexpress_inst.NDUMMY = 6,
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qflexpress_inst.OPT_STARTUP_FILE = "";
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endmodule
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