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82 lines
1.9 KiB
Verilog
Vendored
82 lines
1.9 KiB
Verilog
Vendored
`default_nettype none
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module serv_alu
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#(
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parameter W = 1,
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parameter B = W-1
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)
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(
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input wire clk,
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//State
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input wire i_en,
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input wire i_cnt0,
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output wire o_cmp,
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//Control
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input wire i_sub,
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input wire [1:0] i_bool_op,
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input wire i_cmp_eq,
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input wire i_cmp_sig,
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input wire [2:0] i_rd_sel,
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//Data
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input wire [B:0] i_rs1,
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input wire [B:0] i_op_b,
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input wire [B:0] i_buf,
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output wire [B:0] o_rd);
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wire [B:0] result_add;
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wire [B:0] result_slt;
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reg cmp_r;
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wire add_cy;
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reg [B:0] add_cy_r;
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//Sign-extended operands
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wire rs1_sx = i_rs1[B] & i_cmp_sig;
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wire op_b_sx = i_op_b[B] & i_cmp_sig;
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wire [B:0] add_b = i_op_b^{W{i_sub}};
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assign {add_cy,result_add} = i_rs1+add_b+add_cy_r;
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wire result_lt = rs1_sx + ~op_b_sx + add_cy;
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wire result_eq = !(|result_add) & (cmp_r | i_cnt0);
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assign o_cmp = i_cmp_eq ? result_eq : result_lt;
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/*
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The result_bool expression implements the following operations between
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i_rs1 and i_op_b depending on the value of i_bool_op
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00 xor
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01 0
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10 or
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11 and
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i_bool_op will be 01 during shift operations, so by outputting zero under
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this condition we can safely or result_bool with i_buf
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*/
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wire [B:0] result_bool = ((i_rs1 ^ i_op_b) & ~{W{i_bool_op[0]}}) | ({W{i_bool_op[1]}} & i_op_b & i_rs1);
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assign result_slt[0] = cmp_r & i_cnt0;
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generate
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if (W>1) begin : gen_w_gt_1
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assign result_slt[B:1] = {B{1'b0}};
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end
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endgenerate
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assign o_rd = i_buf |
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({W{i_rd_sel[0]}} & result_add) |
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({W{i_rd_sel[1]}} & result_slt) |
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({W{i_rd_sel[2]}} & result_bool);
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always @(posedge clk) begin
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add_cy_r <= {W{1'b0}};
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add_cy_r[0] <= i_en ? add_cy : i_sub;
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if (i_en)
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cmp_r <= o_cmp;
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end
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endmodule
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