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40 lines
974 B
Systemverilog
40 lines
974 B
Systemverilog
module dma_controller_mock (
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input clk,
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input reset,
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dma_scb.controller dma_scb,
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input start,
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input stop,
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input direction,
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input byte_swap,
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input [26:0] starting_address,
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input [26:0] transfer_length
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);
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always_ff @(posedge clk) begin
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dma_scb.start <= 1'b0;
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dma_scb.stop <= 1'b0;
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if (reset) begin
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dma_scb.direction <= 1'b0;
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dma_scb.byte_swap <= 1'b0;
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dma_scb.starting_address <= 27'd0;
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dma_scb.transfer_length <= 27'd0;
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end else begin
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if (start) begin
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dma_scb.start <= 1'b1;
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dma_scb.direction <= direction;
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dma_scb.byte_swap <= byte_swap;
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dma_scb.starting_address <= starting_address;
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dma_scb.transfer_length <= transfer_length;
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end
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if (stop) begin
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dma_scb.stop <= 1'b1;
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end
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end
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end
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endmodule
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