mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-22 14:09:16 +01:00
5b85b0f661
* [SC64][SW] Added board bring-up via UART header * [SC64][SW] Made I2C in primer stable * [SC64][SW] LCMXO2 primer fixes * [SC64][SW] SC64 primer PC software * [SC64][SW] Added primer.py to release package * [SC64][SW] Fixed FPGA refresh * [SC64][SW] Changed release package contents
67 lines
1.3 KiB
Plaintext
67 lines
1.3 KiB
Plaintext
MEMORY {
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code (rx) : org = 0x08000000, len = 4k
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ram (rwx) : org = 0x20000000, len = 8k
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}
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ENTRY(Reset_Handler)
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SECTIONS {
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.isr_vector : {
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. = ALIGN(4);
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KEEP(*(.isr_vector))
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. = ALIGN(4);
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} > code
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.startup : {
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. = ALIGN(4);
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*(.text.Reset_Handler)
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. = ALIGN(4);
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} > code
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.text : {
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_sitext = LOADADDR(.text);
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. = ALIGN(4);
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_stext = .;
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*(.text)
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*(.text*)
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*(.glue_7)
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*(.glue_7t)
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. = ALIGN(4);
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_etext = .;
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} > ram AT > code
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.bss : {
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. = ALIGN(4);
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_sbss = .;
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*(.bss)
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = .;
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} > ram
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.data : {
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_sidata = LOADADDR(.data);
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. = ALIGN(4);
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_sdata = .;
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*(.data)
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*(.data*)
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. = ALIGN(4);
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_edata = .;
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} > ram AT > code
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.rodata : {
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_sirodata = LOADADDR(.rodata);
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. = ALIGN(4);
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_srodata = .;
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*(.rodata)
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*(.rodata*)
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. = ALIGN(4);
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_erodata = .;
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} > ram AT > code
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_app_header = ORIGIN(code) + LENGTH(code);
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_app_magic = _app_header + 16;
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_estack = ORIGIN(ram) + LENGTH(ram);
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}
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