mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-26 15:44:14 +01:00
349 lines
12 KiB
Verilog
349 lines
12 KiB
Verilog
module sd_dat (
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input i_clk,
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input i_reset,
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inout reg [3:0] io_sd_dat,
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input i_sd_clk_strobe_rising,
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input i_sd_clk_strobe_falling,
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input i_dat_width,
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input i_dat_direction,
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input [6:0] i_dat_block_size,
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input [7:0] i_dat_num_blocks,
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input i_dat_start,
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input i_dat_stop,
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output o_dat_busy,
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output o_dat_write_busy,
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output reg o_dat_crc_error,
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output reg o_dat_write_error,
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output reg o_dat_write_ok,
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input i_rx_fifo_overrun,
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output reg o_rx_fifo_push,
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output reg [31:0] o_rx_fifo_data,
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input [8:0] i_tx_fifo_items,
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input i_tx_fifo_underrun,
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output reg o_tx_fifo_pop,
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input [31:0] i_tx_fifo_data
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);
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// Module state
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localparam STATE_IDLE = 0;
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localparam STATE_READ_WAIT = 1;
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localparam STATE_RECEIVING = 2;
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localparam STATE_WRITE_WAIT = 3;
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localparam STATE_SENDING = 4;
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localparam STATE_STATUS = 5;
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localparam STATE_BUSY = 6;
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reg [6:0] r_state;
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assign o_dat_busy = !r_state[STATE_IDLE];
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assign o_dat_write_busy = !io_sd_dat[0];
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// Bit counter logic
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reg [12:0] r_bit_counter;
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reg r_bit_counter_done;
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wire w_read_start = r_state[STATE_READ_WAIT] && !io_sd_dat[0] && i_sd_clk_strobe_rising;
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wire w_write_start = r_state[STATE_WRITE_WAIT] && (i_tx_fifo_items >= ({1'b0, i_dat_block_size} + 1)) && i_sd_clk_strobe_falling;
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wire w_status_start = r_state[STATE_SENDING] && r_bit_counter_done;
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wire w_status_done = r_state[STATE_STATUS] && r_bit_counter_done;
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wire w_block_read_done = r_state[STATE_RECEIVING] && r_bit_counter_done;
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wire w_block_write_done = r_state[STATE_SENDING] && r_bit_counter_done;
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wire w_block_write_busy_done = r_state[STATE_BUSY] && io_sd_dat[0];
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wire w_block_done = w_block_read_done || w_block_write_busy_done;
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wire [12:0] w_block_bit_length = i_dat_width ? ({2'b00, {1'b0, i_dat_block_size} + 1'd1, 3'b000}) : ({{1'b0, i_dat_block_size} + 1'd1, 5'b00000});
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always @(posedge i_clk) begin
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if (w_read_start) begin
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r_bit_counter <= w_block_bit_length + 13'd16;
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r_bit_counter_done <= 1'b0;
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end else if (w_write_start) begin
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r_bit_counter <= w_block_bit_length + 13'd17;
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r_bit_counter_done <= 1'b0;
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end else if (w_status_start) begin
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r_bit_counter <= 13'd6;
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r_bit_counter_done <= 1'b0;
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end else if (i_sd_clk_strobe_rising) begin
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if (r_bit_counter > 13'd0) begin
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r_bit_counter <= r_bit_counter - 1'd1;
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end else begin
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r_bit_counter_done <= 1'd1;
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end
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end
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end
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// Block counter logic
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reg [7:0] r_block_counter;
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wire w_block_start = i_dat_start && r_state[STATE_IDLE];
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wire w_block_stop = r_block_counter == 8'd0;
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always @(posedge i_clk) begin
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if (w_block_start) begin
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r_block_counter <= i_dat_num_blocks;
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end else if (w_block_done) begin
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if (r_block_counter > 8'd0) begin
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r_block_counter <= r_block_counter - 1'd1;
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end
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end
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end
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// CRC16 generator
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reg [15:0] r_crc_16_received [0:3];
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wire w_crc_shift_reset = !(r_state[STATE_RECEIVING] || r_state[STATE_SENDING]);
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wire w_crc_shift_enabled = r_bit_counter > 13'd16;
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wire w_crc_shift = w_crc_shift_enabled && i_sd_clk_strobe_rising;
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wire [15:0] w_crc_16_calculated [0:3];
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wire w_crc_read_error = (r_bit_counter == 13'd0) && (i_dat_width ? (
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(w_crc_16_calculated[0] != r_crc_16_received[0]) &&
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(w_crc_16_calculated[1] != r_crc_16_received[1]) &&
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(w_crc_16_calculated[2] != r_crc_16_received[2]) &&
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(w_crc_16_calculated[3] != r_crc_16_received[3])
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) : (
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w_crc_16_calculated[0] != r_crc_16_received[0]
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));
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genvar dat_index;
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generate
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for (dat_index = 0; dat_index < 4; dat_index = dat_index + 1) begin : crc_16_loop
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sd_crc_16 sd_crc_16_inst (
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.i_clk(i_clk),
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.i_crc_reset(w_crc_shift_reset),
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.i_crc_shift(w_crc_shift),
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.i_crc_input(io_sd_dat[dat_index]),
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.o_crc_output(w_crc_16_calculated[dat_index])
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);
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end
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endgenerate
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// Control signals
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localparam [4:0] STATUS_NO_ERROR = 5'b00101;
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localparam [4:0] STATUS_CRC_ERROR = 5'b01011;
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localparam [4:0] STATUS_WRITE_ERROR = 5'b01101;
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reg [4:0] r_status;
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wire w_no_write_error = r_status == STATUS_NO_ERROR;
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wire w_crc_write_error = r_status == STATUS_CRC_ERROR;
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wire w_data_write_error = r_status == STATUS_WRITE_ERROR;
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always @(posedge i_clk) begin
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if (i_reset || w_block_start) begin
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o_dat_crc_error <= 1'b0;
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o_dat_write_error <= 1'b0;
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end else begin
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if (w_block_read_done) begin
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o_dat_crc_error <= w_crc_read_error;
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end
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if (w_status_done) begin
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o_dat_crc_error <= w_crc_write_error;
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o_dat_write_error <= w_data_write_error;
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o_dat_write_ok <= w_no_write_error;
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end
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end
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end
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// State machine
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always @(posedge i_clk) begin
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if (i_reset) begin
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r_state <= (1'b1 << STATE_IDLE);
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end else begin
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r_state <= 7'b0000000;
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if (i_dat_stop) begin
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r_state[STATE_IDLE] <= 1'b1;
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end else begin
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unique case (1'b1)
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r_state[STATE_IDLE]: begin
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if (i_dat_start) begin
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if (i_dat_direction) begin
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r_state[STATE_WRITE_WAIT] <= 1'b1;
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end else begin
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r_state[STATE_READ_WAIT] <= 1'b1;
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end
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end else begin
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r_state[STATE_IDLE] <= 1'b1;
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end
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end
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r_state[STATE_READ_WAIT]: begin
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if (w_read_start) begin
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r_state[STATE_RECEIVING] <= 1'b1;
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end else begin
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r_state[STATE_READ_WAIT] <= 1'b1;
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end
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end
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r_state[STATE_RECEIVING]: begin
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if (w_crc_read_error || i_rx_fifo_overrun) begin
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r_state[STATE_IDLE] <= 1'b1;
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end else if (w_block_read_done) begin
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if (w_block_stop) begin
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r_state[STATE_IDLE] <= 1'b1;
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end else begin
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r_state[STATE_READ_WAIT] <= 1'b1;
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end
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end else begin
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r_state[STATE_RECEIVING] <= 1'b1;
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end
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end
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r_state[STATE_WRITE_WAIT]: begin
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if (w_write_start) begin
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r_state[STATE_SENDING] <= 1'b1;
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end else begin
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r_state[STATE_WRITE_WAIT] <= 1'b1;
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end
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end
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r_state[STATE_SENDING]: begin
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if (i_tx_fifo_underrun) begin
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r_state[STATE_IDLE] <= 1'b1;
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end else if (w_block_write_done) begin
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r_state[STATE_STATUS] <= 1'b1;
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end else begin
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r_state[STATE_SENDING] <= 1'b1;
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end
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end
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r_state[STATE_STATUS]: begin
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if (w_status_done) begin
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r_state[STATE_BUSY] <= 1'b1;
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end else begin
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r_state[STATE_STATUS] <= 1'b1;
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end
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end
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r_state[STATE_BUSY]: begin
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if (w_block_write_busy_done) begin
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if (w_block_stop || !w_no_write_error) begin
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r_state[STATE_IDLE] <= 1'b1;
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end else begin
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r_state[STATE_WRITE_WAIT] <= 1'b1;
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end
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end else begin
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r_state[STATE_BUSY] <= 1'b1;
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end
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end
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endcase
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end
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end
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end
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// RX shifting operation
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wire w_rx_latch = r_state[STATE_RECEIVING] && i_sd_clk_strobe_rising;
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wire w_rx_data_phase = r_bit_counter >= 13'd17;
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wire w_rx_crc_phase = r_bit_counter >= 13'd1;
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wire w_rx_fifo_push = i_dat_width ? (r_bit_counter[2:0] == 3'd1) : (r_bit_counter[4:0] == 5'd17);
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wire [31:0] w_rx_fifo_shift = i_dat_width ? {o_rx_fifo_data[27:0], io_sd_dat} : {o_rx_fifo_data[30:0], io_sd_dat[0]};
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always @(posedge i_clk) begin
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o_rx_fifo_push <= 1'b0;
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if (w_rx_latch) begin
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if (w_rx_data_phase) begin
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o_rx_fifo_data <= w_rx_fifo_shift;
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o_rx_fifo_push <= w_rx_fifo_push;
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end else if (w_rx_crc_phase) begin
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for (integer i = 0; i < 4; i = i + 1) begin
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r_crc_16_received[i] <= {r_crc_16_received[i][14:0], io_sd_dat[i]};
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end
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end
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end
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end
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// TX shifting operation
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wire w_tx_latch = r_state[STATE_SENDING] && i_sd_clk_strobe_falling;
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wire w_tx_data_phase = r_bit_counter >= 13'd17;
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wire w_tx_crc_phase = r_bit_counter >= 13'd1;
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wire w_tx_fifo_pop = i_dat_width ? (r_bit_counter[2:0] == 3'd0) : (r_bit_counter[4:0] == 5'd17);
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wire w_tx_shift_load = r_bit_counter[2:0] == 3'd0;
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reg [7:0] r_tx_shift [0:3];
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always @(*) begin
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io_sd_dat = 4'bZZZZ;
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if (r_state[STATE_SENDING]) begin
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io_sd_dat = i_dat_width ? (
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{r_tx_shift[3][7], r_tx_shift[2][7], r_tx_shift[1][7], r_tx_shift[0][7]}
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) : (
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{3'bZZZ, r_tx_shift[0][7]}
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);
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end
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end
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always @(posedge i_clk) begin
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o_tx_fifo_pop <= 1'b0;
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if (w_write_start) begin
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{r_tx_shift[3][7], r_tx_shift[2][7], r_tx_shift[1][7], r_tx_shift[0][7]} <= 4'b0000;
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end else if (w_tx_latch) begin
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if (w_tx_data_phase) begin
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o_tx_fifo_pop <= w_tx_fifo_pop;
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for (integer i = 0; i < 4; i = i + 1) begin
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r_tx_shift[i] <= {r_tx_shift[i][6:0], 1'b0};
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end
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if (w_tx_shift_load) begin
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if (i_dat_width) begin
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for (integer i = 0; i < 4; i = i + 1) begin
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for (integer j = 0; j < 8; j = j + 1) begin
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r_tx_shift[i][j] <= i_tx_fifo_data[((j * 4) + i)];
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end
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end
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end else begin
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case (r_bit_counter[4:3])
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2'b10: r_tx_shift[0] <= i_tx_fifo_data[31:24];
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2'b01: r_tx_shift[0] <= i_tx_fifo_data[23:16];
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2'b00: r_tx_shift[0] <= i_tx_fifo_data[15:8];
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2'b11: r_tx_shift[0] <= i_tx_fifo_data[7:0];
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endcase
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end
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end
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end else if (w_tx_crc_phase) begin
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for (integer i = 0; i < 4; i = i + 1) begin
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r_tx_shift[i] <= {r_tx_shift[i][6:0], 1'b0};
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if (w_tx_shift_load) begin
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r_tx_shift[i] <= !r_bit_counter[3] ? w_crc_16_calculated[i][15:8] : w_crc_16_calculated[i][7:0];
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end
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end
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end else begin
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{r_tx_shift[3][7], r_tx_shift[2][7], r_tx_shift[1][7], r_tx_shift[0][7]} <= 4'b1111;
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end
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end
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end
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// Status shifting operation
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wire w_status_latch = r_state[STATE_STATUS] && i_sd_clk_strobe_rising;
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always @(posedge i_clk) begin
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if (w_status_latch) begin
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r_status <= {r_status[3:0], io_sd_dat[0]};
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end
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end
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endmodule
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