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https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-26 07:34:15 +01:00
63 lines
1.2 KiB
Systemverilog
63 lines
1.2 KiB
Systemverilog
module SummerCart64 (
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input i_clk,
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output o_ftdi_clk,
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output o_ftdi_si,
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input i_ftdi_so,
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input i_ftdi_cts,
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input i_n64_reset,
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input i_n64_nmi,
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output o_n64_int,
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input i_n64_pi_alel,
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input i_n64_pi_aleh,
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input i_n64_pi_read,
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input i_n64_pi_write,
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inout [15:0] io_n64_pi_ad,
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input i_n64_si_clk,
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inout io_n64_si_dq,
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output o_sdram_clk,
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output o_sdram_cs,
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output o_sdram_ras,
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output o_sdram_cas,
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output o_sdram_we,
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output [1:0] o_sdram_ba,
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output [12:0] o_sdram_a,
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inout [15:0] io_sdram_dq,
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output o_sd_clk,
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inout io_sd_cmd,
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inout [3:0] io_sd_dat,
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output o_rtc_scl,
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inout io_rtc_sda,
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output o_led,
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inout [7:0] io_pmod
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);
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if_pll if_pll_inst (.in_clk(i_clk));
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pll pll_inst (.iface(if_pll_inst));
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reg [31:0] counter;
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always_ff @(posedge if_pll_inst.sys.clk) begin
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counter <= counter + 1'd1;
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if (counter >= 32'd100_000_000) begin
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counter <= 1'd0;
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end
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end
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always_comb begin
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o_led = counter < 32'd1_000_000;
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end
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endmodule
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