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https://github.com/Polprzewodnikowy/SummerCart64.git
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53 lines
1.6 KiB
Systemverilog
53 lines
1.6 KiB
Systemverilog
module n64_lock (
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input clk,
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input reset,
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n64_reg_bus.lock reg_bus,
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n64_scb.lock n64_scb,
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);
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const bit [15:0] UNLOCK_SEQUENCE [4] = {
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16'h5F55,
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16'h4E4C,
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16'h4F43,
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16'h4B5F
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};
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always_comb begin
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reg_bus.rdata = 16'd0;
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end
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logic [1:0] sequence_counter;
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always_ff @(posedge clk) begin
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if (reset || n64_scb.n64_reset || n64_scb.n64_nmi) begin
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n64_scb.cfg_unlock <= 1'b0;
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sequence_counter <= 2'd0;
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end else begin
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if (reg_bus.write) begin
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if (reg_bus.address[16] && (reg_bus.address[15:2] == 14'd0)) begin
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for (int i = 0; i < $size(UNLOCK_SEQUENCE); i++) begin
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if (sequence_counter == i) begin
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if (reg_bus.wdata == UNLOCK_SEQUENCE[i]) begin
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sequence_counter <= sequence_counter + 1'd1;
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if (i == ($size(UNLOCK_SEQUENCE) - 1'd1)) begin
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n64_scb.cfg_unlock <= 1'b1;
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sequence_counter <= 2'd0;
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end
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end else begin
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n64_scb.cfg_unlock <= 1'b0;
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sequence_counter <= 2'd0;
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end
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end
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end
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end else begin
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n64_scb.cfg_unlock <= 1'b0;
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sequence_counter <= 2'd0;
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end
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end
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end
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end
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endmodule
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