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https://github.com/Polprzewodnikowy/SummerCart64.git
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96 lines
2.0 KiB
Verilog
96 lines
2.0 KiB
Verilog
// A version of the dhrystone test bench that isn't using the look-ahead interface
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`timescale 1 ns / 1 ps
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module testbench;
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reg clk = 1;
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reg resetn = 0;
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wire trap;
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always #5 clk = ~clk;
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initial begin
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repeat (100) @(posedge clk);
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resetn <= 1;
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end
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wire mem_valid;
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wire mem_instr;
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reg mem_ready;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [3:0] mem_wstrb;
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reg [31:0] mem_rdata;
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picorv32 #(
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.BARREL_SHIFTER(1),
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.ENABLE_FAST_MUL(1),
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.ENABLE_DIV(1),
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.PROGADDR_RESET('h10000),
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.STACKADDR('h10000)
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) uut (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_valid (mem_valid ),
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.mem_instr (mem_instr ),
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.mem_ready (mem_ready ),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (mem_rdata )
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);
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reg [7:0] memory [0:256*1024-1];
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initial $readmemh("dhry.hex", memory);
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always @(posedge clk) begin
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mem_ready <= 1'b0;
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mem_rdata[ 7: 0] <= 'bx;
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mem_rdata[15: 8] <= 'bx;
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mem_rdata[23:16] <= 'bx;
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mem_rdata[31:24] <= 'bx;
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if (mem_valid & !mem_ready) begin
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if (|mem_wstrb) begin
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mem_ready <= 1'b1;
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case (mem_addr)
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32'h1000_0000: begin
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$write("%c", mem_wdata);
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$fflush();
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end
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default: begin
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if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr + 2] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr + 3] <= mem_wdata[31:24];
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end
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endcase
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end
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else begin
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mem_ready <= 1'b1;
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mem_rdata[ 7: 0] <= memory[mem_addr + 0];
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mem_rdata[15: 8] <= memory[mem_addr + 1];
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mem_rdata[23:16] <= memory[mem_addr + 2];
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mem_rdata[31:24] <= memory[mem_addr + 3];
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end
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end
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end
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initial begin
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$dumpfile("testbench_nola.vcd");
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$dumpvars(0, testbench);
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end
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always @(posedge clk) begin
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if (resetn && trap) begin
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repeat (10) @(posedge clk);
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$display("TRAP");
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$finish;
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end
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end
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endmodule
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