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https://github.com/Polprzewodnikowy/SummerCart64.git
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148 lines
4.7 KiB
Verilog
148 lines
4.7 KiB
Verilog
module testbench (
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input clk,
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input resetn,
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output trap_0,
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output trap_1,
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output mem_axi_awvalid_0,
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input mem_axi_awready_0,
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output [31:0] mem_axi_awaddr_0,
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output [ 2:0] mem_axi_awprot_0,
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output mem_axi_awvalid_1,
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input mem_axi_awready_1,
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output [31:0] mem_axi_awaddr_1,
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output [ 2:0] mem_axi_awprot_1,
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output mem_axi_wvalid_0,
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input mem_axi_wready_0,
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output [31:0] mem_axi_wdata_0,
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output [ 3:0] mem_axi_wstrb_0,
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output mem_axi_wvalid_1,
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input mem_axi_wready_1,
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output [31:0] mem_axi_wdata_1,
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output [ 3:0] mem_axi_wstrb_1,
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input mem_axi_bvalid,
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output mem_axi_bready_0,
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output mem_axi_bready_1,
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output mem_axi_arvalid_0,
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input mem_axi_arready_0,
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output [31:0] mem_axi_araddr_0,
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output [ 2:0] mem_axi_arprot_0,
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output mem_axi_arvalid_1,
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input mem_axi_arready_1,
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output [31:0] mem_axi_araddr_1,
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output [ 2:0] mem_axi_arprot_1,
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input mem_axi_rvalid,
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output mem_axi_rready_0,
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output mem_axi_rready_1,
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input [31:0] mem_axi_rdata
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);
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picorv32_axi #(
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.ENABLE_COUNTERS(1),
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.ENABLE_COUNTERS64(1),
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.ENABLE_REGS_16_31(1),
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.ENABLE_REGS_DUALPORT(1),
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.BARREL_SHIFTER(1),
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.TWO_CYCLE_COMPARE(0),
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.TWO_CYCLE_ALU(0),
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.COMPRESSED_ISA(0),
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.CATCH_MISALIGN(1),
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.CATCH_ILLINSN(1)
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) uut_0 (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap_0 ),
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.mem_axi_awvalid (mem_axi_awvalid_0),
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.mem_axi_awready (mem_axi_awready_0),
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.mem_axi_awaddr (mem_axi_awaddr_0 ),
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.mem_axi_awprot (mem_axi_awprot_0 ),
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.mem_axi_wvalid (mem_axi_wvalid_0 ),
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.mem_axi_wready (mem_axi_wready_0 ),
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.mem_axi_wdata (mem_axi_wdata_0 ),
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.mem_axi_wstrb (mem_axi_wstrb_0 ),
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.mem_axi_bvalid (mem_axi_bvalid ),
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.mem_axi_bready (mem_axi_bready_0 ),
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.mem_axi_arvalid (mem_axi_arvalid_0),
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.mem_axi_arready (mem_axi_arready_0),
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.mem_axi_araddr (mem_axi_araddr_0 ),
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.mem_axi_arprot (mem_axi_arprot_0 ),
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.mem_axi_rvalid (mem_axi_rvalid ),
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.mem_axi_rready (mem_axi_rready_0 ),
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.mem_axi_rdata (mem_axi_rdata )
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);
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picorv32_axi #(
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.ENABLE_COUNTERS(1),
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.ENABLE_COUNTERS64(1),
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.ENABLE_REGS_16_31(1),
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.ENABLE_REGS_DUALPORT(1),
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.BARREL_SHIFTER(1),
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.TWO_CYCLE_COMPARE(0),
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.TWO_CYCLE_ALU(0),
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.COMPRESSED_ISA(0),
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.CATCH_MISALIGN(1),
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.CATCH_ILLINSN(1)
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) uut_1 (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap_1 ),
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.mem_axi_awvalid (mem_axi_awvalid_1),
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.mem_axi_awready (mem_axi_awready_1),
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.mem_axi_awaddr (mem_axi_awaddr_1 ),
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.mem_axi_awprot (mem_axi_awprot_1 ),
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.mem_axi_wvalid (mem_axi_wvalid_1 ),
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.mem_axi_wready (mem_axi_wready_1 ),
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.mem_axi_wdata (mem_axi_wdata_1 ),
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.mem_axi_wstrb (mem_axi_wstrb_1 ),
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.mem_axi_bvalid (mem_axi_bvalid ),
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.mem_axi_bready (mem_axi_bready_1 ),
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.mem_axi_arvalid (mem_axi_arvalid_1),
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.mem_axi_arready (mem_axi_arready_1),
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.mem_axi_araddr (mem_axi_araddr_1 ),
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.mem_axi_arprot (mem_axi_arprot_1 ),
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.mem_axi_rvalid (mem_axi_rvalid ),
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.mem_axi_rready (mem_axi_rready_1 ),
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.mem_axi_rdata (mem_axi_rdata )
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);
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always @(posedge clk) begin
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if (resetn && $past(resetn)) begin
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assert(trap_0 == trap_1 );
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assert(mem_axi_awvalid_0 == mem_axi_awvalid_1);
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assert(mem_axi_awaddr_0 == mem_axi_awaddr_1 );
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assert(mem_axi_awprot_0 == mem_axi_awprot_1 );
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assert(mem_axi_wvalid_0 == mem_axi_wvalid_1 );
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assert(mem_axi_wdata_0 == mem_axi_wdata_1 );
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assert(mem_axi_wstrb_0 == mem_axi_wstrb_1 );
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assert(mem_axi_bready_0 == mem_axi_bready_1 );
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assert(mem_axi_arvalid_0 == mem_axi_arvalid_1);
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assert(mem_axi_araddr_0 == mem_axi_araddr_1 );
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assert(mem_axi_arprot_0 == mem_axi_arprot_1 );
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assert(mem_axi_rready_0 == mem_axi_rready_1 );
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if (mem_axi_awvalid_0) assume(mem_axi_awready_0 == mem_axi_awready_1);
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if (mem_axi_wvalid_0 ) assume(mem_axi_wready_0 == mem_axi_wready_1 );
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if (mem_axi_arvalid_0) assume(mem_axi_arready_0 == mem_axi_arready_1);
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if ($fell(mem_axi_awready_0)) assume($past(mem_axi_awvalid_0));
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if ($fell(mem_axi_wready_0 )) assume($past(mem_axi_wvalid_0 ));
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if ($fell(mem_axi_arready_0)) assume($past(mem_axi_arvalid_0));
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if ($fell(mem_axi_awready_1)) assume($past(mem_axi_awvalid_1));
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if ($fell(mem_axi_wready_1 )) assume($past(mem_axi_wvalid_1 ));
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if ($fell(mem_axi_arready_1)) assume($past(mem_axi_arvalid_1));
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if ($fell(mem_axi_bvalid)) assume($past(mem_axi_bready_0));
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if ($fell(mem_axi_rvalid)) assume($past(mem_axi_rready_0));
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if (mem_axi_rvalid && $past(mem_axi_rvalid)) assume($stable(mem_axi_rdata));
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end
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end
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endmodule
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