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https://github.com/Polprzewodnikowy/SummerCart64.git
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55 lines
1.3 KiB
Systemverilog
55 lines
1.3 KiB
Systemverilog
interface if_cpu_bus ();
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localparam [3:0] NUM_DEVICES = sc64::__ID_CPU_END;
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logic request;
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logic ack;
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logic [3:0] wmask;
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logic [31:0] address;
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logic [31:0] wdata;
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logic [31:0] rdata;
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logic device_ack [(NUM_DEVICES - 1):0];
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logic [31:0] device_rdata [(NUM_DEVICES - 1):0];
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always_comb begin
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ack = 1'b0;
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rdata = 32'd0;
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for (integer i = 0; i < NUM_DEVICES; i++) begin
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ack = ack | device_ack[i];
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rdata = rdata | device_rdata[i];
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end
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end
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modport cpu (
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output request,
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input ack,
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output wmask,
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output address,
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output wdata,
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input rdata
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);
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genvar n;
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generate
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for (n = 0; n < NUM_DEVICES; n++) begin : at
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logic device_request;
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always_comb begin
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device_request = request && address[31:28] == n[3:0];
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end
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modport device (
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input .request(device_request),
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output .ack(device_ack[n]),
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input .wmask(wmask),
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input .address(address),
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input .wdata(wdata),
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output .rdata(device_rdata[n])
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);
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end
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endgenerate
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endinterface
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