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https://github.com/Polprzewodnikowy/SummerCart64.git
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85 lines
2.3 KiB
Verilog
85 lines
2.3 KiB
Verilog
`default_nettype none
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module serv_ctrl
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#(parameter RESET_STRATEGY = "MINI",
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parameter RESET_PC = 32'd0,
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parameter WITH_CSR = 1)
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(
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input wire clk,
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input wire i_rst,
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//State
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input wire i_pc_en,
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input wire i_cnt12to31,
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input wire i_cnt0,
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input wire i_cnt1,
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input wire i_cnt2,
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//Control
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input wire i_jump,
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input wire i_jal_or_jalr,
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input wire i_utype,
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input wire i_pc_rel,
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input wire i_trap,
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input wire i_iscomp,
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//Data
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input wire i_imm,
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input wire i_buf,
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input wire i_csr_pc,
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output wire o_rd,
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output wire o_bad_pc,
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//External
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output reg [31:0] o_ibus_adr);
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wire pc_plus_4;
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wire pc_plus_4_cy;
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reg pc_plus_4_cy_r;
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wire pc_plus_offset;
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wire pc_plus_offset_cy;
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reg pc_plus_offset_cy_r;
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wire pc_plus_offset_aligned;
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wire plus_4;
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wire pc = o_ibus_adr[0];
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wire new_pc;
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wire offset_a;
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wire offset_b;
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/* If i_iscomp=1: increment pc by 2 else increment pc by 4 */
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assign plus_4 = i_iscomp ? i_cnt1 : i_cnt2;
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assign o_bad_pc = pc_plus_offset_aligned;
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assign {pc_plus_4_cy,pc_plus_4} = pc+plus_4+pc_plus_4_cy_r;
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generate
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if (|WITH_CSR) begin : gen_csr
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assign new_pc = i_trap ? (i_csr_pc & !i_cnt0) : i_jump ? pc_plus_offset_aligned : pc_plus_4;
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end else begin : gen_no_csr
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assign new_pc = i_jump ? pc_plus_offset_aligned : pc_plus_4;
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end
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endgenerate
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assign o_rd = (i_utype & pc_plus_offset_aligned) | (pc_plus_4 & i_jal_or_jalr);
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assign offset_a = i_pc_rel & pc;
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assign offset_b = i_utype ? (i_imm & i_cnt12to31): i_buf;
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assign {pc_plus_offset_cy,pc_plus_offset} = offset_a+offset_b+pc_plus_offset_cy_r;
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assign pc_plus_offset_aligned = pc_plus_offset & !i_cnt0;
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initial if (RESET_STRATEGY == "NONE") o_ibus_adr = RESET_PC;
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always @(posedge clk) begin
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pc_plus_4_cy_r <= i_pc_en & pc_plus_4_cy;
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pc_plus_offset_cy_r <= i_pc_en & pc_plus_offset_cy;
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if (RESET_STRATEGY == "NONE") begin
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if (i_pc_en)
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o_ibus_adr <= {new_pc, o_ibus_adr[31:1]};
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end else begin
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if (i_pc_en | i_rst)
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o_ibus_adr <= i_rst ? RESET_PC : {new_pc, o_ibus_adr[31:1]};
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end
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end
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endmodule
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