mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-25 15:16:53 +01:00
366 lines
13 KiB
Verilog
366 lines
13 KiB
Verilog
`default_nettype none
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module serv_decode
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#(parameter [0:0] PRE_REGISTER = 1,
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parameter [0:0] MDU = 0)
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(
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input wire clk,
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//Input
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input wire [31:2] i_wb_rdt,
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input wire i_wb_en,
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//To state
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output reg o_sh_right,
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output reg o_bne_or_bge,
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output reg o_cond_branch,
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output reg o_e_op,
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output reg o_ebreak,
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output reg o_branch_op,
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output reg o_shift_op,
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output reg o_slt_or_branch,
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output reg o_rd_op,
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output reg o_two_stage_op,
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output reg o_dbus_en,
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//MDU
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output reg o_mdu_op,
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//Extension
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output reg [2:0] o_ext_funct3,
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//To bufreg
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output reg o_bufreg_rs1_en,
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output reg o_bufreg_imm_en,
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output reg o_bufreg_clr_lsb,
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output reg o_bufreg_sh_signed,
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//To ctrl
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output reg o_ctrl_jal_or_jalr,
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output reg o_ctrl_utype,
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output reg o_ctrl_pc_rel,
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output reg o_ctrl_mret,
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//To alu
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output reg o_alu_sub,
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output reg [1:0] o_alu_bool_op,
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output reg o_alu_cmp_eq,
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output reg o_alu_cmp_sig,
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output reg [2:0] o_alu_rd_sel,
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//To mem IF
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output reg o_mem_signed,
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output reg o_mem_word,
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output reg o_mem_half,
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output reg o_mem_cmd,
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//To CSR
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output reg o_csr_en,
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output reg [1:0] o_csr_addr,
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output reg o_csr_mstatus_en,
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output reg o_csr_mie_en,
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output reg o_csr_mcause_en,
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output reg [1:0] o_csr_source,
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output reg o_csr_d_sel,
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output reg o_csr_imm_en,
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output reg o_mtval_pc,
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//To top
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output reg [3:0] o_immdec_ctrl,
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output reg [3:0] o_immdec_en,
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output reg o_op_b_source,
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//To RF IF
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output reg o_rd_mem_en,
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output reg o_rd_csr_en,
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output reg o_rd_alu_en);
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reg [4:0] opcode;
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reg [2:0] funct3;
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reg op20;
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reg op21;
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reg op22;
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reg op26;
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reg imm25;
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reg imm30;
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wire co_mdu_op = MDU & (opcode == 5'b01100) & imm25;
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wire co_two_stage_op =
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~opcode[2] | (funct3[0] & ~funct3[1] & ~opcode[0] & ~opcode[4]) |
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(funct3[1] & ~funct3[2] & ~opcode[0] & ~opcode[4]) | co_mdu_op;
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wire co_shift_op = (opcode[2] & ~funct3[1]) & !co_mdu_op;
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wire co_slt_or_branch = (opcode[4] | (funct3[1] & opcode[2]) | (imm30 & opcode[2] & opcode[3] & ~funct3[2])) & !co_mdu_op;
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wire co_branch_op = opcode[4];
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wire co_dbus_en = ~opcode[2] & ~opcode[4];
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wire co_mtval_pc = opcode[4];
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wire co_mem_word = funct3[1];
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wire co_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4] & !co_mdu_op;
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wire co_rd_mem_en = (!opcode[2] & !opcode[0]) | co_mdu_op;
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wire [2:0] co_ext_funct3 = funct3;
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//jal,branch = imm
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//jalr = rs1+imm
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//mem = rs1+imm
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//shift = rs1
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wire co_bufreg_rs1_en = !opcode[4] | (!opcode[1] & opcode[0]);
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wire co_bufreg_imm_en = !opcode[2];
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//Clear LSB of immediate for BRANCH and JAL ops
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//True for BRANCH and JAL
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//False for JALR/LOAD/STORE/OP/OPIMM?
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wire co_bufreg_clr_lsb = opcode[4] & ((opcode[1:0] == 2'b00) | (opcode[1:0] == 2'b11));
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//Conditional branch
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//True for BRANCH
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//False for JAL/JALR
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wire co_cond_branch = !opcode[0];
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wire co_ctrl_utype = !opcode[4] & opcode[2] & opcode[0];
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wire co_ctrl_jal_or_jalr = opcode[4] & opcode[0];
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//PC-relative operations
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//True for jal, b* auipc, ebreak
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//False for jalr, lui
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wire co_ctrl_pc_rel = (opcode[2:0] == 3'b000) |
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(opcode[1:0] == 2'b11) |
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(opcode[4] & opcode[2]) & op20|
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(opcode[4:3] == 2'b00);
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//Write to RD
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//True for OP-IMM, AUIPC, OP, LUI, SYSTEM, JALR, JAL, LOAD
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//False for STORE, BRANCH, MISC-MEM
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wire co_rd_op = (opcode[2] |
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(!opcode[2] & opcode[4] & opcode[0]) |
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(!opcode[2] & !opcode[3] & !opcode[0]));
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//
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//funct3
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//
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wire co_sh_right = funct3[2];
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wire co_bne_or_bge = funct3[0];
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//Matches system ops except eceall/ebreak/mret
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wire csr_op = opcode[4] & opcode[2] & (|funct3);
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//op20
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wire co_ebreak = op20;
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//opcode & funct3 & op21
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wire co_ctrl_mret = opcode[4] & opcode[2] & op21 & !(|funct3);
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//Matches system opcodes except CSR accesses (funct3 == 0)
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//and mret (!op21)
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wire co_e_op = opcode[4] & opcode[2] & !op21 & !(|funct3);
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//opcode & funct3 & imm30
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wire co_bufreg_sh_signed = imm30;
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/*
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True for sub, b*, slt*
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False for add*
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op opcode f3 i30
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b* 11000 xxx x t
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addi 00100 000 x f
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slt* 0x100 01x x t
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add 01100 000 0 f
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sub 01100 000 1 t
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*/
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wire co_alu_sub = funct3[1] | funct3[0] | (opcode[3] & imm30) | opcode[4];
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/*
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Bits 26, 22, 21 and 20 are enough to uniquely identify the eight supported CSR regs
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mtvec, mscratch, mepc and mtval are stored externally (normally in the RF) and are
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treated differently from mstatus, mie and mcause which are stored in serv_csr.
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The former get a 2-bit address as seen below while the latter get a
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one-hot enable signal each.
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Hex|2 222|Reg |csr
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adr|6 210|name |addr
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---|-----|--------|----
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300|0_000|mstatus | xx
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304|0_100|mie | xx
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305|0_101|mtvec | 01
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340|1_000|mscratch| 00
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341|1_001|mepc | 10
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342|1_010|mcause | xx
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343|1_011|mtval | 11
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*/
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//true for mtvec,mscratch,mepc and mtval
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//false for mstatus, mie, mcause
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wire csr_valid = op20 | (op26 & !op21);
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wire co_rd_csr_en = csr_op;
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wire co_csr_en = csr_op & csr_valid;
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wire co_csr_mstatus_en = csr_op & !op26 & !op22;
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wire co_csr_mie_en = csr_op & !op26 & op22 & !op20;
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wire co_csr_mcause_en = csr_op & op21 & !op20;
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wire [1:0] co_csr_source = funct3[1:0];
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wire co_csr_d_sel = funct3[2];
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wire co_csr_imm_en = opcode[4] & opcode[2] & funct3[2];
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wire [1:0] co_csr_addr = {op26 & op20, !op26 | op21};
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wire co_alu_cmp_eq = funct3[2:1] == 2'b00;
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wire co_alu_cmp_sig = ~((funct3[0] & funct3[1]) | (funct3[1] & funct3[2]));
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wire co_mem_cmd = opcode[3];
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wire co_mem_signed = ~funct3[2];
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wire co_mem_half = funct3[0];
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wire [1:0] co_alu_bool_op = funct3[1:0];
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wire [3:0] co_immdec_ctrl;
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//True for S (STORE) or B (BRANCH) type instructions
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//False for J type instructions
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assign co_immdec_ctrl[0] = opcode[3:0] == 4'b1000;
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//True for OP-IMM, LOAD, STORE, JALR (I S)
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//False for LUI, AUIPC, JAL (U J)
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assign co_immdec_ctrl[1] = (opcode[1:0] == 2'b00) | (opcode[2:1] == 2'b00);
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assign co_immdec_ctrl[2] = opcode[4] & !opcode[0];
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assign co_immdec_ctrl[3] = opcode[4];
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wire [3:0] co_immdec_en;
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assign co_immdec_en[3] = opcode[4] | opcode[3] | opcode[2] | !opcode[0]; //B I J S U
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assign co_immdec_en[2] = (opcode[4] & opcode[2]) | !opcode[3] | opcode[0]; // I J U
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assign co_immdec_en[1] = (opcode[2:1] == 2'b01) | (opcode[2] & opcode[0]) | co_csr_imm_en;// J U
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assign co_immdec_en[0] = ~co_rd_op; //B S
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wire [2:0] co_alu_rd_sel;
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assign co_alu_rd_sel[0] = (funct3 == 3'b000); // Add/sub
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assign co_alu_rd_sel[1] = (funct3[2:1] == 2'b01); //SLT*
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assign co_alu_rd_sel[2] = funct3[2]; //Bool
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//0 (OP_B_SOURCE_IMM) when OPIMM
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//1 (OP_B_SOURCE_RS2) when BRANCH or OP
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wire co_op_b_source = opcode[3];
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generate
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if (PRE_REGISTER) begin : gen_pre_register
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always @(posedge clk) begin
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if (i_wb_en) begin
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funct3 <= i_wb_rdt[14:12];
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imm30 <= i_wb_rdt[30];
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imm25 <= i_wb_rdt[25];
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opcode <= i_wb_rdt[6:2];
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op20 <= i_wb_rdt[20];
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op21 <= i_wb_rdt[21];
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op22 <= i_wb_rdt[22];
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op26 <= i_wb_rdt[26];
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end
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end
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always @(*) begin
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o_sh_right = co_sh_right;
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o_bne_or_bge = co_bne_or_bge;
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o_cond_branch = co_cond_branch;
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o_dbus_en = co_dbus_en;
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o_mtval_pc = co_mtval_pc;
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o_two_stage_op = co_two_stage_op;
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o_e_op = co_e_op;
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o_ebreak = co_ebreak;
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o_branch_op = co_branch_op;
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o_shift_op = co_shift_op;
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o_slt_or_branch = co_slt_or_branch;
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o_rd_op = co_rd_op;
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o_mdu_op = co_mdu_op;
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o_ext_funct3 = co_ext_funct3;
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o_bufreg_rs1_en = co_bufreg_rs1_en;
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o_bufreg_imm_en = co_bufreg_imm_en;
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o_bufreg_clr_lsb = co_bufreg_clr_lsb;
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o_bufreg_sh_signed = co_bufreg_sh_signed;
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o_ctrl_jal_or_jalr = co_ctrl_jal_or_jalr;
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o_ctrl_utype = co_ctrl_utype;
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o_ctrl_pc_rel = co_ctrl_pc_rel;
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o_ctrl_mret = co_ctrl_mret;
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o_alu_sub = co_alu_sub;
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o_alu_bool_op = co_alu_bool_op;
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o_alu_cmp_eq = co_alu_cmp_eq;
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o_alu_cmp_sig = co_alu_cmp_sig;
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o_alu_rd_sel = co_alu_rd_sel;
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o_mem_signed = co_mem_signed;
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o_mem_word = co_mem_word;
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o_mem_half = co_mem_half;
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o_mem_cmd = co_mem_cmd;
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o_csr_en = co_csr_en;
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o_csr_addr = co_csr_addr;
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o_csr_mstatus_en = co_csr_mstatus_en;
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o_csr_mie_en = co_csr_mie_en;
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o_csr_mcause_en = co_csr_mcause_en;
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o_csr_source = co_csr_source;
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o_csr_d_sel = co_csr_d_sel;
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o_csr_imm_en = co_csr_imm_en;
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o_immdec_ctrl = co_immdec_ctrl;
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o_immdec_en = co_immdec_en;
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o_op_b_source = co_op_b_source;
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o_rd_csr_en = co_rd_csr_en;
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o_rd_alu_en = co_rd_alu_en;
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o_rd_mem_en = co_rd_mem_en;
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end
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end else begin : gen_post_register
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always @(*) begin
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funct3 = i_wb_rdt[14:12];
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imm30 = i_wb_rdt[30];
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imm25 = i_wb_rdt[25];
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opcode = i_wb_rdt[6:2];
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op20 = i_wb_rdt[20];
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op21 = i_wb_rdt[21];
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op22 = i_wb_rdt[22];
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op26 = i_wb_rdt[26];
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end
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always @(posedge clk) begin
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if (i_wb_en) begin
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o_sh_right <= co_sh_right;
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o_bne_or_bge <= co_bne_or_bge;
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o_cond_branch <= co_cond_branch;
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o_e_op <= co_e_op;
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o_ebreak <= co_ebreak;
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o_two_stage_op <= co_two_stage_op;
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o_dbus_en <= co_dbus_en;
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o_mtval_pc <= co_mtval_pc;
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o_branch_op <= co_branch_op;
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o_shift_op <= co_shift_op;
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o_slt_or_branch <= co_slt_or_branch;
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o_rd_op <= co_rd_op;
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o_mdu_op <= co_mdu_op;
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o_ext_funct3 <= co_ext_funct3;
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o_bufreg_rs1_en <= co_bufreg_rs1_en;
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o_bufreg_imm_en <= co_bufreg_imm_en;
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o_bufreg_clr_lsb <= co_bufreg_clr_lsb;
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o_bufreg_sh_signed <= co_bufreg_sh_signed;
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o_ctrl_jal_or_jalr <= co_ctrl_jal_or_jalr;
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o_ctrl_utype <= co_ctrl_utype;
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o_ctrl_pc_rel <= co_ctrl_pc_rel;
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o_ctrl_mret <= co_ctrl_mret;
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o_alu_sub <= co_alu_sub;
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o_alu_bool_op <= co_alu_bool_op;
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o_alu_cmp_eq <= co_alu_cmp_eq;
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o_alu_cmp_sig <= co_alu_cmp_sig;
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o_alu_rd_sel <= co_alu_rd_sel;
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o_mem_signed <= co_mem_signed;
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o_mem_word <= co_mem_word;
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o_mem_half <= co_mem_half;
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o_mem_cmd <= co_mem_cmd;
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o_csr_en <= co_csr_en;
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o_csr_addr <= co_csr_addr;
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o_csr_mstatus_en <= co_csr_mstatus_en;
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o_csr_mie_en <= co_csr_mie_en;
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o_csr_mcause_en <= co_csr_mcause_en;
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o_csr_source <= co_csr_source;
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o_csr_d_sel <= co_csr_d_sel;
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o_csr_imm_en <= co_csr_imm_en;
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o_immdec_ctrl <= co_immdec_ctrl;
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o_immdec_en <= co_immdec_en;
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o_op_b_source <= co_op_b_source;
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o_rd_csr_en <= co_rd_csr_en;
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o_rd_alu_en <= co_rd_alu_en;
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o_rd_mem_en <= co_rd_mem_en;
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end
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end
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end
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endgenerate
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endmodule
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