mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-25 15:16:53 +01:00
660 lines
17 KiB
Verilog
660 lines
17 KiB
Verilog
`default_nettype none
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module serv_top
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#(parameter WITH_CSR = 1,
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parameter PRE_REGISTER = 1,
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parameter RESET_STRATEGY = "MINI",
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parameter RESET_PC = 32'd0,
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parameter [0:0] MDU = 1'b0,
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parameter [0:0] COMPRESSED=0,
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parameter [0:0] ALIGN = COMPRESSED)
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(
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input wire clk,
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input wire i_rst,
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input wire i_timer_irq,
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`ifdef RISCV_FORMAL
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output reg rvfi_valid = 1'b0,
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output reg [63:0] rvfi_order = 64'd0,
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output reg [31:0] rvfi_insn = 32'd0,
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output reg rvfi_trap = 1'b0,
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output reg rvfi_halt = 1'b0,
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output reg rvfi_intr = 1'b0,
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output reg [1:0] rvfi_mode = 2'b11,
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output reg [1:0] rvfi_ixl = 2'b01,
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output reg [4:0] rvfi_rs1_addr,
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output reg [4:0] rvfi_rs2_addr,
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output reg [31:0] rvfi_rs1_rdata,
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output reg [31:0] rvfi_rs2_rdata,
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output reg [4:0] rvfi_rd_addr,
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output reg [31:0] rvfi_rd_wdata,
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output reg [31:0] rvfi_pc_rdata,
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output reg [31:0] rvfi_pc_wdata,
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output reg [31:0] rvfi_mem_addr,
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output reg [3:0] rvfi_mem_rmask,
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output reg [3:0] rvfi_mem_wmask,
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output reg [31:0] rvfi_mem_rdata,
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output reg [31:0] rvfi_mem_wdata,
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`endif
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//RF Interface
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output wire o_rf_rreq,
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output wire o_rf_wreq,
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input wire i_rf_ready,
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output wire [4+WITH_CSR:0] o_wreg0,
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output wire [4+WITH_CSR:0] o_wreg1,
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output wire o_wen0,
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output wire o_wen1,
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output wire o_wdata0,
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output wire o_wdata1,
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output wire [4+WITH_CSR:0] o_rreg0,
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output wire [4+WITH_CSR:0] o_rreg1,
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input wire i_rdata0,
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input wire i_rdata1,
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output wire [31:0] o_ibus_adr,
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output wire o_ibus_cyc,
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input wire [31:0] i_ibus_rdt,
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input wire i_ibus_ack,
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output wire [31:0] o_dbus_adr,
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output wire [31:0] o_dbus_dat,
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output wire [3:0] o_dbus_sel,
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output wire o_dbus_we ,
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output wire o_dbus_cyc,
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input wire [31:0] i_dbus_rdt,
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input wire i_dbus_ack,
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//Extension
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output wire [ 2:0] o_ext_funct3,
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input wire i_ext_ready,
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input wire [31:0] i_ext_rd,
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output wire [31:0] o_ext_rs1,
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output wire [31:0] o_ext_rs2,
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//MDU
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output wire o_mdu_valid);
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wire [4:0] rd_addr;
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wire [4:0] rs1_addr;
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wire [4:0] rs2_addr;
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wire [3:0] immdec_ctrl;
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wire [3:0] immdec_en;
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wire sh_right;
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wire bne_or_bge;
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wire cond_branch;
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wire two_stage_op;
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wire e_op;
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wire ebreak;
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wire branch_op;
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wire shift_op;
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wire slt_or_branch;
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wire rd_op;
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wire mdu_op;
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wire rd_alu_en;
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wire rd_csr_en;
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wire rd_mem_en;
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wire ctrl_rd;
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wire alu_rd;
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wire mem_rd;
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wire csr_rd;
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wire mtval_pc;
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wire ctrl_pc_en;
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wire jump;
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wire jal_or_jalr;
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wire utype;
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wire mret;
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wire imm;
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wire trap;
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wire pc_rel;
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wire iscomp;
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wire init;
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wire cnt_en;
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wire cnt0to3;
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wire cnt12to31;
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wire cnt0;
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wire cnt1;
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wire cnt2;
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wire cnt3;
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wire cnt7;
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wire cnt_done;
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wire bufreg_en;
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wire bufreg_sh_signed;
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wire bufreg_rs1_en;
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wire bufreg_imm_en;
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wire bufreg_clr_lsb;
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wire bufreg_q;
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wire bufreg2_q;
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wire [31:0] dbus_rdt;
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wire dbus_ack;
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wire alu_sub;
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wire [1:0] alu_bool_op;
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wire alu_cmp_eq;
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wire alu_cmp_sig;
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wire alu_cmp;
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wire [2:0] alu_rd_sel;
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wire rs1;
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wire rs2;
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wire rd_en;
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wire op_b;
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wire op_b_sel;
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wire mem_signed;
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wire mem_word;
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wire mem_half;
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wire [1:0] mem_bytecnt;
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wire sh_done;
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wire sh_done_r;
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wire byte_valid;
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wire mem_misalign;
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wire bad_pc;
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wire csr_mstatus_en;
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wire csr_mie_en;
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wire csr_mcause_en;
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wire [1:0] csr_source;
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wire csr_imm;
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wire csr_d_sel;
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wire csr_en;
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wire [1:0] csr_addr;
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wire csr_pc;
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wire csr_imm_en;
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wire csr_in;
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wire rf_csr_out;
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wire dbus_en;
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wire new_irq;
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wire [1:0] lsb;
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wire [31:0] i_wb_rdt;
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wire [31:0] wb_ibus_adr;
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wire wb_ibus_cyc;
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wire [31:0] wb_ibus_rdt;
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wire wb_ibus_ack;
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generate
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if (ALIGN) begin : gen_align
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serv_aligner align
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(
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.clk(clk),
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.rst(i_rst),
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// serv_rf_top
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.i_ibus_adr(wb_ibus_adr),
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.i_ibus_cyc(wb_ibus_cyc),
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.o_ibus_rdt(wb_ibus_rdt),
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.o_ibus_ack(wb_ibus_ack),
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// servant_arbiter
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.o_wb_ibus_adr(o_ibus_adr),
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.o_wb_ibus_cyc(o_ibus_cyc),
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.i_wb_ibus_rdt(i_ibus_rdt),
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.i_wb_ibus_ack(i_ibus_ack));
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end else begin : gen_no_align
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assign o_ibus_adr = wb_ibus_adr;
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assign o_ibus_cyc = wb_ibus_cyc;
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assign wb_ibus_rdt = i_ibus_rdt;
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assign wb_ibus_ack = i_ibus_ack;
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end
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endgenerate
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generate
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if (COMPRESSED) begin : gen_compressed
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serv_compdec compdec
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(
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.i_clk(clk),
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.i_instr(wb_ibus_rdt),
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.i_ack(wb_ibus_ack),
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.o_instr(i_wb_rdt),
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.o_iscomp(iscomp));
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end else begin : gen_no_compressed
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assign i_wb_rdt = wb_ibus_rdt;
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assign iscomp = 1'b0;
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end
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endgenerate
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serv_state
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#(.RESET_STRATEGY (RESET_STRATEGY),
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.WITH_CSR (WITH_CSR[0:0]),
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.MDU(MDU),
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.ALIGN(ALIGN))
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state
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(
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.i_clk (clk),
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.i_rst (i_rst),
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//State
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.i_new_irq (new_irq),
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.i_alu_cmp (alu_cmp),
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.o_init (init),
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.o_cnt_en (cnt_en),
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.o_cnt0to3 (cnt0to3),
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.o_cnt12to31 (cnt12to31),
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.o_cnt0 (cnt0),
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.o_cnt1 (cnt1),
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.o_cnt2 (cnt2),
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.o_cnt3 (cnt3),
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.o_cnt7 (cnt7),
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.o_cnt_done (cnt_done),
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.o_bufreg_en (bufreg_en),
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.o_ctrl_pc_en (ctrl_pc_en),
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.o_ctrl_jump (jump),
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.o_ctrl_trap (trap),
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.i_ctrl_misalign(lsb[1]),
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.i_sh_done (sh_done),
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.i_sh_done_r (sh_done_r),
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.o_mem_bytecnt (mem_bytecnt),
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.i_mem_misalign (mem_misalign),
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//Control
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.i_bne_or_bge (bne_or_bge),
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.i_cond_branch (cond_branch),
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.i_dbus_en (dbus_en),
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.i_two_stage_op (two_stage_op),
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.i_branch_op (branch_op),
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.i_shift_op (shift_op),
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.i_sh_right (sh_right),
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.i_slt_or_branch (slt_or_branch),
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.i_e_op (e_op),
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.i_rd_op (rd_op),
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//MDU
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.i_mdu_op (mdu_op),
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.o_mdu_valid (o_mdu_valid),
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//Extension
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.i_mdu_ready (i_ext_ready),
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//External
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.o_dbus_cyc (o_dbus_cyc),
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.i_dbus_ack (i_dbus_ack),
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.o_ibus_cyc (wb_ibus_cyc),
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.i_ibus_ack (wb_ibus_ack),
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//RF Interface
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.o_rf_rreq (o_rf_rreq),
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.o_rf_wreq (o_rf_wreq),
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.i_rf_ready (i_rf_ready),
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.o_rf_rd_en (rd_en));
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serv_decode
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#(.PRE_REGISTER (PRE_REGISTER),
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.MDU(MDU))
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decode
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(
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.clk (clk),
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//Input
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.i_wb_rdt (i_wb_rdt[31:2]),
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.i_wb_en (wb_ibus_ack),
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//To state
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.o_bne_or_bge (bne_or_bge),
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.o_cond_branch (cond_branch),
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.o_dbus_en (dbus_en),
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.o_e_op (e_op),
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.o_ebreak (ebreak),
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.o_branch_op (branch_op),
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.o_shift_op (shift_op),
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.o_slt_or_branch (slt_or_branch),
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.o_rd_op (rd_op),
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.o_sh_right (sh_right),
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.o_mdu_op (mdu_op),
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.o_two_stage_op (two_stage_op),
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//Extension
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.o_ext_funct3 (o_ext_funct3),
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//To bufreg
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.o_bufreg_rs1_en (bufreg_rs1_en),
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.o_bufreg_imm_en (bufreg_imm_en),
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.o_bufreg_clr_lsb (bufreg_clr_lsb),
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.o_bufreg_sh_signed (bufreg_sh_signed),
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//To bufreg2
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.o_op_b_source (op_b_sel),
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//To ctrl
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.o_ctrl_jal_or_jalr (jal_or_jalr),
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.o_ctrl_utype (utype),
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.o_ctrl_pc_rel (pc_rel),
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.o_ctrl_mret (mret),
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//To alu
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.o_alu_sub (alu_sub),
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.o_alu_bool_op (alu_bool_op),
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.o_alu_cmp_eq (alu_cmp_eq),
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.o_alu_cmp_sig (alu_cmp_sig),
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.o_alu_rd_sel (alu_rd_sel),
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//To mem IF
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.o_mem_cmd (o_dbus_we),
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.o_mem_signed (mem_signed),
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.o_mem_word (mem_word),
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.o_mem_half (mem_half),
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//To CSR
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.o_csr_en (csr_en),
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.o_csr_addr (csr_addr),
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.o_csr_mstatus_en (csr_mstatus_en),
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.o_csr_mie_en (csr_mie_en),
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.o_csr_mcause_en (csr_mcause_en),
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.o_csr_source (csr_source),
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.o_csr_d_sel (csr_d_sel),
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.o_csr_imm_en (csr_imm_en),
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.o_mtval_pc (mtval_pc ),
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//To top
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.o_immdec_ctrl (immdec_ctrl),
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.o_immdec_en (immdec_en),
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//To RF IF
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.o_rd_mem_en (rd_mem_en),
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.o_rd_csr_en (rd_csr_en),
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.o_rd_alu_en (rd_alu_en));
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serv_immdec immdec
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(
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.i_clk (clk),
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//State
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.i_cnt_en (cnt_en),
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.i_cnt_done (cnt_done),
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//Control
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.i_immdec_en (immdec_en),
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.i_csr_imm_en (csr_imm_en),
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.i_ctrl (immdec_ctrl),
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.o_rd_addr (rd_addr),
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.o_rs1_addr (rs1_addr),
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.o_rs2_addr (rs2_addr),
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//Data
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.o_csr_imm (csr_imm),
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.o_imm (imm),
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//External
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.i_wb_en (wb_ibus_ack),
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.i_wb_rdt (i_wb_rdt[31:7]));
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serv_bufreg
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#(.MDU(MDU))
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bufreg
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(
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.i_clk (clk),
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//State
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.i_cnt0 (cnt0),
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.i_cnt1 (cnt1),
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.i_en (bufreg_en),
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.i_init (init),
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.i_mdu_op (mdu_op),
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.o_lsb (lsb),
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//Control
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.i_sh_signed (bufreg_sh_signed),
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.i_rs1_en (bufreg_rs1_en),
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.i_imm_en (bufreg_imm_en),
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.i_clr_lsb (bufreg_clr_lsb),
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//Data
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.i_rs1 (rs1),
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.i_imm (imm),
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.o_q (bufreg_q),
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//External
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.o_dbus_adr (o_dbus_adr),
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.o_ext_rs1 (o_ext_rs1));
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serv_bufreg2 bufreg2
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(
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.i_clk (clk),
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//State
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.i_en (cnt_en),
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.i_init (init),
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.i_cnt_done (cnt_done),
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.i_lsb (lsb),
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.i_byte_valid (byte_valid),
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.o_sh_done (sh_done),
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.o_sh_done_r (sh_done_r),
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//Control
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.i_op_b_sel (op_b_sel),
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.i_shift_op (shift_op),
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//Data
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.i_rs2 (rs2),
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.i_imm (imm),
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.o_op_b (op_b),
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.o_q (bufreg2_q),
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//External
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.o_dat (o_dbus_dat),
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.i_load (dbus_ack),
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.i_dat (dbus_rdt));
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serv_ctrl
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#(.RESET_PC (RESET_PC),
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.RESET_STRATEGY (RESET_STRATEGY),
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.WITH_CSR (WITH_CSR))
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ctrl
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(
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.clk (clk),
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.i_rst (i_rst),
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//State
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.i_pc_en (ctrl_pc_en),
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.i_cnt12to31 (cnt12to31),
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.i_cnt0 (cnt0),
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.i_cnt1 (cnt1),
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.i_cnt2 (cnt2),
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//Control
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.i_jump (jump),
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.i_jal_or_jalr (jal_or_jalr),
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.i_utype (utype),
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.i_pc_rel (pc_rel),
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.i_trap (trap | mret),
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.i_iscomp (iscomp),
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//Data
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.i_imm (imm),
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.i_buf (bufreg_q),
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.i_csr_pc (csr_pc),
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.o_rd (ctrl_rd),
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.o_bad_pc (bad_pc),
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//External
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.o_ibus_adr (wb_ibus_adr));
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serv_alu alu
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(
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.clk (clk),
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//State
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.i_en (cnt_en),
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.i_cnt0 (cnt0),
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.o_cmp (alu_cmp),
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//Control
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.i_sub (alu_sub),
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.i_bool_op (alu_bool_op),
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.i_cmp_eq (alu_cmp_eq),
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.i_cmp_sig (alu_cmp_sig),
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.i_rd_sel (alu_rd_sel),
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//Data
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.i_rs1 (rs1),
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.i_op_b (op_b),
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.i_buf (bufreg_q),
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.o_rd (alu_rd));
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serv_rf_if
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#(.WITH_CSR (WITH_CSR))
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rf_if
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(//RF interface
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.i_cnt_en (cnt_en),
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.o_wreg0 (o_wreg0),
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.o_wreg1 (o_wreg1),
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.o_wen0 (o_wen0),
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.o_wen1 (o_wen1),
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.o_wdata0 (o_wdata0),
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.o_wdata1 (o_wdata1),
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.o_rreg0 (o_rreg0),
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.o_rreg1 (o_rreg1),
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.i_rdata0 (i_rdata0),
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.i_rdata1 (i_rdata1),
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//Trap interface
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.i_trap (trap),
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.i_mret (mret),
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.i_mepc (wb_ibus_adr[0]),
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.i_mtval_pc (mtval_pc),
|
|
.i_bufreg_q (bufreg_q),
|
|
.i_bad_pc (bad_pc),
|
|
.o_csr_pc (csr_pc),
|
|
//CSR write port
|
|
.i_csr_en (csr_en),
|
|
.i_csr_addr (csr_addr),
|
|
.i_csr (csr_in),
|
|
//RD write port
|
|
.i_rd_wen (rd_en),
|
|
.i_rd_waddr (rd_addr),
|
|
.i_ctrl_rd (ctrl_rd),
|
|
.i_alu_rd (alu_rd),
|
|
.i_rd_alu_en (rd_alu_en),
|
|
.i_csr_rd (csr_rd),
|
|
.i_rd_csr_en (rd_csr_en),
|
|
.i_mem_rd (mem_rd),
|
|
.i_rd_mem_en (rd_mem_en),
|
|
|
|
//RS1 read port
|
|
.i_rs1_raddr (rs1_addr),
|
|
.o_rs1 (rs1),
|
|
//RS2 read port
|
|
.i_rs2_raddr (rs2_addr),
|
|
.o_rs2 (rs2),
|
|
|
|
//CSR read port
|
|
.o_csr (rf_csr_out));
|
|
|
|
serv_mem_if
|
|
#(.WITH_CSR (WITH_CSR[0:0]))
|
|
mem_if
|
|
(
|
|
.i_clk (clk),
|
|
//State
|
|
.i_bytecnt (mem_bytecnt),
|
|
.i_lsb (lsb),
|
|
.o_byte_valid (byte_valid),
|
|
.o_misalign (mem_misalign),
|
|
//Control
|
|
.i_mdu_op (mdu_op),
|
|
.i_signed (mem_signed),
|
|
.i_word (mem_word),
|
|
.i_half (mem_half),
|
|
//Data
|
|
.i_bufreg2_q (bufreg2_q),
|
|
.o_rd (mem_rd),
|
|
//External interface
|
|
.o_wb_sel (o_dbus_sel));
|
|
|
|
generate
|
|
if (|WITH_CSR) begin : gen_csr
|
|
serv_csr
|
|
#(.RESET_STRATEGY (RESET_STRATEGY))
|
|
csr
|
|
(
|
|
.i_clk (clk),
|
|
.i_rst (i_rst),
|
|
//State
|
|
.i_trig_irq (wb_ibus_ack),
|
|
.i_en (cnt_en),
|
|
.i_cnt0to3 (cnt0to3),
|
|
.i_cnt3 (cnt3),
|
|
.i_cnt7 (cnt7),
|
|
.i_cnt_done (cnt_done),
|
|
.i_mem_op (!mtval_pc),
|
|
.i_mtip (i_timer_irq),
|
|
.i_trap (trap),
|
|
.o_new_irq (new_irq),
|
|
//Control
|
|
.i_e_op (e_op),
|
|
.i_ebreak (ebreak),
|
|
.i_mem_cmd (o_dbus_we),
|
|
.i_mstatus_en (csr_mstatus_en),
|
|
.i_mie_en (csr_mie_en ),
|
|
.i_mcause_en (csr_mcause_en ),
|
|
.i_csr_source (csr_source),
|
|
.i_mret (mret),
|
|
.i_csr_d_sel (csr_d_sel),
|
|
//Data
|
|
.i_rf_csr_out (rf_csr_out),
|
|
.o_csr_in (csr_in),
|
|
.i_csr_imm (csr_imm),
|
|
.i_rs1 (rs1),
|
|
.o_q (csr_rd));
|
|
end else begin : gen_no_csr
|
|
assign csr_in = 1'b0;
|
|
assign csr_rd = 1'b0;
|
|
assign new_irq = 1'b0;
|
|
end
|
|
endgenerate
|
|
|
|
|
|
`ifdef RISCV_FORMAL
|
|
reg [31:0] pc = RESET_PC;
|
|
|
|
wire rs_en = two_stage_op ? init : ctrl_pc_en;
|
|
|
|
always @(posedge clk) begin
|
|
/* End of instruction */
|
|
rvfi_valid <= cnt_done & ctrl_pc_en & !i_rst;
|
|
rvfi_order <= rvfi_order + {63'd0,rvfi_valid};
|
|
|
|
/* Get instruction word when it's fetched from ibus */
|
|
if (wb_ibus_cyc & wb_ibus_ack)
|
|
rvfi_insn <= i_wb_rdt;
|
|
|
|
/* Store data written to rd */
|
|
if (o_wen0)
|
|
rvfi_rd_wdata <= {o_wdata0,rvfi_rd_wdata[31:1]};
|
|
|
|
if (cnt_done & ctrl_pc_en) begin
|
|
rvfi_pc_rdata <= pc;
|
|
if (!(rd_en & (|rd_addr))) begin
|
|
rvfi_rd_addr <= 5'd0;
|
|
rvfi_rd_wdata <= 32'd0;
|
|
end
|
|
end
|
|
rvfi_trap <= trap;
|
|
if (rvfi_valid) begin
|
|
rvfi_trap <= 1'b0;
|
|
pc <= rvfi_pc_wdata;
|
|
end
|
|
|
|
/* Not used */
|
|
rvfi_halt <= 1'b0;
|
|
rvfi_intr <= 1'b0;
|
|
rvfi_mode <= 2'd3;
|
|
rvfi_ixl = 2'd1;
|
|
|
|
/* RS1 not valid during J, U instructions (immdec_en[1]) */
|
|
/* RS2 not valid during I, J, U instructions (immdec_en[2]) */
|
|
if (i_rf_ready) begin
|
|
rvfi_rs1_addr <= !immdec_en[1] ? rs1_addr : 5'd0;
|
|
rvfi_rs2_addr <= !immdec_en[2] /*rs2_valid*/ ? rs2_addr : 5'd0;
|
|
rvfi_rd_addr <= rd_addr;
|
|
end
|
|
if (rs_en) begin
|
|
rvfi_rs1_rdata <= {!immdec_en[1] & rs1,rvfi_rs1_rdata[31:1]};
|
|
rvfi_rs2_rdata <= {!immdec_en[2] & rs2,rvfi_rs2_rdata[31:1]};
|
|
end
|
|
|
|
if (i_dbus_ack) begin
|
|
rvfi_mem_addr <= o_dbus_adr;
|
|
rvfi_mem_rmask <= o_dbus_we ? 4'b0000 : o_dbus_sel;
|
|
rvfi_mem_wmask <= o_dbus_we ? o_dbus_sel : 4'b0000;
|
|
rvfi_mem_rdata <= i_dbus_rdt;
|
|
rvfi_mem_wdata <= o_dbus_dat;
|
|
end
|
|
if (wb_ibus_ack) begin
|
|
rvfi_mem_rmask <= 4'b0000;
|
|
rvfi_mem_wmask <= 4'b0000;
|
|
end
|
|
end
|
|
/* verilator lint_off COMBDLY */
|
|
always @(wb_ibus_adr)
|
|
rvfi_pc_wdata <= wb_ibus_adr;
|
|
/* verilator lint_on COMBDLY */
|
|
|
|
|
|
`endif
|
|
|
|
generate
|
|
if (MDU) begin: gen_mdu
|
|
assign dbus_rdt = i_ext_ready ? i_ext_rd:i_dbus_rdt;
|
|
assign dbus_ack = i_dbus_ack | i_ext_ready;
|
|
end else begin : gen_no_mdu
|
|
assign dbus_rdt = i_dbus_rdt;
|
|
assign dbus_ack = i_dbus_ack;
|
|
end
|
|
assign o_ext_rs2 = o_dbus_dat;
|
|
endgenerate
|
|
|
|
endmodule
|
|
`default_nettype wire
|