mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-27 21:41:55 +01:00
237 lines
5.3 KiB
Systemverilog
237 lines
5.3 KiB
Systemverilog
interface n64_scb ();
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logic n64_reset;
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logic n64_nmi;
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logic bootloader_enabled;
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logic rom_write_enabled;
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logic rom_shadow_enabled;
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logic rom_extended_enabled;
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logic sram_enabled;
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logic sram_banked;
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logic flashram_enabled;
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logic dd_enabled;
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logic ddipl_enabled;
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logic eeprom_enabled;
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logic eeprom_16k_mode;
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logic dd_write;
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logic [6:0] dd_address;
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logic [15:0] dd_rdata;
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logic [15:0] dd_wdata;
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logic flashram_pending;
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logic flashram_done;
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logic [9:0] flashram_sector;
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logic flashram_sector_or_all;
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logic flashram_write_or_erase;
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logic flashram_read_mode;
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logic flashram_write;
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logic [5:0] flashram_address;
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logic [15:0] flashram_wdata;
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logic sram_done;
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logic eeprom_write;
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logic [10:0] eeprom_address;
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logic [7:0] eeprom_rdata;
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logic [7:0] eeprom_wdata;
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logic rtc_pending;
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logic rtc_done;
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logic rtc_wdata_valid;
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logic [41:0] rtc_rdata;
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logic [41:0] rtc_wdata;
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logic cfg_unlock;
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logic cfg_pending;
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logic cfg_done;
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logic cfg_error;
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logic cfg_irq;
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logic [7:0] cfg_cmd;
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logic [31:0] cfg_rdata [0:1];
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logic [31:0] cfg_wdata [0:1];
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logic [31:0] cfg_identifier;
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logic [15:0] save_count;
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logic cic_invalid_region;
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logic cic_disabled;
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logic cic_64dd_mode;
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logic cic_region;
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logic [7:0] cic_seed;
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logic [47:0] cic_checksum;
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logic pi_sdram_active;
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logic pi_flash_active;
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logic [35:0] pi_debug;
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modport controller (
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input n64_reset,
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input n64_nmi,
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output bootloader_enabled,
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output rom_write_enabled,
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output rom_shadow_enabled,
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output rom_extended_enabled,
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output sram_enabled,
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output sram_banked,
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output flashram_enabled,
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output dd_enabled,
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output ddipl_enabled,
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output eeprom_enabled,
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output eeprom_16k_mode,
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input flashram_pending,
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output flashram_done,
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input flashram_sector,
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input flashram_sector_or_all,
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input flashram_write_or_erase,
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input rtc_pending,
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output rtc_done,
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output rtc_wdata_valid,
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input rtc_rdata,
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output rtc_wdata,
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input cfg_pending,
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output cfg_done,
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output cfg_error,
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output cfg_irq,
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input cfg_cmd,
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input cfg_rdata,
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output cfg_wdata,
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output cfg_identifier,
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input save_count,
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input cic_invalid_region,
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output cic_disabled,
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output cic_64dd_mode,
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output cic_region,
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output cic_seed,
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output cic_checksum,
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input pi_debug
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);
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modport pi (
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output n64_reset,
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output n64_nmi,
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input bootloader_enabled,
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input rom_write_enabled,
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input rom_shadow_enabled,
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input rom_extended_enabled,
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input sram_enabled,
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input sram_banked,
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input flashram_enabled,
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input dd_enabled,
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input ddipl_enabled,
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output sram_done,
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input flashram_read_mode,
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input cfg_unlock,
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output pi_sdram_active,
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output pi_flash_active,
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output pi_debug
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);
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modport flashram (
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output flashram_pending,
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input flashram_done,
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output flashram_sector,
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output flashram_sector_or_all,
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output flashram_write_or_erase,
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output flashram_read_mode,
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output flashram_write,
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output flashram_address,
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output flashram_wdata
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);
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modport si (
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input eeprom_enabled,
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input eeprom_16k_mode,
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output eeprom_write,
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output eeprom_address,
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input eeprom_rdata,
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output eeprom_wdata,
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output rtc_pending,
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input rtc_done,
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input rtc_wdata_valid,
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output rtc_rdata,
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input rtc_wdata
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);
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modport dd (
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input n64_reset,
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input n64_nmi,
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output dd_write,
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output dd_address,
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input dd_rdata,
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output dd_wdata
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);
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modport bram (
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input flashram_write,
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input flashram_address,
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input flashram_wdata,
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input eeprom_write,
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input eeprom_address,
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output eeprom_rdata,
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input eeprom_wdata,
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input dd_write,
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input dd_address,
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output dd_rdata,
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input dd_wdata
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);
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modport cfg (
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input n64_reset,
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input n64_nmi,
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output cfg_unlock,
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output cfg_pending,
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input cfg_done,
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input cfg_error,
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input cfg_irq,
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output cfg_cmd,
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output cfg_rdata,
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input cfg_wdata,
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input cfg_identifier
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);
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modport save_counter (
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input eeprom_write,
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input sram_done,
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input flashram_done,
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output save_count
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);
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modport cic (
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output cic_invalid_region,
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input cic_disabled,
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input cic_64dd_mode,
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input cic_region,
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input cic_seed,
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input cic_checksum
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);
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modport arbiter (
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input pi_sdram_active,
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input pi_flash_active
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);
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endinterface
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