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27 lines
526 B
Systemverilog
27 lines
526 B
Systemverilog
package sc64;
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typedef enum bit [2:0] {
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ID_N64_SDRAM,
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ID_N64_BOOTLOADER,
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ID_N64_FLASHRAM,
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ID_N64_DDREGS,
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ID_N64_CPU,
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__ID_N64_END
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} e_n64_id;
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typedef enum bit [3:0] {
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ID_CPU_RAM,
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ID_CPU_BOOTLOADER,
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ID_CPU_GPIO,
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ID_CPU_I2C,
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ID_CPU_USB,
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ID_CPU_UART,
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__ID_CPU_END
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} e_cpu_id;
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parameter CLOCK_FREQUENCY = 100_000_000;
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parameter UART_BAUD_RATE = 1_000_000;
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endpackage
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