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27 lines
725 B
Systemverilog
27 lines
725 B
Systemverilog
module cpu_rom (
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if_system.sys system_if,
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if_cpu_bus_out cpu_bus_if,
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if_cpu_bus_in cpu_rom_if
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);
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wire request;
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wire ack;
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wire [31:0] rdata;
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assign request = (cpu_bus_if.address[31:24] == 8'h03) && cpu_bus_if.req;
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assign cpu_rom_if.ack = ack & request;
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assign cpu_rom_if.rdata = cpu_rom_if.ack ? rdata : 32'd0;
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intel_flash intel_flash_inst (
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.clock(system_if.clk),
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.avmm_data_addr(cpu_bus_if.address[17:2]),
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.avmm_data_read(request),
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.avmm_data_readdata(rdata),
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.avmm_data_waitrequest(),
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.avmm_data_readdatavalid(ack),
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.avmm_data_burstcount(2'd1),
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.reset_n(~system_if.reset)
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);
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endmodule
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