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44 lines
1.2 KiB
Systemverilog
44 lines
1.2 KiB
Systemverilog
module cpu_bootloader (
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if_system.sys system_if,
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if_cpu_bus_out cpu_bus_if,
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if_cpu_bus_in cpu_bootloader_if
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);
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wire request;
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wire [31:0] rdata;
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cpu_bus_glue #(.ADDRESS(4'hF)) cpu_bus_glue_bootloader_inst (
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.*,
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.cpu_peripheral_if(cpu_bootloader_if),
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.request(request),
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.rdata(rdata)
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);
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always_comb begin
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case (cpu_bus_if.address[6:2])
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0: rdata = 32'hb0000737;
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1: rdata = 32'h00074783;
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2: rdata = 32'h0027f793;
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3: rdata = 32'hfe078ce3;
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4: rdata = 32'h03e00793;
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5: rdata = 32'h00f70423;
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6: rdata = 32'hb00006b7;
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7: rdata = 32'h00000793;
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8: rdata = 32'h00006637;
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9: rdata = 32'h0006c703;
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10: rdata = 32'h00177713;
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11: rdata = 32'h00070a63;
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12: rdata = 32'h0046c703;
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13: rdata = 32'h00178793;
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14: rdata = 32'h0ff77713;
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15: rdata = 32'hfee78fa3;
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16: rdata = 32'hfec792e3;
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17: rdata = 32'h10000097;
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18: rdata = 32'hfbc080e7;
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19: rdata = 32'hfd9ff06f;
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default: rdata = 32'h0000_0000;
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endcase
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end
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endmodule
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