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https://github.com/Polprzewodnikowy/SummerCart64.git
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42 lines
1.1 KiB
Systemverilog
42 lines
1.1 KiB
Systemverilog
module cpu_gpio (
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if_system.sys system_if,
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if_cpu_bus_out cpu_bus_if,
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if_cpu_bus_in cpu_gpio_if,
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input [7:0] gpio_i,
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output reg [7:0] gpio_o,
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output reg [7:0] gpio_oe
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);
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wire request;
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wire [31:0] rdata;
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cpu_bus_glue #(.ADDRESS(4'hE)) cpu_bus_glue_gpio_inst (
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.*,
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.cpu_peripheral_if(cpu_gpio_if),
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.request(request),
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.rdata(rdata)
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);
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reg [7:0] gpio_i_ff1, gpio_i_ff2;
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reg [7:0] gpio_o_value;
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reg [7:0] gpio_oe_value;
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assign rdata = {8'd0, gpio_oe_value, gpio_i_ff2, gpio_o_value};
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always_ff @(posedge system_if.clk) begin
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{gpio_i_ff2, gpio_i_ff1} <= {gpio_i_ff1, gpio_i};
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gpio_o <= gpio_o_value;
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gpio_oe <= gpio_oe_value;
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if (system_if.reset) begin
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gpio_o_value <= 8'd0;
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gpio_oe_value <= 8'd0;
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end else if (request) begin
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if (cpu_bus_if.wstrb[0]) gpio_o_value <= cpu_bus_if.wdata[7:0];
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if (cpu_bus_if.wstrb[2]) gpio_oe_value <= cpu_bus_if.wdata[23:16];
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end
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end
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endmodule
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