mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2025-01-28 04:15:26 +01:00
ff69030643
* isv support + usb/dd improvements * make room for saves * update offset * fixed debug address * idk * exception * ironed out all broken stuff * cleanup * return epc fix * better * more cleanup * even more cleanup * mooore cleanup * fixed printf * no assert * improved docker build, pyft232 instead of pyserial * fixed displaying long message strings description test * just straight cleanup * smallest cleanup * PAL * cpu buffer * n64 bootloader done * super slow usb storage reading implemented * reduced buffer size * usb gets fast * little cleanup * double buffered reads * removed separate event id * ISV in hardware finally * small exception changes * mac testing * py spacing * fsd write, rtc, isv and reset fixes * fixxx * good stopping point * usb fixed? * pretend we have 128 MB sdram * backup * chmod * test * test done * more tests * user rm * help * final fix * updated component values * nice asset names * cic 64dd support * ddipl enable separation * pre DMA rewrite, created dedicated buffer memory space, simplified code * dma rewrite, needs testing * moved xml * dd basics * timing * 64dd working yet again, isv brought back, dma fixes, usb path rewrite, pc code rewrite * added usb read functionality, general cleanup * changed mem addressing * added fpga flash update access * added mcu update * chmod * little cleanup * update format and stuff * fixes * uninitialized fix * small fixes * update fixes * update stuff done * fpga update tested * build time fix * boot fix * test timing * readme test * test 2 * reports * testseet * final * build test * forgot * button and naming * General cleanup And multiline commit message test * Exception screen UI touch ups * display separation and tests beginning * pc software update * pc software done * timing test * delete launch.json * sw fixes * fixed button hole diameter in shell * small cleanup, rpi testing * shell fillet fix, pc rtc printing * added cfg lock mechanism * moved lock to cfg address space * extended ROM and ISV fixes * preliminary sd card support * little sd card cleanup * sd menu fixes * 5 second limit * reduced shell thickness * basic led act blinking * faster sd menu loading * inst cache invalidate * sd card writing is working * SD card CSD and CID registers * wait for previous command * led error codes * fixed cfg_translate_address use * 64dd from sd card working * 64dd speedup and button handling * delayed address latching cycle - might break other builds, needs testing * bootloader improvements * small fixes * return previous cfg when setting new * cache stuff * unfloader debug protocol support * UNFLoader style debug command line support * requirements.txt * shell groove fillet * reset state inside controller * fixed fast PI read, added PI R/W fifo debug info * PI access prioritize * SD clock stop when RX FIFO is more than half full * flash erase method change * CFG error handling, TLOZ MM debug ISV support * CIC5167 support * general fixes * USB unplugged cable handling * turn off led when changing between error/act modes * rtc 2 bit clock stop support * line endings * Revert "line endings" This reverts commit d0ddfe5ec716d2db7c72561703f51a94bf34e6bb. * PI address debug * readme test * diagram update * diagram background * diagram background * diagram background * updated readme
236 lines
6.2 KiB
ArmAsm
236 lines
6.2 KiB
ArmAsm
#include "vr4300.h"
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#define WATCHDOG_TIMEOUT (5 * (93750000UL / 2))
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#define VECTOR_LOCATION (0xA0000000UL)
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#define VECTOR_SIZE (0x80)
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#define VECTOR_NUM (4)
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#define AT_OFFSET (8)
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#define V0_OFFSET (16)
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#define V1_OFFSET (24)
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#define A0_OFFSET (32)
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#define A1_OFFSET (40)
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#define A2_OFFSET (48)
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#define A3_OFFSET (56)
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#define T0_OFFSET (64)
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#define T1_OFFSET (72)
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#define T2_OFFSET (80)
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#define T3_OFFSET (88)
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#define T4_OFFSET (96)
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#define T5_OFFSET (104)
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#define T6_OFFSET (112)
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#define T7_OFFSET (120)
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#define S0_OFFSET (128)
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#define S1_OFFSET (136)
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#define S2_OFFSET (144)
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#define S3_OFFSET (152)
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#define S4_OFFSET (160)
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#define S5_OFFSET (168)
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#define S6_OFFSET (176)
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#define S7_OFFSET (184)
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#define T8_OFFSET (192)
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#define T9_OFFSET (200)
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#define K0_OFFSET (208)
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#define K1_OFFSET (216)
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#define GP_OFFSET (224)
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#define SP_OFFSET (232)
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#define S8_OFFSET (240)
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#define RA_OFFSET (248)
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#define C0_STATUS_OFFSET (256)
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#define C0_CAUSE_OFFSET (260)
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#define C0_EPC_OFFSET (264)
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#define C0_BADVADDR_OFFSET (272)
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#define SAVE_REGISTERS_SIZE (280)
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.section .text.exception_handler
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exception_handler:
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.set noat
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la $k0, (_esp - SAVE_REGISTERS_SIZE)
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sd $at, AT_OFFSET($k0)
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sd $v0, V0_OFFSET($k0)
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sd $v1, V1_OFFSET($k0)
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sd $a0, A0_OFFSET($k0)
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sd $a1, A1_OFFSET($k0)
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sd $a2, A2_OFFSET($k0)
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sd $a3, A3_OFFSET($k0)
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sd $t0, T0_OFFSET($k0)
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sd $t1, T1_OFFSET($k0)
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sd $t2, T2_OFFSET($k0)
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sd $t3, T3_OFFSET($k0)
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sd $t4, T4_OFFSET($k0)
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sd $t5, T5_OFFSET($k0)
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sd $t6, T6_OFFSET($k0)
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sd $t7, T7_OFFSET($k0)
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sd $s0, S0_OFFSET($k0)
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sd $s1, S1_OFFSET($k0)
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sd $s2, S2_OFFSET($k0)
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sd $s3, S3_OFFSET($k0)
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sd $s4, S4_OFFSET($k0)
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sd $s5, S5_OFFSET($k0)
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sd $s6, S6_OFFSET($k0)
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sd $s7, S7_OFFSET($k0)
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sd $t8, T8_OFFSET($k0)
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sd $t9, T9_OFFSET($k0)
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sd $gp, GP_OFFSET($k0)
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sd $sp, SP_OFFSET($k0)
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sd $s8, S8_OFFSET($k0)
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sd $ra, RA_OFFSET($k0)
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.set at
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move $sp, $k0
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exception_check_type:
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mfc0 $a0, C0_CAUSE
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sw $a0, C0_CAUSE_OFFSET($k0)
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move $a1, $a0
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move $t0, $a0
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andi $t0, C0_CR_IP7
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andi $a0, C0_CR_EC_MASK
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srl $a0, $a0, C0_CR_EC_BIT
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andi $a1, C0_CR_IP_MASK
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srl $a1, $a1, C0_CR_IP_BIT
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bne $t0, $zero, exception_fatal
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beq $a0, $zero, exception_interrupt
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exception_fatal:
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sd $k0, K0_OFFSET($k0)
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sd $k1, K1_OFFSET($k0)
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mfc0 $t0, C0_STATUS
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sw $t0, C0_STATUS_OFFSET($k0)
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dmfc0 $t0, C0_EPC
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sd $t0, C0_EPC_OFFSET($k0)
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dmfc0 $t0, C0_BADVADDR
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sd $t0, C0_BADVADDR_OFFSET($k0)
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move $a2, $k0
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la $t1, exception_fatal_handler
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jalr $t1
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ld $t0, C0_EPC_OFFSET($k0)
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dmtc0 $t0, C0_EPC
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j exception_restore
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exception_interrupt:
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la $t1, exception_interrupt_handler
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jalr $t1
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exception_restore:
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.set noat
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ld $at, AT_OFFSET($k0)
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ld $v0, V0_OFFSET($k0)
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ld $v1, V1_OFFSET($k0)
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ld $a0, A0_OFFSET($k0)
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ld $a1, A1_OFFSET($k0)
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ld $a2, A2_OFFSET($k0)
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ld $a3, A3_OFFSET($k0)
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ld $t0, T0_OFFSET($k0)
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ld $t1, T1_OFFSET($k0)
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ld $t2, T2_OFFSET($k0)
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ld $t3, T3_OFFSET($k0)
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ld $t4, T4_OFFSET($k0)
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ld $t5, T5_OFFSET($k0)
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ld $t6, T6_OFFSET($k0)
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ld $t7, T7_OFFSET($k0)
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ld $s0, S0_OFFSET($k0)
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ld $s1, S1_OFFSET($k0)
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ld $s2, S2_OFFSET($k0)
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ld $s3, S3_OFFSET($k0)
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ld $s4, S4_OFFSET($k0)
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ld $s5, S5_OFFSET($k0)
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ld $s6, S6_OFFSET($k0)
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ld $s7, S7_OFFSET($k0)
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ld $t8, T8_OFFSET($k0)
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ld $t9, T9_OFFSET($k0)
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ld $gp, GP_OFFSET($k0)
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ld $sp, SP_OFFSET($k0)
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ld $s8, S8_OFFSET($k0)
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ld $ra, RA_OFFSET($k0)
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.set at
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eret
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.section .text.exception_vector
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exception_vector:
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.set noreorder
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la $k0, exception_handler
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jalr $k1, $k0
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nop
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.equ exception_vector_size, (. - exception_vector)
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.set reorder
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.section .text.exception_install
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exception_install:
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.global exception_install
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la $t0, exception_vector
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li $t1, VECTOR_LOCATION
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li $t2, (VECTOR_SIZE * VECTOR_NUM)
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add $t2, $t2, $t1
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1:
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move $t3, $t0
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move $t4, $t1
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li $t5, exception_vector_size
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add $t5, $t5, $t4
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2:
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lw $t6, 0($t3)
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addiu $t3, 4
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sw $t6, 0($t4)
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addiu $t4, 4
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bne $t4, $t5, 2b
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addiu $t1, VECTOR_SIZE
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bne $t1, $t2, 1b
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li $t0, VECTOR_LOCATION
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li $t1, (VECTOR_SIZE * VECTOR_NUM)
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add $t1, $t0, $t1
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3:
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cache HIT_INVALIDATE_I, 0($t0)
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addiu $t0, CACHE_LINE_SIZE_I
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bne $t0, $t1, 3b
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jr $ra
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.section .text.exception_enable_interrupts
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exception_enable_interrupts:
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.global exception_enable_interrupts
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mfc0 $t0, C0_STATUS
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li $t1, C0_SR_IE
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or $t0, $t0, $t1
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mtc0 $t0, C0_STATUS
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jr $ra
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.section .text.exception_disable_interrupts
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exception_disable_interrupts:
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.global exception_disable_interrupts
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mfc0 $t0, C0_STATUS
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li $t1, ~(C0_SR_IE)
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and $t0, $t0, $t1
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mtc0 $t0, C0_STATUS
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jr $ra
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.section .text.exception_enable_watchdog
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exception_enable_watchdog:
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.global exception_enable_watchdog
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mtc0 $zero, C0_COUNT
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li $t1, WATCHDOG_TIMEOUT
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mtc0 $t1, C0_COMPARE
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mfc0 $t0, C0_STATUS
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li $t1, C0_SR_IM7
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or $t0, $t0, $t1
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mtc0 $t0, C0_STATUS
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jr $ra
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.section .text.exception_disable_watchdog
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exception_disable_watchdog:
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.global exception_disable_watchdog
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mfc0 $t0, C0_STATUS
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li $t1, ~(C0_SR_IM7)
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and $t0, $t0, $t1
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mtc0 $t0, C0_STATUS
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mtc0 $zero, C0_COMPARE
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jr $ra
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