mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-04 02:44:15 +01:00
140 lines
3.7 KiB
Verilog
140 lines
3.7 KiB
Verilog
/*
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* PicoSoC - A simple example SoC using PicoRV32
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*
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* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module hx8kdemo (
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input clk,
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output ser_tx,
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input ser_rx,
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output [7:0] leds,
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output flash_csb,
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output flash_clk,
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inout flash_io0,
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inout flash_io1,
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inout flash_io2,
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inout flash_io3,
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output debug_ser_tx,
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output debug_ser_rx,
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output debug_flash_csb,
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output debug_flash_clk,
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output debug_flash_io0,
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output debug_flash_io1,
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output debug_flash_io2,
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output debug_flash_io3
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);
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reg [5:0] reset_cnt = 0;
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wire resetn = &reset_cnt;
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always @(posedge clk) begin
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reset_cnt <= reset_cnt + !resetn;
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end
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wire flash_io0_oe, flash_io0_do, flash_io0_di;
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wire flash_io1_oe, flash_io1_do, flash_io1_di;
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wire flash_io2_oe, flash_io2_do, flash_io2_di;
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wire flash_io3_oe, flash_io3_do, flash_io3_di;
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SB_IO #(
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.PIN_TYPE(6'b 1010_01),
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.PULLUP(1'b 0)
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) flash_io_buf [3:0] (
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.PACKAGE_PIN({flash_io3, flash_io2, flash_io1, flash_io0}),
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.OUTPUT_ENABLE({flash_io3_oe, flash_io2_oe, flash_io1_oe, flash_io0_oe}),
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.D_OUT_0({flash_io3_do, flash_io2_do, flash_io1_do, flash_io0_do}),
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.D_IN_0({flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di})
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);
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wire iomem_valid;
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reg iomem_ready;
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wire [3:0] iomem_wstrb;
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wire [31:0] iomem_addr;
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wire [31:0] iomem_wdata;
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reg [31:0] iomem_rdata;
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reg [31:0] gpio;
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assign leds = gpio;
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always @(posedge clk) begin
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if (!resetn) begin
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gpio <= 0;
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end else begin
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iomem_ready <= 0;
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if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
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iomem_ready <= 1;
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iomem_rdata <= gpio;
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if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
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if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
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if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
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if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
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end
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end
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end
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picosoc soc (
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.clk (clk ),
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.resetn (resetn ),
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.ser_tx (ser_tx ),
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.ser_rx (ser_rx ),
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.flash_csb (flash_csb ),
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.flash_clk (flash_clk ),
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.flash_io0_oe (flash_io0_oe),
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.flash_io1_oe (flash_io1_oe),
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.flash_io2_oe (flash_io2_oe),
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.flash_io3_oe (flash_io3_oe),
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.flash_io0_do (flash_io0_do),
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.flash_io1_do (flash_io1_do),
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.flash_io2_do (flash_io2_do),
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.flash_io3_do (flash_io3_do),
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.flash_io0_di (flash_io0_di),
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.flash_io1_di (flash_io1_di),
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.flash_io2_di (flash_io2_di),
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.flash_io3_di (flash_io3_di),
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.irq_5 (1'b0 ),
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.irq_6 (1'b0 ),
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.irq_7 (1'b0 ),
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.iomem_valid (iomem_valid ),
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.iomem_ready (iomem_ready ),
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.iomem_wstrb (iomem_wstrb ),
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.iomem_addr (iomem_addr ),
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.iomem_wdata (iomem_wdata ),
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.iomem_rdata (iomem_rdata )
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);
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assign debug_ser_tx = ser_tx;
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assign debug_ser_rx = ser_rx;
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assign debug_flash_csb = flash_csb;
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assign debug_flash_clk = flash_clk;
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assign debug_flash_io0 = flash_io0_di;
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assign debug_flash_io1 = flash_io1_di;
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assign debug_flash_io2 = flash_io2_di;
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assign debug_flash_io3 = flash_io3_di;
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endmodule
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