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37 lines
721 B
Systemverilog
37 lines
721 B
Systemverilog
module pll (
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input inclk,
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output logic reset,
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output clk,
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output sdram_clk
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);
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logic pll_sdram_clk;
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logic buf_sdram_clk;
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logic pll_lock;
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pll_lattice_generated pll_lattice_generated_inst (
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.CLKI(inclk),
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.CLKOP(clk),
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.CLKOS(pll_sdram_clk),
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.LOCK(pll_lock)
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);
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ODDRXE oddrxe_sdram_clk_inst (
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.D0(1'b1),
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.D1(1'b0),
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.SCLK(pll_sdram_clk),
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.RST(1'b0),
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.Q(buf_sdram_clk)
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);
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OB ob_sdram_clk_inst (
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.I(buf_sdram_clk),
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.O(sdram_clk)
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) /* synthesis IO_TYPE="LVCMOS33" */;
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always_ff @(posedge clk) begin
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reset <= ~pll_lock;
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end
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endmodule
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