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43 lines
1.4 KiB
Verilog
43 lines
1.4 KiB
Verilog
module n64_bank_decoder (
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input [31:0] i_address,
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output reg [25:0] o_translated_address,
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output reg [3:0] o_bank,
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output reg o_bank_prefetch
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);
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localparam [3:0] BANK_INVALID = 4'd0;
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localparam [3:0] BANK_ROM = 4'd1;
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localparam [3:0] BANK_CART = 4'd2;
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localparam [3:0] BANK_EEPROM = 4'd3;
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localparam [31:0] ROM_BASE = 32'h1000_0000;
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localparam [31:0] ROM_END = 32'h13FF_FFFF;
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localparam [31:0] CART_BASE = 32'h1E00_0000;
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localparam [31:0] CART_END = 32'h1EFF_FFFF;
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localparam [31:0] EEPROM_BASE = 32'h1D00_0000;
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localparam [31:0] EEPROM_END = 32'h1D00_07FF;
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always @(*) begin
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o_bank = BANK_INVALID;
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o_bank_prefetch = 1'b0;
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o_translated_address = i_address[25:0];
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if (i_address >= ROM_BASE && i_address <= ROM_END) begin
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o_translated_address = i_address - ROM_BASE;
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o_bank = BANK_ROM;
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o_bank_prefetch = 1'b1;
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end
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if (i_address >= CART_BASE && i_address <= CART_END) begin
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o_translated_address = i_address - CART_BASE;
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o_bank = BANK_CART;
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end
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if (i_address >= EEPROM_BASE && i_address <= EEPROM_END) begin
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o_translated_address = i_address - EEPROM_BASE;
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o_bank = BANK_EEPROM;
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o_bank_prefetch = 1'b1;
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end
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end
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endmodule
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