mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-22 14:09:16 +01:00
408 lines
11 KiB
Verilog
408 lines
11 KiB
Verilog
module top (
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input i_clk,
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output o_ftdi_clk,
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output o_ftdi_si,
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input i_ftdi_so,
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input i_ftdi_cts,
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input i_n64_nmi,
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input i_n64_reset,
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input i_n64_pi_alel,
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input i_n64_pi_aleh,
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input i_n64_pi_read,
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input i_n64_pi_write,
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inout [15:0] io_n64_pi_ad,
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input i_n64_si_clk,
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inout io_n64_si_dq,
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input i_n64_cic_clk,
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inout io_n64_cic_dq,
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output o_sdram_clk,
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output o_sdram_cs,
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output o_sdram_ras,
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output o_sdram_cas,
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output o_sdram_we,
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output [1:0] o_sdram_ba,
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output [12:0] o_sdram_a,
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inout [15:0] io_sdram_dq,
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output o_sd_clk,
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inout io_sd_cmd,
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inout [3:0] io_sd_dat,
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output o_flash_clk,
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output o_flash_cs,
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inout [3:0] io_flash_dq,
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output o_sram_clk,
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output o_sram_cs,
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inout [3:0] io_sram_dq,
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output o_rtc_scl,
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inout io_rtc_sda,
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output o_led,
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inout [7:0] io_pmod
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);
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// Clock and reset signals
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wire w_sys_clk;
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wire w_sdram_clk;
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wire w_pll_lock;
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wire w_sys_reset = ~w_pll_lock;
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// PLL clock generator
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pll sys_pll (
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.inclk0(i_clk),
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.c0(w_sys_clk),
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.c1(w_sdram_clk),
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.locked(w_pll_lock)
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);
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// SDRAM clock output
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gpio_ddro sdram_clk_ddro (
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.outclock(w_sdram_clk),
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.outclocken(1'b1),
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.din({1'b0, 1'b1}),
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.pad_out(o_sdram_clk)
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);
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// Bank ids
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localparam [3:0] BANK_INVALID = 4'd0;
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localparam [3:0] BANK_ROM = 4'd1;
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localparam [3:0] BANK_CART = 4'd2;
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localparam [3:0] BANK_EEPROM = 4'd3;
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// N64 PI
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wire w_n64_request;
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wire w_n64_write;
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wire w_n64_busy;
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wire w_n64_ack;
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wire [3:0] w_n64_bank;
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wire [25:0] w_n64_address;
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wire [31:0] w_n64_i_data;
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wire [31:0] w_n64_o_data;
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wire w_n64_busy_cart_control;
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wire w_n64_ack_cart_control;
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wire [31:0] w_n64_i_data_cart_control;
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wire w_n64_busy_sdram;
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wire w_n64_ack_sdram;
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wire [31:0] w_n64_i_data_sdram;
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wire w_n64_busy_embedded_flash;
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wire w_n64_ack_embedded_flash;
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wire [31:0] w_n64_i_data_embedded_flash;
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wire w_n64_busy_eeprom;
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wire w_n64_ack_eeprom;
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wire [31:0] w_n64_i_data_eeprom;
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always @(*) begin
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w_n64_busy = w_n64_busy_cart_control || w_n64_busy_sdram || w_n64_busy_embedded_flash || w_n64_busy_eeprom;
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w_n64_ack = w_n64_ack_cart_control || w_n64_ack_sdram || w_n64_ack_embedded_flash || w_n64_ack_eeprom;
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w_n64_i_data = 32'h0000_0000;
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if (w_n64_ack_cart_control) w_n64_i_data = w_n64_i_data_cart_control;
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if (w_n64_ack_sdram) w_n64_i_data = w_n64_i_data_sdram;
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if (w_n64_ack_embedded_flash) w_n64_i_data = w_n64_i_data_embedded_flash;
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if (w_n64_ack_eeprom) w_n64_i_data = w_n64_i_data_eeprom;
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end
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n64_pi n64_pi_inst (
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.i_clk(w_sys_clk),
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.i_reset(w_sys_reset),
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.i_n64_reset(i_n64_reset),
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.i_n64_pi_alel(i_n64_pi_alel),
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.i_n64_pi_aleh(i_n64_pi_aleh),
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.i_n64_pi_read(i_n64_pi_read),
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.i_n64_pi_write(i_n64_pi_write),
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.io_n64_pi_ad(io_n64_pi_ad),
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.o_request(w_n64_request),
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.o_write(w_n64_write),
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.i_busy(w_n64_busy),
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.i_ack(w_n64_ack),
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.o_bank(w_n64_bank),
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.o_address(w_n64_address),
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.i_data(w_n64_i_data),
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.o_data(w_n64_o_data)
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);
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// PC USB
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wire w_pc_request;
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wire w_pc_write;
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wire w_pc_busy;
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wire w_pc_ack;
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wire [3:0] w_pc_bank;
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wire [25:0] w_pc_address;
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wire [31:0] w_pc_i_data;
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wire [31:0] w_pc_o_data;
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wire w_pc_busy_cart_control;
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wire w_pc_ack_cart_control;
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wire [31:0] w_pc_i_data_cart_control;
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wire w_pc_busy_sdram;
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wire w_pc_ack_sdram;
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wire [31:0] w_pc_i_data_sdram;
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wire w_pc_busy_eeprom;
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wire w_pc_ack_eeprom;
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wire [31:0] w_pc_i_data_eeprom;
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always @(*) begin
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w_pc_busy = w_pc_busy_cart_control || w_pc_busy_sdram || w_pc_busy_eeprom;
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w_pc_ack = w_pc_ack_cart_control || w_pc_ack_sdram || w_pc_ack_eeprom;
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w_pc_i_data = 32'h0000_0000;
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if (w_pc_ack_cart_control) w_pc_i_data = w_pc_i_data_cart_control;
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if (w_pc_ack_sdram) w_pc_i_data = w_pc_i_data_sdram;
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if (w_pc_ack_eeprom) w_pc_i_data = w_pc_i_data_eeprom;
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end
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usb_pc usb_pc_inst (
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.i_clk(w_sys_clk),
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.i_reset(w_sys_reset),
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.o_ftdi_clk(o_ftdi_clk),
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.o_ftdi_si(o_ftdi_si),
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.i_ftdi_so(i_ftdi_so),
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.i_ftdi_cts(i_ftdi_cts),
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.o_request(w_pc_request),
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.o_write(w_pc_write),
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.i_busy(w_pc_busy),
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.i_ack(w_pc_ack),
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.o_bank(w_pc_bank),
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.o_address(w_pc_address),
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.i_data(w_pc_i_data),
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.o_data(w_pc_o_data)
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);
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// Cart interface
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wire w_cart_control_request;
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wire w_cart_control_write;
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wire w_cart_control_busy;
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wire w_cart_control_ack;
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wire [25:0] w_cart_control_address;
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wire [31:0] w_cart_control_o_data;
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wire [31:0] w_cart_control_i_data;
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wire w_rom_switch;
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wire w_eeprom_enable;
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wire w_eeprom_16k_mode;
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device_arbiter device_arbiter_cart_control_inst (
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.i_clk(w_sys_clk),
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.i_reset(w_sys_reset),
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.i_request_pri(w_n64_request),
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.i_write_pri(w_n64_write),
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.o_busy_pri(w_n64_busy_cart_control),
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.o_ack_pri(w_n64_ack_cart_control),
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.i_bank_pri(w_n64_bank),
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.i_address_pri(w_n64_address[25:2]),
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.o_data_pri(w_n64_i_data_cart_control),
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.i_data_pri(w_n64_o_data),
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.i_request_sec(w_pc_request),
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.i_write_sec(w_pc_write),
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.o_busy_sec(w_pc_busy_cart_control),
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.o_ack_sec(w_pc_ack_cart_control),
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.i_bank_sec(w_pc_bank),
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.i_address_sec(w_pc_address[25:2]),
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.o_data_sec(w_pc_i_data_cart_control),
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.i_data_sec(w_pc_o_data),
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.o_request(w_cart_control_request),
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.o_write(w_cart_control_write),
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.i_busy(w_cart_control_busy),
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.i_ack(w_cart_control_ack),
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.o_address(w_cart_control_address),
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.i_data(w_cart_control_o_data),
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.o_data(w_cart_control_i_data)
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);
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defparam device_arbiter_cart_control_inst.DEVICE_BANK = BANK_CART;
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cart_control cart_control_inst (
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.i_clk(w_sys_clk),
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.i_reset(w_sys_reset),
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.i_n64_reset(i_n64_reset),
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.i_n64_nmi(i_n64_nmi),
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.i_request(w_cart_control_request),
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.i_write(w_cart_control_write),
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.o_busy(w_cart_control_busy),
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.o_ack(w_cart_control_ack),
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.i_address(w_cart_control_address),
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.o_data(w_cart_control_o_data),
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.i_data(w_cart_control_i_data),
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.o_rom_switch(w_rom_switch),
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.o_eeprom_enable(w_eeprom_enable),
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.o_eeprom_16k_mode(w_eeprom_16k_mode)
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);
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// Embedded flash
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memory_embedded_flash memory_embedded_flash_inst (
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.i_clk(w_sys_clk),
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.i_reset(w_sys_reset),
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.i_request(!w_rom_switch && w_n64_request && !w_n64_write && w_n64_bank == BANK_ROM),
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.o_busy(w_n64_busy_embedded_flash),
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.o_ack(w_n64_ack_embedded_flash),
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.i_address(w_n64_address[25:2]),
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.o_data(w_n64_i_data_embedded_flash)
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);
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// SDRAM
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wire w_sdram_request;
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wire w_sdram_write;
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wire w_sdram_busy;
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wire w_sdram_ack;
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wire [25:0] w_sdram_address;
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wire [31:0] w_sdram_o_data;
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wire [31:0] w_sdram_i_data;
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device_arbiter device_arbiter_sdram_inst (
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.i_clk(w_sys_clk),
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.i_reset(w_sys_reset),
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.i_request_pri(w_rom_switch && w_n64_request),
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.i_write_pri(w_n64_write),
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.o_busy_pri(w_n64_busy_sdram),
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.o_ack_pri(w_n64_ack_sdram),
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.i_bank_pri(w_n64_bank),
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.i_address_pri(w_n64_address[25:1]),
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.o_data_pri(w_n64_i_data_sdram),
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.i_data_pri(w_n64_o_data),
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.i_request_sec(w_pc_request),
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.i_write_sec(w_pc_write),
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.o_busy_sec(w_pc_busy_sdram),
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.o_ack_sec(w_pc_ack_sdram),
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.i_bank_sec(w_pc_bank),
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.i_address_sec(w_pc_address[25:1]),
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.o_data_sec(w_pc_i_data_sdram),
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.i_data_sec(w_pc_o_data),
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.o_request(w_sdram_request),
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.o_write(w_sdram_write),
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.i_busy(w_sdram_busy),
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.i_ack(w_sdram_ack),
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.o_address(w_sdram_address),
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.i_data(w_sdram_o_data),
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.o_data(w_sdram_i_data)
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);
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defparam device_arbiter_sdram_inst.DEVICE_BANK = BANK_ROM;
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memory_sdram memory_sdram_inst (
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.i_clk(w_sys_clk),
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.i_reset(w_sys_reset),
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.o_sdram_cs(o_sdram_cs),
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.o_sdram_ras(o_sdram_ras),
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.o_sdram_cas(o_sdram_cas),
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.o_sdram_we(o_sdram_we),
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.o_sdram_ba(o_sdram_ba),
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.o_sdram_a(o_sdram_a),
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.io_sdram_dq(io_sdram_dq),
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.i_request(w_sdram_request),
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.i_write(w_sdram_write),
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.o_busy(w_sdram_busy),
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.o_ack(w_sdram_ack),
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.i_address(w_sdram_address),
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.o_data(w_sdram_o_data),
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.i_data(w_sdram_i_data)
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);
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// EEPROM 4/16k
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wire w_eeprom_request;
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wire w_eeprom_write;
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wire w_eeprom_busy;
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wire w_eeprom_ack;
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wire [25:0] w_eeprom_address;
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wire [31:0] w_eeprom_o_data;
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wire [31:0] w_eeprom_i_data;
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device_arbiter device_arbiter_eeprom_inst (
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.i_clk(w_sys_clk),
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.i_reset(w_sys_reset),
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.i_request_pri(w_n64_request),
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.i_write_pri(w_n64_write),
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.o_busy_pri(w_n64_busy_eeprom),
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.o_ack_pri(w_n64_ack_eeprom),
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.i_bank_pri(w_n64_bank),
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.i_address_pri(w_n64_address[25:2]),
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.o_data_pri(w_n64_i_data_eeprom),
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.i_data_pri(w_n64_o_data),
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.i_request_sec(w_pc_request),
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.i_write_sec(w_pc_write),
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.o_busy_sec(w_pc_busy_eeprom),
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.o_ack_sec(w_pc_ack_eeprom),
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.i_bank_sec(w_pc_bank),
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.i_address_sec(w_pc_address[25:2]),
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.o_data_sec(w_pc_i_data_eeprom),
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.i_data_sec(w_pc_o_data),
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.o_request(w_eeprom_request),
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.o_write(w_eeprom_write),
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.i_busy(w_eeprom_busy),
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.i_ack(w_eeprom_ack),
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.o_address(w_eeprom_address),
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.i_data(w_eeprom_o_data),
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.o_data(w_eeprom_i_data)
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);
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defparam device_arbiter_eeprom_inst.DEVICE_BANK = BANK_EEPROM;
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n64_si n64_si_inst (
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.i_clk(w_sys_clk),
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.i_reset(w_sys_reset),
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.i_n64_reset(i_n64_reset),
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.i_n64_si_clk(i_n64_si_clk),
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.io_n64_si_dq(io_n64_si_dq),
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.i_request(w_eeprom_request),
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.i_write(w_eeprom_write),
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.o_busy(w_eeprom_busy),
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.o_ack(w_eeprom_ack),
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.i_address(w_eeprom_address),
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.i_data(w_eeprom_i_data),
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.o_data(w_eeprom_o_data),
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.i_eeprom_enable(w_eeprom_enable),
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.i_eeprom_16k_mode(w_eeprom_16k_mode)
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);
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endmodule
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